UPD8884A

DATA SHEET MOS INTEGRATED CIRCUIT μ PD8884A (10680 PIXELS × 4 LINES) × 3 COLOR CCD LINEAR IMAGE SENSOR DESCRIPTION The μ PD8884A is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to electrical signal and has the function of color separation. The μ PD8884A has 3 rows of (10680 × 4) staggered pixels, and each row has a dual-sided readout-type charge transfer register. And it has reset feed-through level clamp circuits and voltage amplifiers. Therefore, it is suitable for 4800 dpi/A4 color image scanners. FEATURES • Valid photocell • Photocell’s size • Line spacing • Color filter • Resolution : (10680 pixels × 4) × 3 : 4 μm : Quad staggered pixels 96 μ m (24 lines) Red line - Green line, Green line - Blue line : Primary colors (red, green and blue), pigment filter (with light resistance 10 lx•hour) : 192 dot/mm A4 (210 × 297 mm) size (shorter side) 4800 dpi US letter (8.5” × 11”) size (shorter side) • Drive clock level : CMOS output under 5 V operation • Data rate • Power supply • On-chip circuits : 5.0 MHz Max. : +12 V : Reset feed-through level clamp circuits Voltage amplifiers 7 ORDERING INFORMATION Part Number Package CCD linear image sensor 32-pin plastic DIP (10.16 mm (400)) μ PD8884ACY-A Remark The μ PD8884ACY-A is a lead-free product. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. S17546EJ1V0DS00 (1st edition) Date Published May 2005 NS CP (K) Printed in Japan 2005 μ PD8884A BLOCK DIAGRAM VOD GND GND 29 14 4 φ SEL2 30 φ 2-2 φ 1-2 11 22 Drain gate Transfer gate CCD analog shift register Transfer gate Photocell (Blue) Transfer gate CCD analog shift register Transfer gate Drain gate Drain gate Transfer gate CCD analog shift register Transfer gate Photocell (Green) Transfer gate CCD analog shift register Transfer gate Drain gate Drain gate Transfer gate CCD analog shift register Transfer gate Photocell (Red) Transfer gate CCD analog shift register Transfer gate Drain gate 2 3 5 28 19 15 VOUT1 31 (Blue) 18 φTG1 (Blue) VOUT2 32 (Green) 17 φ TG2 (Green) VOUT3 1 (Red) 16 φ TG3 (Red) φ CLB φ RB φ 2-1 φ 1-1 φ SEL1 φ SEL3 2 Data Sheet S17546EJ1V0DS μ PD8884A PIN CONFIGURATION (Top View) CCD linear image sensor 32-pin plastic DIP (10.16 mm (400)) • μ PD8884ACY-A Output signal 3 (Red) Reset feed-through level clamp clock Reset gate clock Ground Shift register clock 2-1 Internal connection Internal connection No connection No connection No connection Shift register clock 2-2 Internal connection Internal connection Ground VOUT3 φ CLB φ RB 1 2 1 1 1 32 31 30 29 28 27 26 25 24 23 22 21 20 21360 × 2 21360 × 2 21360 × 2 VOUT2 VOUT1 Output signal 2 (Green) Output signal 1 (Blue) 3 4 5 6 7 8 Red φ SEL2 Dpi selector 2 GND VOD φ 1-1 Output drain voltage Shift register clock 1-1 Internal connection Internal connection No connection No connection No connection Shift register clock 1-2 Internal connection Internal connection φ 2-1 IC IC NC NC NC IC IC NC NC NC φ 1-2 Green 9 10 11 12 13 14 15 16 φ 2-2 IC IC GND Blue IC IC 19 18 17 φ SEL1 Dpi selector 1 φ TG1 φ TG2 Dpi selector 3 φ SEL3 Transfer gate clock 3 (for Red) Transfer gate clock 1 (for Blue) Transfer gate clock 2 (for Green) φ TG3 Cautions 1. Leave pins 6, 7, 12, 13, 20, 21, 26, 27 (IC) unconnected. 2. Connect the No connection pins (NC) to GND. Data Sheet S17546EJ1V0DS 3 μ PD8884A PHOTOCELL STRUCTURE DIAGRAM (4800 dpi, for each color) 4 μm 2 6 10 14 18 22 3.0 μ m 1.0 μ m CCD 33.5 μ m 1 5 9 13 17 21 8 μm 3 7 11 15 19 23 CCD 33.5 μ m 4 8 12 16 20 24 4 Data Sheet S17546EJ1V0DS μ PD8884A PHOTOCELL ARRAY STRUCTURE DIAGRAM-1 (Line spacing) Drain gate Blue photocell array CCD analog shift register 4 μm 4 μm 4 μm Resolution Select 4 μm Blue photocell array Blue photocell array CCD analog shift register Blue photocell array Drain gate Drain gate Blue photocell array CCD analog shift register 4 μm 4 μm 4 μm Resolution Select 4 μm Blue photocell array Blue photocell array CCD analog shift register Blue photocell array Drain gate Drain gate Blue photocell array CCD analog shift register 4 μm 4 μm 4 μm Resolution Select 4 μm Blue photocell array Blue photocell array CCD analog shift register Blue photocell array Drain gate (33.5 μ m) 2 lines (8 μ m) (33.5 μ m) 4 μm 24 lines (96 μ m) (21 μ m) 4 μm (33.5 μ m) 2 lines (8 μ m) (33.5 μ m) 271 μ m 24 lines (96 μ m) (21 μ m) 4 μm (33.5 μ m) 2 lines (8 μ m) (33.5 μ m) PHOTOCELL ARRAY STRUCTURE DIAGRAM-2 (Dummy, OB, for each color) Dummy (160 pixels) 4800 dpi 2 158 162 Optical black (192 pixels) Invalid photocell (16 pixels) 350 354 358 362 366 370 374 Valid photocell (42720 pixels) 43082 43086 Invalid photocell (8 pixels) 1 2400 dpi 3 157 161 349 353 357 361 365 369 373 43081 43085 159 163 351 355 359 363 367 371 375 43083 43087 4800 dpi 4 160 164 352 356 360 364 368 372 376 43084 43088 Data Sheet S17546EJ1V0DS 5 μ PD8884A ABSOLUTE MAXIMUM RATINGS (TA = +25°C) Parameter Output drain voltage Shift register clock voltage Reset gate clock voltage Reset feed-through level clamp clock voltage Dpi select signal voltage Transfer gate clock voltage Operating ambient temperature Storage temperature Note Symbol VOD Vφ 1, Vφ 2 V φ RB Vφ CLB Vφ SEL1 to Vφ SEL3 Vφ TG1 to Vφ TG3 TA Tstg Ratings −0.3 to +15 −0.3 to +8 −0.3 to +8 −0.3 to +8 −0.3 to +8 −0.3 to +8 0 to +60 −40 to +70 Unit V V V V V V °C °C Note Use at the condition without dew condensation. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. RECOMMENDED OPERATING CONDITIONS (TA = +25°C) Parameter Output drain voltage Shift register clock high level Shift register clock low level Reset gate clock high level Reset gate clock low level Reset feed-through level clamp clock high level Reset feed-through level clamp clock low level Dpi select signal high level Dpi select signal low level Transfer gate clock high level Transfer gate clock low level Data rate Clock pulse frequency VOD Vφ 1H, Vφ 2H Vφ 1L, Vφ 2L Vφ RBH Vφ RBL Vφ CLBH Vφ CLBL Vφ SEL1H to Vφ SEL3H Vφ SEL1L to Vφ SEL3L Vφ TG1H to Vφ TG3H Vφ TG1L to Vφ TG3L fφ RB fφ 1, fφ 2 Symbol Min. 11.5 4.75 −0.3 4.5 −0.3 4.5 −0.3 4.5 −0.3 4.5 −0.3 − − Typ. 12.0 5.0 0 5.0 0 5.0 0 5.0 0 5.0 0 2.0 1.0 Max. 12.5 5.5 +0.3 5.5 +0.3 5.5 +0.3 5.5 +0.3 5.5 +0.3 5.0 10.0 Unit V V V V V V V V V V V MHz MHz 6 Data Sheet S17546EJ1V0DS μ PD8884A ELECTRICAL CHARACTERISTICS TA = +25°C, VOD = 12 V, data rate (fφ RB) = 2 MHz, storage time = 11.0 ms, input signal clock = 5 Vp-p, light source : 3200 K halogen lamp + C-500S (infrared cut filter, t = 1 mm) + HA-50 (heat absorbing filter, t = 3 mm) Parameter Saturation voltage Saturation exposure Red Green Blue Photo response non-uniformity Average dark signal Dark signal non-uniformity Power consumption Output impedance Response Red Green Blue Offset level Note Symbol Vsat SER SEG SEB PRNU ADS DSNU PW ZO RR RG RB VOS TTE Red Green Blue Test Conditions Min. 2.3 − − − − − − − − 2.38 2.17 1.40 4.5 Typ. 2.7 0.79 0.87 1.35 6 0.1 2.0 380 0.4 3.40 3.10 2.00 6.0 98 630 540 460 0.05 1.0 1.0 1.0 −500 1.2 Max. − − − − 20 4.0 8.0 540 1.0 4.42 4.03 2.60 7.5 − − − − 3.0 6.0 6.0 6.0 +1000 − Unit V lx•s lx•s lx•s % mV mV mW kΩ V/lx•s V/lx•s V/lx•s V % nm nm nm % % % % mV mV VOUT = 1.0 V Light shielding Light shielding Total transfer efficiency Response peak VOUT = 1.0 V Clock pulse frequency = 10 MHz 92 − − − − − − − − − Image lag Response difference between inside and outside Potocell array imbalance Note IL RDIO PAIIN PAIOUT VOUT = 1.0 V VOUT = 1.0 V VOUT = 1.0 V VOUT = 1.0 V Light shielding Light shielding Reset feed-through noise Random noise (CDS) RFTN σ CDS Note Refer to TIMING CHART 2-1 to 2-3. Data Sheet S17546EJ1V0DS 7 μ PD8884A INPUT PIN CAPACITANCE (TA = +25°C, VOD = 12 V) Parameter Shift register clock pin capacitance 1 Shift register clock pin capacitance 2 Shift register clock pin capacitance 3 Shift register clock pin capacitance 4 Reset gate clock pin capacitance Reset feed-through level clamp clock pin capacitance Select signal and gain pin capacitance Symbol Cφ 1-1 Cφ 1-2 Cφ 2-1 Cφ 2-2 Cφ RB Cφ CLB Cφ SEL1 Cφ SEL2 Cφ SEL3 Transfer gate clock pin capacitance Cφ TG Pin name Pin No. 28 22 5 11 3 2 19 30 15 18 17 16 Min. − − − − − − − − − − − − Typ. 750 750 750 750 20 20 20 20 20 20 20 20 Max. − − − − − − − − − − − − Unit pF pF pF pF pF pF pF pF pF pF pF pF φ 1-1 φ 1-2 φ 2-1 φ 2-2 φ RB φ CLB φ SEL1 φ SEL2 φ SEL3 φ TG1 φ TG2 φ TG3 Remark Cφ 1-1 to Cφ 2-2 show the equivalent capacity of the real drive including the capacity of between each clock pin (φ 1-1, φ 1-2, φ 2-1 and φ 2-2). INPUT SIGNAL TABLE Mode φ SEL1 (Even-line enable switch) φ SEL2 (CCD-drain switch) φ SEL3 (TG-select switch) Note 4800 dpi High level High level High level High level High level High level Low level Low level Even-line electron read photodiode to CCD Odd-line electron read photodiode to CCD Odd-line electron read photodiode to CCD Even-line electron sink to drain 2400 dpi Low level 1200 dpi 600 dpi Low level Low level Low level 1, 5, 9, 13, … : Line photodiode use 2 to 4, 6 to 8, 10 to 12, … : Sink to drain 8 Data Sheet S17546EJ1V0DS TIMING CHART 1-1 (4800 dpi, for each color) Storage time (l2, l4) Storage time (l1, l3) φ TG1 to φ TG3 2400 dpi cycle Odd line read 2400 dpi cycle Even line read φ SEL3 φ SEL1, φ SEL2 “H” Data Sheet S17546EJ1V0DS φ 1-2400 φ 2-2400 21360 pixels Odd 2400 dpi Data read 21360 pixels Even 2400 dpi Data read 21360 pixels Odd 2400 dpi Data read 21360 pixels Even 2400 dpi Data read Remark Above means, storage time of each photocell array is “TG period × 2”. And storage time of (l1, l3) and (l2, l4) is a half overlap each other. μ PD8884A 9 VOUT1 to VOUT3 Optical black (96 pixels) Invalid photocell (8 pixels) Valid photocell (21360 pixels) 43083 43085 43087 43089 43091 43093 43095 157 159 161 163 347 349 351 353 365 367 369 371 1 3 5 7 9 11 10 Data Sheet S17546EJ1V0DS TIMING CHART 1-2 (2400 dpi, for each color) Storage time φ TG1 to φ TG3 φ1 φ2 φ RB Note Note φ CLB φ SEL1 φ SEL2 φ SEL3 “L” “H” “L” μ PD8884A Invalid photocell (4 pixels) Note Set the φ RB and the φ CLB to high level during this period. TIMING CHART 1-3 (1200 dpi, for each color) Storage time φ TG1 to φ TG3 φ1 φ2 φ RB Note Note φ CLB φ SEL1 φ SEL2 φ SEL3 VOUT1 to VOUT3 Optical black (48 pixels) Invalid photocell (4 pixels) Valid photocell (10680 pixels) 43081 43085 43089 43093 43097 153 157 161 165 345 349 353 357 361 365 369 373 1 5 9 13 17 21 Data Sheet S17546EJ1V0DS “L” “L” “L” μ PD8884A Invalid photocell (2 pixels) Note Set the φ RB and the φ CLB to high level during this period. 11 153+157 161+165 345+349 353+357 361+365 369+373 42973+ 42977 42981+ 42985 VOUT1 to VOUT3 Optical black (24 pixels) Valid photocell (5340 pixels) 42989+ 42993 9+13 1+5 12 Data Sheet S17546EJ1V0DS TIMING CHART 1-4 (600 dpi, for each color) Storage time φ TG1 to φ TG3 φ1 φ2 φ RB Note Note φ CLB φ SEL1 φ SEL2 φ SEL3 “L” “L” “L” μ PD8884A Invalid photocell (2 pixels) Invalid photocell (1 pixels) N Note Set the φ RB and the φ CLB to high level during this period. Remark 2 pixels data merge at the charge detected capacitance. μ PD8884A TIMING CHART 2-1 (4800 dpi / 2400 dpi, for each color) t1 t2 φ1 φ2 t5 t3 t6 t4 90% 10% 90% 10% t5 t3 t6 t4 φ RB 90% 10% t7 t9 t8 t10 t11 t7 t9 t8 t10 t11 φ CLB 90% 10% td RFTN td VOUT 10% VOS 10% Symbol t1, t2 t3 t4 t5, t6 t7 t8 t9, t10 t11 td Min. 0 20 40 0 −10 20 0 10 − Typ. 30 100 150 10 +25 100 10 25 15 Max. − − − − − − − − − Unit ns ns ns ns ns ns ns ns ns Data Sheet S17546EJ1V0DS 13 μ PD8884A TIMING CHART 2-2 (1200 dpi, for each color) t1 t2 φ1 φ2 t5 t3 t6 t4 90% 10% 90% 10% φ RB 90% 10% t7 t9 t8 t10 t11 φ CLB 90% 10% td RFTN VOUT 10% VOS Symbol t1, t2 t3 t4 t5, t6 t7 t8 t9, t10 t11 td Min. 0 20 40 0 −10 20 0 10 − Typ. 30 100 150 10 +25 100 10 25 15 Max. − − − − − − − − − Unit ns ns ns ns ns ns ns ns ns 14 Data Sheet S17546EJ1V0DS μ PD8884A TIMING CHART 2-3 (600 dpi, for each color) t1 t2 φ1 φ2 t5 t3 t6 t4 90% 10% 90% 10% φ RB 90% 10% t7 t9 t8 t10 t11 φ CLB 90% 10% td RFTN VOUT 10% VOS Symbol t1, t2 t3 t4 t5, t6 t7 t8 t9, t10 t11 td Min. 0 20 40 0 −10 20 0 10 − Typ. 30 100 150 10 +25 100 10 25 15 Max. − − − − − − − − − Unit ns ns ns ns ns ns ns ns ns Data Sheet S17546EJ1V0DS 15 μ PD8884A TIMING CHART 3 (readout) t13 t12 t14 φ TG1 to φ TG3 90% 10% t15 90% 10% t17 t16 φ SEL3 t18 φ1 φ2 90% t19 t20 φ RB, φ CLB 90% Symbol t12 t13, t14 t15, t16 t17 t18 t19, t20 Min. 8000 0 1000 1000 7000 500 Typ. 15000 50 2000 2000 10000 1000 Max. (50000) − − − − − Unit ns ns ns ns ns ns φ 1, φ 2 CROSS POINTS φ2 2.0 V or more 2.0 V or more φ1 Remark Adjust cross points of φ 1 and φ 2 with input resistance of each pin. 16 Data Sheet S17546EJ1V0DS μ PD8884A DEFINITIONS OF CHARACTERISTIC ITEMS 1. Saturation voltage : Vsat Output signal voltage at which the response linearity is lost. Photo pixel and CCD register electron saturate level. 2. Saturation exposure : SE Product of intensity of illumination (lx) and storage time (s) when saturation of output voltage occurs. 3. Photo response non-uniformity : PRNU The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of uniform illumination. PRNU of 4800 dpi is calculated by the following formula. PRNUIN (%) = Δx × 100 x PRNUOUT (%) = Δy × 100 y Δ x : maximum of ⎪xj − x ⎪ Δ x : maximum of ⎪yj − y ⎪ x= Σx j=1 IV IV j y= Σy j=1 IO IO j xj : Output voltage of valid pixel number j IV : Number of inside valid pixels (21360 bits) yj : Output voltage of valid pixel number j IO : Number of outside valid pixels (21360 bits) The following figure shows output waveform of 4800 dpi mode. VOUT Register Dark DC level x y Δx Δy Inside 2400 dpi data set Outnside 2400 dpi data set 4. Average dark signal : ADS Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula. Vaild pixels j=1 Σd j ADS (mV) = Valid pixels dj : Dark signal of valid pixel number j Data Sheet S17546EJ1V0DS 17 μ PD8884A 5. Dark signal non-uniformity : DSNU Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. This is calculated by the following formula. DSNU (mV) : maximum of ⎪dj − ADS ⎪j = 1 to Valid pixels dj : Dark signal of valid pixel number j VOUT ADS Register Dark DC level DSNU 6. Output impedance : ZO Impedance of the output pins viewed from outside. 7. Response : R Output voltage divided by exposure (lx•s). Note that the response varies with a light source (spectral characteristic). R of 4800 dpi is defined as following (refer to 3. Photo response non-uniformity). x RIN : ¯¯ divided by exposure (lx•s) y ROUT : ¯¯ divided by exposure (lx•s) 8. Image lag : IL The rate between the last output voltage and the next one after read out the data of a line. φ TG Light ON OFF VOUT V1 VOUT IL (%) = V1 × 100 VOUT 18 Data Sheet S17546EJ1V0DS μ PD8884A 9. Response difference between inside and outside : RDIO Difference of average output voltage between inside 2400 dpi and outside 2400 dpi (refer to 3. Photo response non-uniformity). 2⎪x−y⎪ × 100 x+y RDIO (%) = 10. Photocell array imbalance : PAI PAI is calculated by following formula (refer to 3. Photo response non-uniformity). n m 2 n PAIIN (%) = j=1 ∑ (x2j –1 – x2j) 1 n j=1 2 2 m × 100 PAIOUT (%) = j=1 ∑ (y2j –1 – y2j) 1 n j=1 2 ∑ xj n ∑ yj m × 100 xj : Output voltage of each pixel n : Number of valid pixels (21360 bits) yj : Output voltage of each pixel m : Number of valid pixels (21360 bits) 11. Offset level : VOS DC level of output signal is defined as follows. 12. Reset feed-through noise : RFTN Reset feed-through noise (RFTN) are defined as follows. RFTN VOUT VOS Data Sheet S17546EJ1V0DS 19 μ PD8884A 13. Random noise (CDS) : σ CDS Random noise σ CDS is defined as the standard deviation of a valid pixel output signal with 100 times (=100 lines) data sampling at dark (light shielding). σ CDS is calculated by the following procedure. 1. One valid photocell in one reading is fixed as measurement point. 2. The output level is measured during the reset feed-through period which is averaged over 100 ns to get “VDi”. 3. The output level is measured during the video output time averaged over 100 ns to get “VOi”. 4. The correlated double sampling output is defined by the following formula. VCDSi = VDi – VOi 5. Repeat the above procedure (1 to 4) for 100 times (= 100 lines). 6. Calculate the standard deviation σ CDS using the following formula equation. 100 σ CDS (mV) = Σ (VCDS – V) i=1 i 2 , V= 1 100 100 100 i = 1 Σ VCDS i The following figure shows output waveform (valid photocell under dark condition). Reset feed-through Video output 20 Data Sheet S17546EJ1V0DS μ PD8884A STANDARD CHARACTERISTIC CURVES (Reference Value) DARK OUTPUT TEMPERATURE CHARACTERISTIC 8 2 STORAGE TIME OUTPUT VOLTAGE CHARACTERISTIC (TA = +25°C) 4 Relative Output Voltage 2 1 0.5 0.25 0.1 0 10 20 30 40 50 Relative Output Voltage 1 0.2 0.1 1 5 Storage Time (ms) 10 Operating Ambient Temperature TA (°C) TOTAL SPECTRAL RESPONSE CHARACTERISTICS (without infrared cut filter and heat absorbing filter) (TA = +25°C) 100 R B 80 G Response Ratio (%) 60 40 G 20 B 0 400 500 600 Wavelength (nm) 700 800 Data Sheet S17546EJ1V0DS 21 μ PD8884A APPLICATION CIRCUIT EXAMPLE μ PD8884A 1 VOUT3 47 Ω VOUT2 31 VOUT1 B1 30 29 GND 5.1 Ω VOD 28 27 IC 7 IC 8 NC 9 NC 10 NC 5.1 Ω NC 11 12 IC 13 IC 14 GND 47 Ω 15 16 IC IC 20 19 18 17 47 Ω NC 23 22 21 5.1 Ω NC 24 IC 25 IC 26 5.1 Ω 47 Ω 0.1 μ F 47 μ F/25 V 2 3 4 5 6 32 B2 +12 V B3 + φ CLB 47 Ω φ CLB φ RB φ RB φ SEL2 φ SEL2 φ 2-1 φ 2-1 φ 1-1 φ 1-1 φ 2-2 φ 2-2 φ 1-2 φ 1-2 φ SEL1 φ SEL1 47 Ω 47 Ω φ SEL3 47 Ω φ SEL3 φ TG1 φ TG2 φ TG φ TG3 Cautions 1. Leave pins 6, 7, 12, 13, 20, 21, 26, 27 (IC) unconnected. 2. Connect the No connection pins (NC) to GND. Remarks 1. φ RB, φ CLB, φ TG1 to φ TG3 and φ SEL1 to φ SEL3 driving inverters shown in the above application circuit example are the 74HC04. φ 1-1 to φ 2-2 driving inverters shown in the above application circuit example are the 74HC04 (≤ 2.0 MHz) or the 74AC04 (> 2.0 MHz). 2. Inverters B1 to B3 in the above application circuit example are shown in the figure below. B1 to B3 EQUIVALENT CIRCUIT 12 V + 100 Ω CCD VOUT 47 μ F/25 V 100 Ω 2SC1842 2 kΩ 22 Data Sheet S17546EJ1V0DS μ PD8884A PACKAGE DRAWING μ PD8884ACY CCD LINEAR IMAGE SENSOR 32-PIN PLASTIC DIP (10.16 mm (400)) (Unit : mm) 55.2±0.5 54.8±0.5 1st valid pixel 5.85±0.3 32 1 17 1 46.7 12.6±0.5 4 16 2.0 4.1±0.5 4 9.05±0.3 9.25±0.3 10.16±0.20 (1.775) 2 1.02±0.15 4.55±0.5 2.725±0.3 0.46±0.1 2.54±0.25 (5.42) 4.21±0.5 0.25±0.05 3 10.16 + 0.70 − 0.20 Name Plastic cap Dimensions 52.2×6.4×0.8 (0.7 5) Refractive index 1.5 1 1st valid pixel The center of the pin1 2 The surface of the CCD chip The top of the cap 3 The bottom of the package The surface of the CCD chip 4 Mirror finishied surface 5 Thickness of mirror finished surface Data Sheet S17546EJ1V0DS 23 μ PD8884A RECOMMENDED SOLDERING CONDITIONS When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) Type of Through-hole Device μ PD8884ACY-A : CCD linear image sensor 32-pin plastic DIP (10.16 mm (400)) Process Partial heating method Conditions Pin temperature : 300 °C or below, Heat time : 3 seconds or less (per pin) Cautions 1. 2. During assembly care should be taken to prevent solder or flux from contacting the plastic cap. The optical characteristics could be degraded by such contact. Soldering by the solder flow method may have deleterious effects on prevention of plastic cap soiling and heat resistance. So the method cannot be guaranteed. 24 Data Sheet S17546EJ1V0DS μ PD8884A NOTES ON HANDLING THE PACKAGES 1 DUST AND DIRT PROTECTING The optical characteristics of the CCD will be degraded if the cap is scratched during cleaning. Don’t either touch plastic cap surface by hand or have any object come in contact with plastic cap surface. Should dirt stick to a plastic cap surface, blow it off with an air blower. For dirt stuck through electricity ionized air is recommended. And if the plastic cap surface is grease stained, clean with our recommended solvents. CLEANING THE PLASTIC CAP Care should be taken when cleaning the surface to prevent scratches. We recommend cleaning the cap with a soft cloth moistened with one of the recommended solvents below. Excessive pressure should not be applied to the cap during cleaning. If the cap requires multiple cleanings it is recommended that a clean surface or cloth be used. RECOMMENDED SOLVENTS The following are the recommended solvents for cleaning the CCD plastic cap. Use of solvents other than these could result in optical or physical degradation in the plastic cap. Please consult your sales office when considering an alternative solvent. Solvents Ethyl Alcohol Methyl Alcohol Isopropyl Alcohol N-methyl Pyrrolidone Symbol EtOH MeOH IPA NMP 2 MOUNTING OF THE PACKAGE The application of an excessive load to the package may cause the package to warp or break, or cause chips to come off internally. Particular care should be taken when mounting the package on the circuit board. Don't have any object come in contact with plastic cap. You should not reform the lead frame. We recommended to use a IC-inserter when you assemble to PCB. Also, be care that the any of the following can cause the package to crack or dust to be generated. 1. Applying heat to the external leads for an extended period of time with soldering iron. 2. Applying repetitive bending stress to the external leads. 3. Rapid cooling or heating 3 OPERATE AND STORAGE ENVIRONMENTS Operate in clean environments. CCD image sensors are precise optical equipment that should not be subject to mechanical shocks. Exposure to high temperatures or humidity will affect the characteristics. So avoid storage or usage in such conditions. Keep in a case to protect from dust and dirt. Dew condensation may occur on CCD image sensors when the devices are transported from a low-temperature environment to a high-temperature environment. Avoid such rapid temperature changes. For more details, refer to our document "Review of Quality and Reliability Handbook" (C12769E) 4 ELECTROSTATIC BREAKDOWN CCD image sensor is protected against static electricity, but destruction due to static electricity is sometimes detected. Before handling be sure to take the following protective measures. 1. 2. 3. 4. 5. 6. Ground the tools such as soldering iron, radio cutting pliers of or pincer. Install a conductive mat or on the floor or working table to prevent the generation of static electricity. Either handle bare handed or use non-chargeable gloves, clothes or material. Ionized air is recommended for discharge when handling CCD image sensor. For the shipment of mounted substrates, use box treated for prevention of static charges. Anyone who is handling CCD image sensors, mounting them on PCBs or testing or inspecting PCBs on which CCD image sensors have been mounted must wear anti-static bands such as wrist straps and ankle straps which are grounded via a series resistance connection of about 1 MΩ. Data Sheet S17546EJ1V0DS 25 μ PD8884A [MEMO] 26 Data Sheet S17546EJ1V0DS μ PD8884A N OTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. Data Sheet S17546EJ1V0DS 27 μ PD8884A • T he information in this document is current as of May, 2005. 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(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11-1