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NJW4140RT1-TE2

NJW4140RT1-TE2

  • 厂商:

    NJRC

  • 封装:

    LSSOP8

  • 描述:

    MOSFET DRIVE SWITCHING REGULATOR

  • 数据手册
  • 价格&库存
NJW4140RT1-TE2 数据手册
NJW4140 MOSFET Drive Switching Regulator IC for Boost / Fly-back Converter ■ PACKAGE OUTLINE  GENERAL DESCRIPTION The NJW4140 is a MOSFET Drive switching regulator IC for Boost / Fly-back Converter that operates wide input range from 3V to 40V. It can provide large current application because of built-in highly effective Nch MOSFET drive circuit. Built-in pulse-by-pulse current detecting type over current protection limits the output current at over load. It is suitable for boost/fly-back application such as Car Accessory, Office Automation Equipment, Industrial Instrument and so on.  FEATURES  Nch MOSFET Driving  Wide Operating Voltage Range  PWM Control  Wide Oscillating Frequency  Over Current Protection  UVLO (Under Voltage Lockout)  Standby Function  Package Outline NJW4140R NJW4140M Driving Voltage 5.3V (typ.) 3V to 40V 40kHz to 1MHz NJW4140R : MSOP8(VSP8)* NJW4140M : DMP8 *MEET JEDEC MO-187-DA Ver.2020-03-11 -1- NJW4140  PIN CONFIGURATION 1 8 2 7 3 6 4 5 PIN FUNCTION 1. V+ 2. EN 3. IN4. FB 5. CT 6. GND 7. SI 8. OUT NJW4140R NJW4140M  BLOCK DIAGRAM V Enable Control EN High: ON Low : OFF (Standby) ON/OFF 5V Reg. 500k Soft Start Vref Low Frequency Control Driver 0.8V Pulse by Pulse IN- PWM Comparator FB OUT OSC Error AMP -2- + CT SI VIPK GND Ver.2020-03-11 NJW4140  ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL Supply Voltage V+ OUT pin Voltage VOUT SI pin Voltage VSI EN pin Voltage VEN IN- pin Voltage VINCT pin Voltage VCT IO_PEAK+ OUT pin Peak Current IO_PEAKPower Dissipation PD (Ta=25°C) UNIT V V V V V V MAXIMUM RATINGS +45 -0.3 to +6 (*1) -0.3 to +6 +45 +6 +6 (*1) 200 (Source) 700 (Sink) mA MSOP8(VSP8) 595 (*2) DMP8 530 (*2) +150 -40 to +150 mW C C (*1): When Supply voltage is less than +6V, the absolute maximum EN pin voltage is equal to the Supply voltage. (*2): Mounted on glass epoxy board. (76.2×114.3×1.6mm:based on EIA/JDEC standard, 2Layers) Junction Temperature Storage Temperature Tjmax Tstg  RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL MIN. Supply Voltage V+ 3 Timing Capacitor CT 120 Oscillating Frequency fOSC 40 Operating Temperature Topr -40 Ver.2020-03-11 TYP. – – – – MAX. 40 3,900 1,000 +85 UNIT V pF kHz C -3- NJW4140  ELECTRICAL CHARACTERISTICS (Unless otherwise noted, V+=VEN=12V, CT=470pF, Ta=25C) PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT Oscillator Block Oscillation Frequency 1 fOSC1 CT=470pF 270 300 330 kHz Oscillation Frequency 2 Charge Current fOSC2 Ichg CT=680pF 180 150 210 200 240 250 kHz A Discharge Current Idis 150 200 250 A Voltage amplitude VOSC – 0.7 – V Oscillation Frequency deviation (Supply voltage) Oscillation Frequency deviation (Temperature) Oscillation Frequency (Low Frequency Control) fDV V+=3 to 40V – 1 – % fDT Ta= -40 to +85C – 6 – % VIN-=0.3V, VFB=0.7V, CT=470pF 90 105 120 kHz VB=0.75V 2 4 8 ms -1.0% -0.1 – – 0.8 – 80 3 +1.0% 0.1 – – V A dB MHz fOSC_LOW Soft Start Block Soft Start Time TSS Error Amplifier Block Reference Voltage Input Bias Current Open Loop Gain Gain Bandwidth VB IB AV GB Output Source Current IOM+ VFB=1V, VIN-=0.7V 50 100 150 A Output Sink Current IOM- VFB=1V, VIN-=0.9V 2 4 6 mA 0.32 0.63 85 0.4 0.7 90 0.54 0.77 95 V V % 115 140 165 mV ΔVSI=300mV – 90 – ns ROH IO= -50mA – 3 4.5  ROL IO= +50mA – 2.5 3.5  OUT pin= 4.5V 45 5 65 5.3 85 5.55 mA V PWM Comparate Block Input Threshold Voltage (FB pin) Maximum Duty Cycle Current Limit Detection Block Current Limit Detection Voltage Delay Time VT_0 VT_50 MAXDUTY Duty=0%, VIN-=0.6V Duty=50%, VIN-=0.6V VFB=1.2V VIPK TDELAY Output Block Output High Level ON Resistance Output Low Level ON Resistance Output Source Current Output pin Limiting Voltage -4- IOH VOLIM Ver.2020-03-11 NJW4140  ELECTRICAL CHARACTERISTICS (Unless otherwise noted, V+=VEN=12V, CT=470pF, Ta=25C) PARAMETER SYMBOL Under Voltage Lockout Block ON Threshold Voltage OFF Threshold Voltage VT_ON VT_OFF VON VOFF RPD Enable Control Block ON Control Voltage OFF Control Voltage Pull-down Resistance General Characteristics Quiescent Current Standby Current Ver.2020-03-11 IDD IDD_STB TEST CONDITION MIN. TYP. MAX. UNIT V+= L → H V+= H → L 2.65 2.4 2.8 2.55 2.95 2.7 V V VEN= L → H VEN= H → L 1.7 0 – – – 500 V+ 0.9 – V V k – – 1.4 2.5 1.7 6 mA A RL=no load, VIN-= VFB= 0.7V VEN=0V -5- NJW4140  APPLICATION EXAMPLE Non-isolated Boost Converter CNF RNF EN High: ON Low: OFF(Standby) V IN CIN1 CIN2 L SBD 4 3 2 1 FB IN- EN V+ COUT CFB R2 Pow er MOSFET NJW4140 CT GND SI OUT 5 6 7 8 V OUT RFB RSENSE R1 CT Filter Non-isolated Fly-back Converter CNF RNF EN High: ON Low: OFF(Standby) SBD T COUT V OUT V IN CIN1 CFB CIN2 R2 RFB 4 3 2 1 FB IN- EN V+ R1 Pow er MOSFET NJW4140 CT GND SI OUT 5 6 7 8 RSENSE CT Filter -6- Ver.2020-03-11 NJW4140  TYPICAL CHARACTERISTICS Oscillation frequency vs. Timing Capacitor + (V =12V, Ta=25°C) 100 Maximum Duty Cycle MAXDUTY (%) Oscillation frequency fOSC (kHz) 1000 100 10 100 Maximum Duty Cycle vs. Oscillator Frequency + (V =12V, VFB=1.2V, Ta=25°C) 90 80 70 60 50 40 30 20 10 0 1000 Timing Capacitor CT (pF) 10 10000 Oscillation Frequency vs. Supply Voltage (CT=470pF, Ta=25°C) 1000 Reference Voltage vs. Supply Voltage (Ta=25°C) 0.810 320 315 Reference Voltage VB (V) 310 305 300 295 290 0.805 0.800 0.795 285 280 0.790 0 10 20 30 Supply Voltage V+ (V) 40 0 40 Error Amplifier Block Voltage Gain, Phase vs. Frequency + (V =12V, Gain=40dB, Ta=25°C) Quiescent Current vs. Supply Voltage (RL=no load, VIN-=VFB=0.7V, Ta=25°C) 2 60 1.8 180 Phase 1.6 Voltage Gain Av (dB) Quiescent Current IDD (mA) 10 20 30 Supply Voltage V+ (V) 1.4 1.2 1 0.8 0.6 0.4 45 135 Gain 30 90 15 45 0.2 0 0 Ver.2020-03-11 10 20 30 Supply Voltage V+ (V) 40 0 100 1k 10k 100k Frequency f (kHz) 1M 0 10M -7- Phase Φ (deg) Oscillation Frequnecny fOSC (kHz) 100 Oscillator Frequency fOSC (kHz) NJW4140  TYPICAL CHARACTERISTICS Oscillation Frequency vs Temperature + (V =12V, CT=470pF) 320 0.810 Reference Voltage VB (V) Oscillator Frequency fOSC (kHz) 330 Reference Voltage vs. Temperature + (V =12V) 310 300 290 280 270 -50 0.805 0.800 0.795 0.790 -25 0 25 50 75 100 125 150 Ambient Temperature Ta (°C) -50 Current Limit Detection Votage vs.Temperature + (V =12V) OUT pin Limiting Voltage vs.Temperature + (V =12V) 170 Current Limit Detection Voltage VIPK (mV) OUT pin Limiting Voltage VOLIM (V) 12 160 150 140 130 120 10 110 6 4 2 -25 0 25 50 75 100 125 150 Ambient Temperature Ta (°C) -50 Output High Level ON Resistance vs.Temperature (IO=-50mA) 7 6 5 + V =3V 4 3 + V =12V V+=40V 2 1 0 -25 0 25 50 75 100 125 150 Ambient Temperature Ta (°C) Output Low Level ON Resistance vs.Temperature (IO=+50mA) 5 Output Low Level ON Resistance ROL () Output High Level ON Resistance ROH () 8 0 -50 4 + V =3V 3 2 V+=12V + V =40V 1 0 -50 -8- -25 0 25 50 75 100 125 150 Ambient Temperature Ta (°C) -25 0 25 50 75 100 125 150 Ambient Temperature Ta (°C) -50 -25 0 25 50 75 100 125 150 Ambient Temperature Ta (°C) Ver.2020-03-11 NJW4140  TYPICAL CHARACTERISTICS Enable Control ON/OFF Voltage vs.Temperature + (V =12V) 2 Under Voltage Lockout Voltage vs. Temperature 3.00 Threshold Voltage (V) VT_ON 2.80 2.70 2.60 VT_OFF 2.50 ON/OFF Voltage VON/OFF (V) 1.8 2.90 VON 1.6 1.4 1.2 VOFF 1 0.8 0.6 0.4 0.2 2.40 0 -50 -25 0 25 50 75 100 125 150 Ambient Temperature Ta (°C) -50 Quiescent Current vs. Temperature (RL=no load, VIN-=VFB=0.7V) Standby Current vs. Temperature (VEN=0V) 2 + V =40V 1.6 1.4 V+=12V 1.2 1 + V =3V 0.8 0.6 0.4 Standby Current IDD_STB (μA) 6 1.8 Quiescent Current IDD (mA) -25 0 25 50 75 100 125 150 Ambient Temperature Ta (°C) 5 4 3 + V =40V 2 V+=3V 1 V+=12V 0.2 0 0 -50 Ver.2020-03-11 -25 0 25 50 75 100 125 150 Ambient Temperature Ta (°C) -50 -25 0 25 50 75 100 125 150 Ambient Temperature Ta (°C) -9- NJW4140 NJW4140Application Manual Technical Information  PIN DESCRIPTIONS PIN PIN NAME NUMBER 1 V+ - 10 - 2 EN 3 IN- 4 FB 5 CT 6 GND 7 SI 8 OUT FUNCTION Power Supply pin Enable Control pin The ON/OFF pin internally pulls down with 500k. Normal Operation at the time of High Level. Standby Mode at the time of Low Level or OPEN. Output Voltage Detecting pin Connects output voltage through the resistor divider tap to this pin in order to voltage of the IN- pin become 0.8V. Feedback Setting pin The feedback resistor and capacitor are connected between the FB pin and the IN- pin. Oscillating Frequency Setting pin by Timing Capacitor Oscillating Frequency should set between 40kHz and 1MHz. GND pin Current Sensing pin When difference voltage between the SI pin and the GND pin exceeds 140mV(typ.), over current protection operates. Output pin for Power MOSFET Driving The OUT pin Voltage is clamped with 5.3V(typ.) at the time of High level, in order to protect a gate of Nch MOSFET. Ver.2020-03-11 NJW4140 ApplicationNJW4140 Manual Technical Information  Description of Block Features  Error Amplifier Section (ERAMP) 0.8V±1% precise reference voltage is connected to the non-inverted input of this section. To set the output voltage, connects converter's output to inverted input of this section (IN- pin). If requires output voltage over 0.8V, inserts resistor divider. This AMP section has high gain and external feedback pin (FB pin). It is easy to insert a feedback resistor and a capacitor between the FB pin and the IN- pin, making possible to set optimum loop compensation for each type of application. Oscillation frequency vs. Timing Capacitor + (V =12V, Ta=25°C) 1000 Oscillation frequency fOSC (kHz)  Oscillation Circuit Section (OSC) Oscillation frequency can be set by inserting capacitor between the CT pin and GND. Referring to the sample characteristics in "Timing Capacitor and Oscillation Frequency", set oscillation frequency between 40kHz and 1MHz. The triangular wave of the oscillating circuit is generated in the IC, having amplitude between 0.4V and 1.0V at CT=470pF(ref.). If voltage of the IN- pin becomes less than 0.4V, the oscillation frequency decreases to one third (33%) and the energy consumption is suppressed. 100 10 100 1000 Timing Capacitor CT (pF) 10000  PWM Comparator Section (PWM) This section controls the switching duty ratio. PWM comparator receives the signal of the error amplifier and the triangular wave, and controls the duty ratio between 0% and 90%. The timing chart is shown in Fig.1. Max Duty setting FB pin Voltage OSC Waveform (IC internal) Maximum duty: 90% V+ High OUT pin Low Fig. 1. Timing Chart PWM Comparator and OUT pin Ver.2020-03-11 - 11 - NJW4140 NJW4140Application Manual Technical Information  Description of Block Features (Continued)  Driver Section (Driver) The output driver circuit is configured a totem pole type, it can efficiently drive a Nch MOSFET switching device. When the output is high level, the OUT pin voltage is clamped with 5.3V (typ.) by the internal regulator to protect gate of Nch MOSFET. (Ref. Fig.2. OUT pin) V+ V+ 5.3V 5V Regulator GND OUT From PWM Comparator To turn on Nch MOSFET High Level Output OFF Driver ON OFF ON To turn off Nch MOSFET Low Level Output V GS Fig. 2. Driver Circuit and the OUT pin Voltage When supply voltage is decreasing, gate drive voltage output from the OUT pin is also decreasing. Although the OUT pin voltage is kept gate drive voltage by bypassing the internal regulator around supply voltage 5V. Fig.3. shows the example of the OUT pin voltage vs. supply voltage characteristic The optimum drive ability of MOSFET depends on the oscillation frequency and the gate capacitance of MOSFET. OUT pin Voltage vs. Supply Voltage (IO_SINK=0mA, Ta=25°C) OUT pin Voltage VOUT (V) 6 5 4 3 2 1 0 3 4 5 6 7 Supply Voltage V+ (V) 8 Fig. 3. OUT pin Voltage vs. Supply Voltage Characteristic - 12 - Ver.2020-03-11 NJW4140 ApplicationNJW4140 Manual Technical Information  Description of Block Features (Continued)  Power Supply, GND pin (V+, GND) In line with MOSFET drive, current flows into the IC according to frequency. If the power supply impedance provided to the power supply circuit is high, it will not be possible to take advantage of IC performance due to input voltage fluctuation. Therefore insert a bypass capacitor close to the V+ pin – the GND pin connection in order to lower high frequency impedance.  Under Voltage Lockout Function (UVLO) The UVLO circuit operating is released above V+=2.8V(typ.) and IC operation starts. When power supply voltage is low, IC does not operate because the UVLO circuit operates. There is 250mV width hysteresis voltage at rise and decay of power supply voltage. Hysteresis prevents the malfunction at the time of UVLO operating and releasing.  Enable Function (Enable Control) The NJW4140 stops the operating and becomes standby status when the EN pin becomes less than 0.9V. The EN pin internally pulls down with 500k, therefore the NJW4140 becomes standby mode when the EN pin is OPEN. You should connect this pin to V+ when you do not use Enable function.  Soft Start Function (Soft Start) The output voltage of the converter gradually rises to a set value by the soft start function. The soft start time is 4ms (typ). It is defined with the time of the error amplifier reference voltage becoming from 0V to 0.75V. The soft start circuit operates after the release UVLO. The operating frequency is controlled with a low frequency, approximately 33% of the set value by the timing resistor, until voltage of the IN- pin becomes approximately 0.4V. 0.8V Vref, IN- pin Voltage Max Duty setting FB pin Voltage OSC Waveform V+ High OUT pin Low UVLO(2.8V typ.) Release, Standby Low Frequency Control VIN-=approx 0.4V Soft Start time: Tss=4ms(typ.) to VB=0.75V Steady Operaton Soft Start effective period to VB=0.8V Fig. 4. Startup Timing Chart Ver.2020-03-11 - 13 - NJW4140 NJW4140Application Manual Technical Information  Description of Block Features (Continued)  Over Current Protection Circuit At when the potential difference between the V+ pin and the SI pin becomes 140mV or more, the over current protection circuit is stopped the switch output. The switching current is detected by inserted current sensing resistor (RSENSE) between the SI pin and the GND pin. Fig.5. shows the timing chart of the over current protection detection. The switching output holds low level until next pulse output at OCP operating. The NJW4140 output returns automatically along with release from the over current condition because the OCP is pulse-by-pulse type. If voltage of the IN- pin becomes less than 0.4V, the oscillation frequency decreases to one third (33%) and the energy consumption is suppressed. Max Duty setting FB pin Voltage OSC Waveform V+ High OUT pin Low Sw itching Current ILIM 0 Static State Static State Detect Overcurrent Fig. 5. Timing Chart at Over Current Detection The current waveform contains high frequency superimposed noises due to the parasitic elements of MOSFET, the inductor and the others. Depending on the application, inserting RC low-pass filter between current sensing resistor (RSENSE) and the SI pin to prevent the malfunction due to such noise. The time constant of RC low-pass filter should be equivalent to the spike width (T R  C) as a rough guide (Fig. 6). OUT Spike Noise Current Limit Detection SI To Pulse by Pulse R C V IPK T Current Waveform example RSENSE Low Pass Filter Fig. 6. Current Waveform and Filter Circuit - 14 - Ver.2020-03-11 NJW4140 ApplicationNJW4140 Manual Technical Information  Application Information  Inductors Current Peak Current Ipk Large currents flow into inductor, therefore you must provide current capacity that does not saturate. Inductor (1) Continuous Reducing L, the size of the inductor can be smaller. Current IL Conduction Mode However, peak current increases and adversely affecting (2) Critical Mode efficiency. (3) Continuous On the other hand, increasing L, peak current can be 0 Conduction Mode reduced at switching time. Therefore conversion Frequency tON tOFF efficiency improves, and output ripple voltage reduces. fOSC Above a certain level, increasing inductance windings increases loss (copper loss) due to the resistor element. Fig. 7. Inductor Current State Transition Ideally, the value of L is set so that inductance current is in continuous conduction mode. However, as the load current decreases, the current waveform changes from (1) CCM: Continuous Conduction Mode  (2) Critical Mode  (3) DCM: Discontinuous Conduction Mode (Fig. 7.). In discontinuous mode, peak current increases with respect to output current, and conversion efficiency tend to decrease. Depending on the situation, increase L to widen the load current area to maintain continuous mode.  Catch Diode When the switch element is in OFF cycle, power stored in the inductor flows via the catch diode to the output capacitor. Therefore during each cycle current flows to the diode in response to load current. Because diode's forward saturation voltage and current accumulation cause power loss, a Schottky Barrier Diode (SBD), which has a low forward saturation voltage, is ideal. An SBD also has a short reverse recovery time. If the reverse recovery time is long, through current flows when the switching transistor transitions from OFF cycle to ON cycle. This current may lower efficiency and affect such factors as noise generation. When the switch element is in ON cycle, a reverse voltage flows to SBD. Therefore you should select a SBD that has reverse voltage rating greater than maximum output voltage. The power loss, which stored in output capacitor, will be increase due to increasing reverse current through SBD at high temperature. Therefore, there is cases preferring reverse current characteristics to forward current characteristic in order to improve efficiency.  Switching Element You should use a switching element (Nch MOSFET) that is specified for use as a switch. And select sufficiently low RON MOSFET at less than VGS=5V because the NJW4140 OUT pin voltage is clamped 5.3 (typ.). However, when the supply voltage of the NJW4140 is low, the OUT pin voltage becomes low. You should select a suitable MOSFET according to the supply voltage specification. (Ref. Driver section) Large gate capacitance is a source of decreased efficiency. That is charge and discharge from gate capacitance delays switching rise and fall time, generating switching loss. The spike noise might occur at the time of charge/discharge of gate by the parasitic inductance element. You should insert resistance between the OUT pin and the gate and limit the current for gate protection when gate capacitance is small. However, it should be noted that the efficiency might decrease because the shape of waves may become duller when resistance is too large. The last fine-tuning should be done on the actual device and equipment. Ver.2020-03-11 - 15 - NJW4140 NJW4140Application Manual Technical Information  Application Information (Continued)  Input Capacitor Transient current flows into the input section of a switching regulator responsive to frequency. If the power supply impedance provided to the power supply circuit is large, it will not be possible to take advantage of NJW4140 performance due to input voltage fluctuation. Therefore insert an input capacitor as close to the MOSFET as possible.  Output Capacitor An output capacitor stores power from the inductor, and stabilizes voltage provided to the output. When selecting an output capacitor, you must consider Equivalent Series Resistance (ESR) characteristics, ripple current, and breakdown voltage. Also, the ambient temperature affects capacitors, decreasing capacitance and increasing ESR (at low temperature), and decreasing lifetime (at high temperature). Concerning capacitor rating, it is advisable to allow sufficient margin. Output capacitor ESR characteristics have a major influence on output ripple noise. A capacitor with low ESR can further reduce ripple voltage. Be sure to note the following points; when ceramic capacitor is used, the capacitance value decreases with DC voltage applied to the capacitor. - 16 - Ver.2020-03-11 NJW4140 ApplicationNJW4140 Manual Technical Information  Application Information (Continued)  Board Layout In the switching regulator application, because the current flow corresponds to the oscillation frequency, the substrate (PCB) layout becomes an important. You should attempt the transition voltage decrease by making a current loop area minimize as much as possible. Therefore, you should make a current flowing line thick and short as much as possible. Fig.8. shows a current loop at step-down converter. L V IN SBD L COUT CIN V IN SW SBD COUT CIN SW NJW4140 NJW4140 (a) Boost Converter SW ON (b) Boost Converter SW OFF Fig. 8. Current Loop at Boost Converter Concerning the GND line, it is preferred to separate the power system and the signal system, and use single ground point. The voltage sensing feedback line should be as far away as possible from the inductance. Because this line has high impedance, it is laid out to avoid the influence noise caused by flux leaked from the inductance. Fig. 9. shows example of wiring at boost converter. Fig. 10 shows the PCB layout example. L V IN SBD CIN V OUT COUT RL SW OUT (Bypass Capacitor) V+ RFB CFB NJW4140 INCT CT Separate Digital(Signal) GND from Pow er GND R2 GND R1 To avoid the influence of the voltage drop, the output voltage should be detected near the load. Because IN- pin is high impedance, the voltage detection resistance: R1/R2 is put as much as possible near IC(IN-). Fig. 9. Board Layout at Boost Converter Ver.2020-03-11 - 17 - NJW4140 NJW4140Application Manual Technical Information  Application Information (Continued) VIN VOUT L SBD CIN1 COUT1 COUT2 FET RSENSE GND IN GNDOUT Power GND Area CS1 RS1 RG EN CIN2 IC Feed back signal CT REN Signal GND Area CNF RNF R1 R2 RFB CFB Fig. 10 Layout Example (upper view) - 18 - Ver.2020-03-11 NJW4140 ApplicationNJW4140 Manual Technical Information  Calculation of Package Power You should consider derating power consumption under using high ambient temperature. Moreover, you should consider the power consumption that occurs in order to drive the switching element. Supply Voltage: Quiescent Current: Oscillation Frequency: ON time: Gate charge amount: V+ IDD fOSC ton Qg The gate of MOSFET has the character of high impedance. The power consumption increases by quickening the switching frequency due to charge and discharge the gate capacitance. Power consumption: PD is calculated as follows. PD = (V+  IDD) + (V+  Qg  fOSC) [W] You should consider temperature derating to the calculated power consumption: PD. You should design power consumption in rated range referring to the power dissipation vs. ambient temperature characteristics (Fig. 11). NJW4140M (DMP8 Package) Power Dissipation vs. Ambient Temperature (Tj=~150°C) 1000 At on 4 layer PC Board At on 2 layer PC Board 800 Power Dissipation P D (mW) Power Dissipation P D (mW) 1000 NJW4140R (MSOP8(VSP8) Package) Power Dissipation vs. Ambient Temperature (Tj=~150°C) 600 400 200 0 At on 4 layer PC Board At on 2 layer PC Board 800 600 Operating Temp. Extend Spec. 400 General Spec. 200 0 -50 -25 0 25 50 75 100 Ambient Temperature Ta (°C) 125 150 -50 -25 0 25 50 75 100 Ambient Temperature Ta (°C) 125 Mounted on glass epoxy board. (76.2114.31.6mm:EIA/JDEC standard size, 2Layers) Mounted on glass epoxy board. (76.2114.31.6mm:EIA/JDEC standard size, 4Layers), internal Cu area: 74.274.2mm Fig. 11. Power Dissipation vs. Ambient Temperature Characteristics Ver.2020-03-11 - 19 - 150 NJW4140 NJW4140Application Manual Technical Information  Application Design Examples  Step-Up Application Circuit IC : NJW4140R Input Voltage : VIN=9V to 15V Output Voltage : VOUT=20V Output Current : IOUT=1.5A (@VIN=12V) Oscillation frequency : fosc=300kHz CNF RNF 10,000pF 13k EN High: ON Low: OFF(Standby) VIN=12V CIN1 220F/35V CIN2 0.1F/50V 4 3 2 1 FB IN- EN V+ NJW4140 L1 22H/4.7A SBD GND SI OUT 5 6 7 8 VOUT=20V CFB 820pF RG 0 Q1 CT COUT1 COUT2 100F/35V, 0.1F/50V x2pcs. RFB 20k RSENSE 39m R2 82k R1 3.3k CT 470pF CS1 390pF Reference Qty. RS1 330 Part Number IC 1 NJW4140R Q1 L1 SBD CIN1 CIN2 COUT1 COUT2 CT CNF CFB CS1 R1 R2 RNF RFB RSENSE RG RS1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 TPCA8052-H CDRH127LDNP-220 DE5SC4M EEEFP1V221AP 0.1F EEEFP1V101AP 0.1F 470pF 10,000pF 820pF 390pF 3.3k 82k 13k 20k UR73D3ATTE39L0F 0 (Short) 330 - 20 - Description MOSFET Drive Switching Regulator IC for Boost / Fly-back Converter IC Nch MOSFET 40V, 20A Inductor 22H, 4.7A Schottky Diode 40V, 5A Aluminum Electrolytic Capacitor 220F, 35V Ceramic Capacitor 1608 0.1F, 50V, B Aluminum Electrolytic Capacitor 100F, 35V Ceramic Capacitor 1608 0.1F, 50V, B Ceramic Capacitor 1608 470pF, 50V, CH Ceramic Capacitor 1608 10,000pF, 50V, B Ceramic Capacitor 1608 820pF, 50V, B Ceramic Capacitor 1608 390pF, 50V, CH Resistor 1608 3.3k, 1%, 0.1W Resistor 1608 82k, 1%, 0.1W Resistor 1608 13k, 1%, 0.1W Resistor 1608 20k, 1%, 0.1W Resistor 2512 39m, ±1%, 1W Resistor 1608 0, 0.1W Resistor 1608 330, 1%, 0.1W Manufacturer New JRC Toshiba Sumida Shindengen Panasonic Std. Panasonic Std. Std. Std. Std. Std. Std. Std. Std. Std. KOA Std. Std. Ver.2020-03-11 NJW4140 ApplicationNJW4140 Manual Technical Information  Application Design Examples (Continued)  Setting Oscillation Frequency From the Oscillation frequency vs. Timing Capacitor Characteristic, reads CT=470 [pF], t=3.33[s] at fosc=300kHz. Step-Up converter duty ratio is shown with the following equation.  V Duty  1  IN VOUT    12    100  1    100  40 %  20   Therefore, tON=1.33 [s], tOFF=2.0 [s]  Selecting Inductance The inductor's average current equals input current (IIN). Estimated efficiency () is 93% and calculates input current as follows. IIN  VOUT  IOUT 20  1.5   2.69 A    VIN 0.93  12 IL is Inductance ripple current. When IL is 27% of input current: IL = 0.27  IIN = 0.27  2.69 = 0.73 [A] This obtains inductance L. L 12 VIN  1.33  22 [H]  t ON  0 .73 IL Inductance L is a theoretical value. The optimum value varies according such factors as application specifications and components. Fine-tuning should be done on the actual device. Peak Current: Ipk Inductance Current: IL Output Current: IOUT 0 This obtains the peak current Ipk at switching time. Ipk  IIN  IL 0.73  2.69   3.06[ A ] 2 2 tON tOFF Period: t Frequency: fOSC=1/t Fig. 12. Inductor Current Waveform The current that flows into the inductance provides sufficient margin for peak current at switching time. In the application circuit, use L=22H, 4.5A.  Setting Over Current Detection In this application, current limitation value: ILIMIT is set to Ipk=3.5A. ILIMIT = VIPK / RSC = 140mV / 39m =3.59 [A] The limit value increases slightly according to response time from the overcurrent detection with the SI pin to the OUT pin stop. ILIMIT _ DELAY  ILIMIT  Ver.2020-03-11 VIN 12  TDELAY  3.59   90n  3.64 [ A ] L 22 - 21 - NJW4140 NJW4140Application Manual Technical Information  Application Design Examples (Continued)  Selecting the Input Capacitor The input capacitor corresponds to the input of the power supply. It is required to adequately reduce the impedance of the power supply. The input capacitor selection should be determined by the input ripple current and the maximum input voltage of the capacitor rather than its capacitance value. The effective input current can be expressed by the following formula. IRMS _ CIN  I L 2 3  0.73 2 3  0.21 [ Arms] When selecting the input capacitor, carry out an evaluation based on the application, and use a capacitor that has adequate margin.  Selecting the Output Capacitor The output capacitor is an important component that determines output ripple noise. Equivalent Series Resistance (ESR), ripple current, and capacitor breakdown voltage are important in determining the output capacitor. The output ripple noise can be expressed by the following formula. I  0.73    Vripple  ESR   IL  L   40m   2.69    122 [mV ] 2  2    When selecting output capacitance, select a capacitor that allows for sufficient ripple current. The effective ripple current that flows in a capacitor (IRMS_COUT) is obtained by the following equation. IRMS _ COUT  I OUT  VOUT  VIN 20  12  1 .5   1.22 [ Arms ] VIN 12 Consider sufficient margin, and use a capacitor that fulfills the above spec. In the application circuit, Aluminum Electrolytic Capacitor COUT=100F/35V are used by 2 parallel.  Setting Output Voltage The output voltage VOUT is determined by the relative resistances of R1, R2. The current that flows in R1, R2 must be a value that can ignore the bias current that flows in Error AMP.  R2   82k  VOUT    1  VB    1  0.8  20.7 [ V ] R 1 3 . 3 k     It is easy to make a feedback loop, because the error amplifier output connects to FB pin. DC gain affects voltage sensing of the error amplifier. If AC gain increases, it affects stability of regulator due to AC gain which contains switching noise, ripple noise and the others. Recommended way of feedback is high DC gain and low AC gain. In this application, a feedback resistor RNF=13k and capacitor CNF=10,000pF are connected in serial. However, if the AC gain is lowered too much, it happens slower transient response against fast load changes. The optimum value varies according such factors as application specifications and components. Fine-tuning should be done on the actual device. - 22 - Ver.2020-03-11 NJW4140 ApplicationNJW4140 Manual Technical Information ■ Application Characteristics Efficiency vs. Output Current (VOUT=20V, Ta=25ºC) 100 f=300kHz L=22H 90 Efficiency η (%) 80 V+=9V, 12V, 15V 70 60 50 40 30 20 10 0 1 10 100 1000 Output Current IOUT (mA) 10000 Output Voltage vs Output Current (Ta=25ºC) Output Voltage VOUT (V) 21.0 f=300kHz L=22H 20.9 V+=9V, 12V, 15V 20.8 20.7 20.6 20.5 20.4 1 Ver.2020-03-11 10 100 1000 Output Current IOUT (mA) 10000 - 23 - NJW4140 MEMO [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. - 24 - Ver.2020-03-11
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