ADC10D1000CCMPR

ADC10D1000QML Low Power, 10-Bit, Dual 1.0 GSPS or Single 2.0 GSPS A/D Converter May 10, 2010 ADC10D1000QML Low Power, 10-Bit, Dual 1.0 GSPS or Single 2.0 GSPS A/D Converter 1.0 General Description The ADC10D1000 is the latest advance in National's UltraHigh-Speed ADC family of products. This low-power, highperformance CMOS analog-to-digital converter digitizes signals at 10-bit resolution at sampling rates of up to 1.0 GSPS in dual channel mode or 2.0 GSPS in single channel mode. The ADC10D1000 achieves excellent accuracy and dynamic performance while consuming a typical 2.9 Watts of power. This space grade, Radiation Tolerant part is rad hard to a single event latch up level of greater than 120MeV and a total dose (TID) of 100 krad(Si). The product is packaged in a hermatic 376 column thermally enhanced CCGA package rated over the temperature range of -55°C to +125°C. The ADC10D1000 builds upon the features, architecture and functionality of the 8-bit GHz family of ADCs. New features include an auto-sync feature for multi-chip synchronization, independent programmable15-bit gain and 12-bit offset adjustment per channel, LC tank filter on the clock input, and the option of two's complement format for the digital output data. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal track-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 8.9 Effective Number of Bits (ENOB) with a 498 MHz input signal and a 1.0 GHz sample rate while providing a 10−18 Code Error Rate (C.E.R.) Consuming a typical 2.9 Watts in Non-Demultiplex Mode at 1.0 GSPS from a single 1.9 Volt supply, this device is guaranteed to have no missing codes over the full operating temperature range. Each channel has its own independent DDR Data Clock, DCLKI and DCLKQ, which are in phase when both channels are powered up, so that only one Data Clock could be used to capture all data, which is sent out at the same rate as the input sample clock. If the 1:2 Demultiplexed Mode is selected, a second 10-bit LVDS bus becomes active for each channel, such that the output data rate is sent out two times slower, but two times wider to relax data-capture timing margin. The two channels (I and Q) can also be interleaved (DES Mode) and used as a single 2.0 GSPS ADC to sample on the Q input. The output formatting is offset binary or two's complement and the Low Voltage Differential Signaling (LVDS) digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V. 2.0 Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Total Ionizing Dose 100 krad(Si) Single Event Latch-up 120 Mev-cm2/mg Excellent accuracy and dynamic performance Low power consumption R/W SPI Interface for Extended Control Mode Internally terminated, buffered, differential analog inputs Ability to interleave the two channels to operate one channel at twice the conversion rate Test patterns at output for system debug Programmable 15-bit gain and 12-bit plus sign offset adjustments Option of 1:2 demuxed or 1:1 non-demuxed LVDS outputs Auto-sync feature for multi-chip systems Single 1.9V±0.1V power supply 376 Ceramic Column Grid Array package (28.2mm x 28.2mm x 3.1mm with 1.27mm ball-pitch) 3.0 Key Specifications (Non-Demux Non-DES Mode, Fs = 1.0 GSPS, Fin = 248 MHz) 10 Bits ■ Resolution ■ Conversion Rate — Dual channels at 1.0 GSPS (typ) — Single channel at 2.0 GSPS (typ) 10 −18 (typ) ■ Code Error Rate 9.0 bits (typ) ■ ENOB 56.1 dBc (typ) ■ SNR 63 dBc (typ) ■ SFDR 2.8 GHz (typ) ■ Full Power Bandwidth ±0.2 LSB (typ) ■ DNL Power Consumption ■ 1.64W (typ) — Single Channel Enabled 2.9W (typ) — Dual Channels Enabled 6 mW (typ) — Power Down Mode 4.0 Applications ■ Data Acquisition Systems ■ Wideband Communications ■ Direct RF Down Conversion © 2010 National Semiconductor Corporation 300718 www.national.com ADC10D1000QML 5.0 Ordering Information NS Part Number ADC10D1000CCMLS Flight Part ADC10D1000CCRQV Flight Part ADC10D1000CCMPR Pre-flight Prototype ADC10D1000CVAL Ceramic Evaluation Board TBD SMD Part Number NS Package Number CCC376A CCC376A CCC376A Package Description 376 Ceramic Column Grid Array 376 Ceramic Column Grid Array 376 Ceramic Column Grid Array 376 Ceramic Column Grid Array on Evaluation Board 6.0 Block Diagram 30071853 FIGURE 1. Simplified Block Diagram www.national.com 2 ADC10D1000QML Table of Contents 1.0 General Description ......................................................................................................................... 1 2.0 Features ........................................................................................................................................ 1 3.0 Key Specifications ........................................................................................................................... 1 4.0 Applications .................................................................................................................................... 1 5.0 Ordering Information ....................................................................................................................... 2 6.0 Block Diagram ................................................................................................................................ 2 7.0 Connection Diagram ........................................................................................................................ 6 8.0 Column Descriptions and Equivalent Circuits ....................................................................................... 7 9.0 Absolute Maximum Ratings ............................................................................................................ 15 10.0 Operating Ratings ....................................................................................................................... 15 11.0 Quality Conformance Inspection .................................................................................................... 15 12.0 Converter Electrical Characteristics ............................................................................................... 16 13.0 Specification Definitions ................................................................................................................ 26 14.0 Transfer Characteristic ................................................................................................................. 28 15.0 Timing Diagrams ......................................................................................................................... 29 16.0 Typical Performance Plots ............................................................................................................ 32 17.0 Functional Description .................................................................................................................. 38 17.1 OVERVIEW ......................................................................................................................... 38 17.2 POWER-ON RESET ............................................................................................................. 38 17.3 CONTROL MODES .............................................................................................................. 38 17.3.1 Non-Extended Control Mode ........................................................................................ 38 17.3.1.1 Non-Demultiplexed Mode Pin (NDM) ................................................................... 38 17.3.1.2 Dual Data Rate Phase Pin (DDRPh) .................................................................... 38 17.3.1.3 Calibration Pin (CAL) ......................................................................................... 39 17.3.1.4 Power Down I-channel Pin (PDI) ......................................................................... 39 17.3.1.5 Power Down Q-channel Pin (PDQ) ...................................................................... 39 17.3.1.6 Test Pattern Mode Pin (TPM) ............................................................................. 39 17.3.1.7 Full-Scale Input Range Pin (FSR) ....................................................................... 39 17.3.1.8 LVDS Output Common-mode Pin (VBG) ............................................................... 39 17.3.2 Extended Control Mode ............................................................................................... 40 17.3.2.1 The Serial Interface ........................................................................................... 40 17.4 FEATURES ......................................................................................................................... 43 17.4.1 Input Control and Adjust .............................................................................................. 44 17.4.1.1 Input Full-Scale Range Adjust ............................................................................ 44 17.4.1.2 Input Offset Adjust ............................................................................................ 44 17.4.1.3 DES/Non-DES Mode ......................................................................................... 44 17.4.1.4 Sampling Clock Phase Adjust ............................................................................. 44 17.4.1.5 LC Filter on Input Clock ..................................................................................... 44 17.4.2 Output Control and Adjust ............................................................................................ 44 17.4.2.1 DDR Clock Phase ............................................................................................. 45 17.4.2.2 LVDS Output Differential Voltage ........................................................................ 45 17.4.2.3 LVDS Output Common-Mode Voltage ................................................................. 45 17.4.2.4 Output Formatting ............................................................................................. 45 17.4.2.5 Demux/Non-demux Mode .................................................................................. 45 17.4.2.6 Test Pattern Mode ............................................................................................ 45 17.4.3 Calibration Feature ..................................................................................................... 46 17.4.3.1 Calibration Pins ................................................................................................ 46 17.4.3.2 How to Initiate a Calibration Event ....................................................................... 46 17.4.3.3 On-command Calibration ................................................................................... 46 17.4.3.4 Calibration Adjust .............................................................................................. 46 17.4.3.5 Calibration and Power-Down .............................................................................. 46 17.4.4 Power Down .............................................................................................................. 46 18.0 Applications Information ............................................................................................................... 47 18.1 THE ANALOG INPUTS ......................................................................................................... 47 18.1.1 Acquiring the Input ...................................................................................................... 47 18.1.2 The Reference Voltage and FSR .................................................................................. 47 18.1.3 Out-Of-Range Indication .............................................................................................. 47 18.1.4 AC-coupled Input Signals ............................................................................................ 47 18.1.5 Single-Ended Input Signals .......................................................................................... 48 18.2 THE CLOCK INPUTS ........................................................................................................... 48 18.2.1 CLK Coupling ............................................................................................................. 48 18.2.2 CLK Frequency .......................................................................................................... 48 18.2.3 CLK Level .................................................................................................................. 48 18.2.4 CLK Duty Cycle .......................................................................................................... 48 3 www.national.com ADC10D1000QML 18.2.5 CLK Jitter .................................................................................................................. 18.2.6 CLK Layout ................................................................................................................ 18.3 THE LVDS OUTPUTS ........................................................................................................... 18.3.1 Common-mode and Differential Voltage ......................................................................... 18.3.2 Output Data Rate ........................................................................................................ 18.4 SYNCHRONIZING MULTIPLE ADC10D1000S IN A SYSTEM .................................................... 18.4.1 AutoSync Feature ....................................................................................................... 18.4.2 DCLK Reset Feature ................................................................................................... 18.5 SUPPLY/GROUNDING, LAYOUT AND THERMAL RECOMMENDATIONS ................................. 18.5.1 Power Planes ............................................................................................................. 18.5.1.1 Bypass Capacitors ............................................................................................ 18.5.1.1.1 Ground Plane ......................................................................................... 18.5.1.1.2 Power Supply Example ............................................................................ 18.6 THERMAL MANAGEMENT ................................................................................................... 18.7 TEMPERATURE SENSOR DIODE ......................................................................................... 18.8 RADIATION ENVIRONMENTS .............................................................................................. 18.8.1 Total Ionizing Dose ..................................................................................................... 18.8.2 Single Event Latch-Up and Functional Interrupt .............................................................. 18.8.3 Single Event Upset ..................................................................................................... 18.9 BOARD MOUNTING RECOMMENDATION ............................................................................. 19.0 Register Definitions ...................................................................................................................... 20.0 Revision History .......................................................................................................................... 21.0 Physical Dimensions .................................................................................................................... 48 48 48 49 49 49 49 49 50 50 50 50 50 52 53 53 53 53 53 54 55 61 62 List of Figures FIGURE 1. Simplified Block Diagram ............................................................................................................. 2 FIGURE 2. ADC10D1000 Connection Diagram ................................................................................................ 6 FIGURE 3. LVDS Output Signal Levels ......................................................................................................... 26 FIGURE 4. Input / Output Transfer Characteristic ............................................................................................. 28 FIGURE 5. Clocking in 1:4 Demux DES Mode ................................................................................................ 29 FIGURE 6. Clocking in 1:2 Demux Non-DES Mode* ......................................................................................... 29 FIGURE 7. Clocking in Non-Demux Mode Non-DES Mode** ............................................................................... 30 FIGURE 8. Clocking in Non-Demux Mode DES Mode ....................................................................................... 30 FIGURE 9. Data Clock Reset Timing ............................................................................................................ 31 FIGURE 10. On-Command Calibration Timing ................................................................................................ 31 FIGURE 11. Serial Interface Timing ............................................................................................................. 31 FIGURE 12. Serial Interface Timing (Zoom Start)*** ......................................................................................... 41 FIGURE 13. Serial Interface Timing (Zoom End)**** ......................................................................................... 41 FIGURE 14. Serial Data Protocol - Read Operation .......................................................................................... 42 FIGURE 15. Serial Data Protocol - Write Operation .......................................................................................... 42 FIGURE 16. DDR DCLK-to-Data Phase Relationship ........................................................................................ 45 FIGURE 17. AC-coupled Differential Input ..................................................................................................... 47 FIGURE 18. Single-Ended to Differential Conversion Using a Balun ...................................................................... 48 FIGURE 19. Differential Input Clock Connection .............................................................................................. 48 FIGURE 20. AutoSync Example ................................................................................................................. 49 FIGURE 21. DCLK RST +/- ....................................................................................................................... 50 FIGURE 22. Power and Grounding Example .................................................................................................. 51 FIGURE 23. CCGA Conceptual Drawing ....................................................................................................... 52 FIGURE 24. Typical Temperature Sensor Application ....................................................................................... 53 FIGURE 25. Landing Pattern Recommendation ............................................................................................... 54 List of Tables TABLE 1. Analog Front-End and Clock Pins .................................................................................................... 7 TABLE 2. Control and Status Pins ................................................................................................................ 9 TABLE 3. Power and Ground Pins ............................................................................................................... 12 TABLE 4. High-Speed Digital Outputs .......................................................................................................... 13 TABLE 5. Static Converter Characteristics ..................................................................................................... 16 TABLE 6. Dynamic Converter Characteristics ................................................................................................. 17 TABLE 7. Analog Input/Output and Reference Characteristics ............................................................................. 20 TABLE 8. Channel-to-Channel Characteristics ................................................................................................ 20 TABLE 9. LVDS CLK Input Characteristics .................................................................................................... 21 TABLE 10. Digital Control and Output Pin Characteristics ................................................................................... 21 TABLE 11. Power Supply Characteristics (1:2 Demux Mode) .............................................................................. 22 TABLE 12. AC Electrical Characteristics ........................................................................................................ 23 TABLE 13. Non-ECM Pin Summary ............................................................................................................. 38 TABLE 14. Serial Interface Pins .................................................................................................................. 40 TABLE 15. Command and Data Field Definitions ............................................................................................. 40 www.national.com 4 ADC10D1000QML TABLE 16. Features and Modes ................................................................................................................ TABLE 17. LC Filter Code vs. fC ................................................................................................................. TABLE 18. LC Filter Bandwidth at 1GHz ....................................................................................................... TABLE 19. Test Pattern by Output Port in1:2 Demux Mode ................................................................................ TABLE 20. Test Pattern by Output Port inNon-Demux Mode ............................................................................... TABLE 21. Calibration Pins ....................................................................................................................... TABLE 22. Input Channel Samples Produced at Data Outputs in Demultiplexed Mode ............................................... TABLE 23. Input Channel Samples Produced at Data Outputs in Non-Demux Mode .................................................. TABLE 24. Temperature Sensor Recommendation .......................................................................................... TABLE 25. Solder Profile Specification ......................................................................................................... TABLE 26. Register Addresses .................................................................................................................. 43 44 44 45 45 46 47 47 53 54 55 5 www.national.com ADC10D1000QML 7.0 Connection Diagram 30071801 FIGURE 2. ADC10D1000 Connection Diagram The center ground pins are for thermal dissipation and must be soldered to a ground plane to ensure rated performance. For best performance, a common ground plane on multiple PC board layers is recommended. www.national.com 6 ADC10D1000QML 8.0 Column Descriptions and Equivalent Circuits TABLE 1. Analog Front-End and Clock Pins Column Name Equivalent Circuit Description Differential Signal I- and Q-Inputs. In the NonDual Edge Sampling (Non-DES) Mode, each Iand Q-channel is sampled and converted by its respective converter with each positive transition of the CLK+/- input. In the DES Mode and Extended Control Mode (ECM), only the Q-channel may be selected for conversion by the DESQ Bit (Addr: 0h, Bit 6). In the DES mode the Q-channel input is converted on the positive and negative edge of the CLK± input. Each I- and Q-channel input has an internal DCbias. Both channels must be AC coupled. In Non-ECM, the full-scale range of these inputs is determined by FSR (Pin Y3) and both I- and Qchannels have the same full-scale input range. In ECM, the full-scale input range of the I- and Qchannel inputs is independently determined by the setting of Addr: 3h and Addr: Bh, respectively. Note that the higher and lower full-scale input range setting in Non-ECM does not exactly correspond to the maximum and minimum full-scale input range in ECM. Additional features include: an input offset adjust, in Extended Control Mode. Differential Converter Sampling Clock. In the Non-DES Mode, the analog inputs are sampled on the positive transitions of this clock signal. In the DES Mode, the Q-channel is sampled on both transitions of this clock. This clock must be ACcoupled. Additional features include: LC filter on the clock input. H1/J1 N1/M1 VinI+/VinQ+/- U2/V1 CLK+/- V2/W1 DCLK_RST+/- Differential DCLK Reset. A positive pulse on this input is used to reset the DCLKI+/- and DCLKQ+/- outputs of two or more ADC10D1000s in order to synchronize them with other ADC10D1000s in the system. DCLKI+/- and DCLKQ+/- are always in phase with each other, unless one channel is powered down, and do not require a pulse from DCLK_RST+/- to become synchronized. The pulse applied here must meet timing relationships with respect to the CLK+/input. This feature may still be used while the chip is in the AutoSync Mode. 7 www.national.com ADC10D1000QML Column Name Equivalent Circuit Description Bandgap Voltage Output or LVDS Commonmode Voltage Select. This pin provides the bandgap output voltage and is capable of sourcing/ sinking 100 uA and driving a load of up to 80 pF. Alternately, this pin may be used to select the LVDS digital output common-mode voltage. If tied to logic-high, the higher LVDS common-mode voltage is selected. The lower value is the default. External Reference and Input Termination Trim Resistor terminals. A 3.3 kΩ ±0.1% resistor should be connected between Rtrim+/-. The Rtrim resistor is used to establish the calibrated 100Ω input impedance of VinI+/-, VinQ+/- and CLK+/-. These impedances may be fine tuned by varying the value of the resistor by a corresponding percentage; however, the tuning range and performance is not guaranteed for such an alternate value. A 3.3 kΩ ±0.1% resistor should be connected between Rext+/-. The Rext resistor is used for setting internal temperature-independent bias currents; the value and precision of this resistor should not be compromised. B1 VBG C1/D2 Rtrim+/- C3/D3 Rext+/- Temperature Sensor Diode Positive (Anode) and Negative (Cathode) Terminals. This set of pins is used for die temperature measurements. E2/F3 Tdiode+/- www.national.com 8 ADC10D1000QML Column Name Equivalent Circuit Description Reference Clock Input. When the AutoSync feature is active, and the ADC10D1000 is in Slave Mode, the internal divided clocks are synchronized with respect to this input clock. The delay on this clock may be adjusted when synchronizing multiple ADCs. This feature is available in ECM via Control Register (Addr: Eh). Y4/W5 RCLK+/- Y5/U6 V6/V7 RCOut1+/RCOut2+/- Reference Clock Output 1 and 2. These signals provide a reference clock at a rate of CLK/4, when enabled, independently of whether the ADC is in Master or Slave Mode. They are used to drive the RCLK of another ADC10D1000, to enable automatic synchronization for multiple ADCs (AutoSync feature.) The impedance of each trace from RCOut1+/- and RCOut2+/- to the RCLK+/- of another ADC10D1000 should be 100Ω differential. Having two clock outputs allows the auto-synchronization to propagate as a binary tree. Use the DOC Bit (Addr: Eh, Bit 1) to enable/ disable this feature; default is disabled. TABLE 2. Control and Status Pins Column Name Equivalent Circuit Description Calibration Cycle Initiate. The user can command the device to execute a self-calibration cycle by holding this input high a minimum of tCAL_H after having held it low a minimum of tCAL_L. This pin is active in both ECM and Non-ECM. In ECM, this pin is logically OR'd with the CAL Bit (Addr: 0h, Bit 15) in the Control Register. Therefore, both pin and bit must be set low and then either can be set high to execute an on-command calibration. Calibration Running Indication. This output is logichigh while the calibration sequence is executing. This output is logic-low while the calibration sequence is not running. B5 CalRun D6 CAL 9 www.national.com ADC10D1000QML Column Name Equivalent Circuit Description Power Down I- and Q-channel. Setting either input to logic-high powers down the respective I- or Q-channel converter. Setting either input to logic-low brings the respective I- or Q-channel converter to a fully operational state after a finite time delay. This pin is active in both ECM and Non-ECM. In the ECM, either this pin or the PDI and PDQ Bit in the Control Register can be used to power-down the I- and Q-channel (Addr: 0h, Bit 11 and Bit 10), respectively. Test Pattern Mode. With this input at logic-high, the device continuously outputs a fixed, repetitive test pattern at the digital outputs. In the ECM, this input is ignored and the test pattern mode can only be activated through the Control Register by the TPM Bit (Addr: 0h, Bit 12). U3 V3 PDI PDQ A4 TPM A5 NDM Non-Demuxed Mode. Setting this input to logic-high causes the digital output bus to be in the 1:1 NonDemuxed Mode. Setting this input to logic-low causes the digital output bus to be in the 1:2 Demuxed Mode. This feature is pin-controlled only and remains active during ECM and Non-ECM. Y3 FSR Full-Scale input Range Select. In Non-ECM, when this input is set to logic-low or logic-high, the full-scale differential input range for both I- and Q-channel inputs is set to the lower or higher value, respectively. In the ECM, this input is ignored and the full-scale range of the I- and Q-channel inputs is independently determined by the setting of Addr: 3h and Addr: Bh, respectively. Note that the higher and lower FSR value in Non-ECM does not precisely correspond to the maximum and minimum available selection in ECM; in ECM, the selection range is greater. DDR Phase Select. This input, when logic-low, selects the 0-degree Data-to-DCLK phase relationship. When logic-high, it selects the 90-degree Data-to-DCLK phase relationship. This pin only has an effect when the chip is in 1:2 Demuxed Mode, e.g. the NDM pin is set to logic-low. In ECM, this input is ignored and the DDR phase is selected through the Control Register by the DPS Bit (Addr: 0h, Bit 14); the default is 0degree Data-to-DCLK phase relationship. W4 DDRPh www.national.com 10 ADC10D1000QML Column Name Equivalent Circuit Description Extended Control Enable bar. Extended feature control through the SPI interface is enabled when this signal is asserted logic-low. In this case, most of the direct control pins have no effect. When this signal is de-asserted, i.e. logic-high, the SPI interface is disabled and the direct control pins are enabled. B3 ECE C4 SCS Serial Chip Select bar. In ECM, when this signal is asserted logic-low, SCLK is used to clock in serial data which is present on the SDI input and to source serial data on the SDO output. When this signal is deasserted, i.e. logic-high, the SDI input is ignored and the SDO output is in tri-state mode. C5 SCLK Serial Clock. In ECM, serial data is shifted into and out of the device synchronously to this clock signal. This clock may be disabled and held logic-low, so long as timing specifications are not violated when the clock is enabled or disabled. Serial Data-In. In ECM, serial data is shifted into the device on this pin while SCS signal is asserted (logiclow). B4 SDI Serial Data-Out. In ECM, serial data is shifted out of the device on this pin while SCS signal is asserted (logic-low). This output is in tri-state mode when SCS is de-asserted. A3 SDO W3 RSV NONE Reserved: This pin is used for internal purposes and should be connected to GND through a 100K Ω resistor. 11 www.national.com ADC10D1000QML TABLE 3. Power and Ground Pins Column A2, A6, B6, C7, D1, D8, D9, E1, F1, H4, N4, R1, T1, U8, U9, W6, Y2, Y6 G1, G3, G4, H2, J3, K3, L3, M3, N2, P1, P3, P4, R3, R4 A11, A15, C18, D11, D15, D17, J17, J20, R17, R20, T17, U11, U15, U16, Y11, Y15 A8, B9, C8, V8, W9, Y8 Name Equivalent Circuit Description Analog Power Supply. This supply is tied to the ESD ring. Therefore, it must be powered up before or with any other supply. VA NONE VTC NONE Analog Power Supply for the Track-and-Hold and Clock circuitry. Power Supply for the Output Drivers. VDR NONE VE NONE Power Supply for the Digital Encoder. Bias Voltage I-channel. This is an externally decoupled bias voltage for the I-channel. Each pin should individually be decoupled with a 100nF capacitor via a low resistance, low inductance path to GND. Bias Voltage Q-channel. This is an externally decoupled bias voltage for the Q-channel. Each pin should individually be decoupled with a 100nF capacitor via a low resistance, low inductance path to GND. Analog Ground Return. D7, E3, J4, K2 VbiasI NONE F4, L2, M4, U7 VbiasQ NONE A1, A7, B2, B7, C2, C6, D4, D5, E4, K1, L1, T4, U4, U5, V4, V5, W2, W7, Y1, Y7, AA2thru AL11 F2, G2, H3, J2, K4, L4, M2, N3, P2, R2, T2, T3, U1 GND NONE GNDTC NONE Analog Ground Return for the Track-and-Hold and Clock circuitry. www.national.com 12 ADC10D1000QML Column A10, A13, A17, A20, B10 B18, B19, B20, C10, C17, D10, D13, D16, E17, F17, F20, M17, M20, U10,U13, U17, V10, V17, V18, W10, W18, W19, W20, Y10, Y13, Y17, Y20 A9, B8, C9, V9, W8, Y9 Name Equivalent Circuit Description Ground Return for the Output Driver. GNDDR NONE GNDE NONE Ground Return for the Digital Encoder. TABLE 4. High-Speed Digital Outputs Column Name Equivalent Circuit Description Data Clock Output for the I- and Q-channel data bus. These differential clock outputs are used to latch the output data and should always be terminated with a 100Ω differential resistor. Delayed and non-delayed data outputs are supplied synchronously to this signal. In 1:2 Demux Mode or Non-Demux Mode, this signal is at ¼ or ½ the input clock rate, respectively. DCLKI+/- and DCLKQ+/- are always in phase with each other, unless one channel is powered down and do not require a pulse from DCLK_RST+/- to become synchronized. K19/K20 L19/L20 DCLKI+/DCLKQ+/- K17/K18 L17/L18 ORI+/ORQ+/- Out-of-Range Output for the I- and Q-channel. This differential output is asserted logic-high while the overor under-range condition exists, i.e. the differential signal at each respective analog input exceeds the fullscale value. Each OR results refers to the current Data, with which it is clocked out. Each of these outputs should always be terminated with a 100Ω differential resistor placed as closely as possible to the differential receiver. 13 www.national.com ADC10D1000QML Column J18/J19 H19/H20 H17/H18 G19/G20 G17/G18 F18/F19 E19/E20 D19/D20 D18/E18 C19/C20 · M18/M19 N19/N20 N17/N18 P19/P20 P17/P18 R18/R19 T19/T20 U19/U20 U18/T18 V19/V20 A18/A19 B17/C16 A16/B16 B15/C15 C14/D14 A14/B14 B13/C13 C12/D12 A12/B12 B11/C11 · Y18/Y19 W17/V16 Y16/W16 W15/V15 V14/U14 Y14/W14 W13/V13 V12/U12 Y12/W12 W11/V11 Name DI9+/DI8+/DI7+/DI6+/DI5+/DI4+/DI3+/DI2+/DI1+/DI0+/· DQ9+/DQ8+/DQ7+/DQ6+/DQ5+/DQ4+/DQ3+/DQ2+/DQ1+/DQ0+/DId9+/DId8+/DId7+/DId6+/DId5+/DId4+/DId3+/DId2+/DId1+/DId0+/· DQd9+/DQd8+/DQd7+/DQd6+/DQd5+/DQd4+/DQd3+/DQd2+/DQd1+/DQd0+/- Equivalent Circuit Description I- and Q-channel Digital Data Outputs. In Non-Demux Mode, this LVDS data is transmitted at the sampling clock rate. In Demux Mode, these outputs provide ½ the data at ½ the sampling clock rate, synchronized with the delayed data, i.e. the other ½ of the data which was sampled one clock cycle earlier. Compared with the DId and DQd outputs, these outputs represent the later time samples. Each of these outputs should always be terminated with a 100Ω differential resistor placed as closely as possible to the differential receiver Delayed I- and Q-channel Digital Data Outputs. In Non-Demux Mode, these outputs are tri-stated. In Demux Mode, these outputs provide ½ the data at ½ the sampling clock rate, synchronized with the nondelayed data, i.e. the other ½ of the data which was sampled one clock cycle later. Compared with the DI and DQ outputs, these outputs represent the earlier time samples. Each of these outputs should always be terminated with a 100Ω differential resistor placed as closely as possible to the differential receiver. www.national.com 14 ADC10D1000QML 9.0 Absolute Maximum Ratings (Note 1, Note 2) Supply Voltage (VA, VTC, VDR, VE) 2.2V Supply Difference max(VA /TC/DR /E) -min(VA /TC/DR/E) 0V to 100 mV Voltage on Any Input Pin −0.15V to (VA +0.15V) Voltage on VIN+, VIN−0.15V to 2.5V (Maintaining Common Mode) Ground Difference max(GNDTC/DR/E) -min(GNDTC/DR/E) 0V to 100 mV Input Current at Any Pin (Note 3) ±50 mA Power Dissipation at TA ≤ 85°C (Note 3) ESD Susceptibility (Note 4) Human Body Model Charged Device Model Machine Model Storage Temperature 3.4 W   8000V 750V 250V −65°C to +150°C 10.0 Operating Ratings (Note 1, Note 2) Ambient Temperature Range Supply Voltage (VA, VTC, VE) Driver Supply Voltage (VDR) VIN+, VIN- Voltage Range (Maintaining Common Mode) −55°C ≤ TA ≤ +125°C +1.8V to +2.0V +1.8V to VA 0V to 2.15V (100% duty cycle) 0V to 2.5V (10% duty cycle) 0V 0V to VA 0.4VP-P to 2.0VP-P θJB To Board 3.2°C / W Ground Difference max(GNDTC/DR/E) -min(GNDTC/DR/E) CLK Pins Voltage Range Differential CLK Amplitude Package Thermal Resistance Package θJA 376 Ceramic 10.4°C / W Column Grid Array Solder process specifications in Section 18.9 BOARD MOUNTING RECOMMENDATION 11.0 Quality Conformance Inspection MIL-STD-883, Method 5005 - Group A Subgroup 1 2 3 4 5 6 7 8A 8B 9 10 11 12 13 14 Description Static tests at Static tests at Static tests at Dynamic tests at Dynamic tests at Dynamic tests at Functional tests at Functional tests at Functional tests at Switching tests at Switching tests at Switching tests at Setting time at Setting time at Setting time at Temp (°C) +25 +125 -55 +25 +125 -55 +25 +125 -55 +25 +125 -55 +25 +125 -55 15 www.national.com ADC10D1000QML 12.0 Converter Electrical Characteristics (Note 13) The following specifications apply after calibration for VA = VDR = VTC = VE = +1.9V; I- and Q-channels AC coupled, FSR Pin = High; CL = 10 pF; Differential AC coupled Sine Wave Input Clock, fCLK = 1 GHz at 0.5 VP-P with 50% duty cycle; VBG = Floating; Non-extended Control Mode; Rext = Rtrim = 3300 Ω ±0.1%; Analog Signal Source Impedance = 100 Ω Differential; 1:2 Demultiplex Non-DES Mode; I- and Q-channels; Duty Cycle Stabilizer on. Boldface limits apply for TA = TMIN to TMAX, unless otherwise noted. All other limits TA = 25°C, unless otherwise noted. (Note 5, Note 6, Note 12) TABLE 5. Static Converter Characteristics Symbol INL DNL Parameter Integral Non-Linearity (Best fit) Conditions D.C. Coupled, 1 MHz Sine Wave Over-ranged Notes Typical ±0.7 ±0.2 Min Max ±1.4 ±0.5 10 -2.8 Extended Control Mode (Note 8) (Note 8) (VIN+) − (VIN−) > + Full Scale (VIN+) − (VIN−) < − Full Scale ±45 ±28.0 ±28.0 1023 0 Units LSB LSB bits LSB mV mV mV 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 Subgroups 1, 2, 3 1, 2, 3 1, 2, 3 Differential Non-Linearity D.C. Coupled, 1 MHz Sine Wave Over-ranged Resolution with No Missing Codes VOFF VOFF_ADJ PFSE NFSE Offset Error Input Offset Adjustment Range Positive Full-Scale Error Negative Full-Scale Error Out of Range Output Code www.national.com 16 ADC10D1000QML TABLE 6. Dynamic Converter Characteristics Symbol FPBW C.E.R. Parameter Full Power Bandwidth Code Error Rate Gain Flatness NPR Noise Power Ratio D.C. to 498 MHz D.C. to 1.0 GHz fc,notch = 325 MHz, notch width = 25 MHz fIN = 248 MHz, VIN = -0.5 dBFS, TA = 25°C to TMax fIN = 248 MHz, VIN = -0.5 dBFS, TA = TMIN fIN = 498 MHz, VIN = -0.5 dBFS, TA = 25°C to TMax fIN = 498 MHz, VIN = -0.5 dBFS, TA = TMIN SINAD Signal-to-Noise Plus Distortion Ratio fIN = 248 MHz, VIN = -0.5 dBFS, TA = 25°C to TMax fIN = 248 MHz, VIN = -0.5 dBFS, TA = TMIN fIN = 498 MHz, VIN = -0.5 dBFS, TA = 25°C to TMax fIN = 498 MHz, VIN = -0.5 dBFS, TA = TMIN SNR Signal-to-Noise Ratio fIN = 248 MHz, VIN = -0.5 dBFS, TA = 25°C to TMax fIN = 248 MHz, VIN = -0.5 dBFS, TA = TMIN fIN = 498 MHz, VIN = -0.5 dBFS, TA = 25°C to TMax fIN = 498 MHz, VIN = -0.5 dBFS, TA = TMIN THD Total Harmonic Distortion fIN = 248 MHz, VIN = -0.5 dBFS, TA =25°C to TMAX fIN = 248 MHz, VIN = -0.5 dBFS, TA = TMIN fIN = 498 MHz, VIN = -0.5 dBFS, TA = 25°C to TMAX fIN = 498 MHz, VIN = -0.5 dBFS, TA = TMIN 2nd Harm 3rd Harm Second Harmonic Distortion Third Harmonic Distortion fIN = 248 MHz, VIN = -0.5 dBFS fIN = 498 MHz, VIN = -0.5 dBFS fIN = 248 MHz, VIN = -0.5 dBFS fIN = 498 MHz, VIN = -0.5 dBFS Conditions Non-DES Mode DES Mode Notes Typical 2.8 1.3 10−18 ±0.25 ±0.5 47.5 Min Max Units GHz GHz Error/ Sample dBFS dBFS dB Subgroups 1:2 Demux Non-DES Mode, Extended Control Mode, FM (14:0) = 7FFFh ENOB Effective Number of Bits 8.4 9.0 7.8 8.2 8.9 7.8 52.2 55.8 48.5 51.0 55.4 48.8 53.2 56.8 49.4 52.0 56.1 49.4 -59.0 -68 -56.0 -58.0 -61 -57.0 −75 −68 −72 −67 dBc dBc dBc dBc dBc 6 dBc dBc 6 4, 5 dBc dBc 6 4, 5 dBc dBc 6 4, 5 dB dBc 6 4, 5 dB dB 6 4, 5 bits dB 6 4, 5 bits bits 6 4, 5 bits 4, 5 17 www.national.com ADC10D1000QML Symbol SFDR Parameter Spurious-Free Dynamic Range Conditions fIN = 248 MHz, VIN = -0.5 dBFS, TA = 25°C to TMax fIN = 248 MHz, VIN = -0.5 dBFS, TA = TMIN fIN = 498 MHz, VIN = -0.5 dBFS, TA = 25°C to TMax fIN = 498 MHz, VIN = -0.5 dBFS, TA = TMIN Notes Typical Min 59.0 Max Units dBc dBc dBc dBc Subgroups 4, 5 6 4, 5 6 63.0 53.0 57.5 63.0 54.5 1:2 Demux Non-DES Mode, Non-Extended Control Mode, FSR = VA ENOB Effective Number of Bits fIN = 248 MHz, VIN = -0.5 dBFS, TA = 25°C to TMAX fIN = 248 MHz, VIN = -0.5 dBFS, TA = TMIN fIN = 498 MHz, VIN = -0.5 dBFS, TA = 25°C to TMAX fIN = 498 MHz, VIN = -0.5 dBFS, TA = TMIN SINAD Signal-to-Noise Plus Distortion Ratio fIN = 248 MHz, VIN = -0.5 dBFS, TA = 25°C to TMAX fIN = 248 MHz, VIN = -0.5 dBFS, TA = TMIN fIN = 498 MHz, VIN = -0.5 dBFS, TA = 25°C to TMAX fIN = 498 MHz, VIN = -0.5 dBFS, TA = TMIN SNR Signal-to-Noise Ratio fIN = 248 MHz, VIN = -0.5 dBFS, TA = 25°C to TMAX fIN = 248 MHz, VIN = -0.5 dBFS, TA = TMIN fIN = 498 MHz, VIN = -0.5 dBFS, TA = 25°C to TMAX fIN = 498 MHz, VIN = -0.5 dBFS, TA = TMIN THD Total Harmonic Distortion fIN = 248 MHz, VIN = -0.5 dBFS, TA = 25°C to TMAX fIN = 248 MHz, VIN = -0.5 dBFS, TA = TMIN fIN = 498 MHz, VIN = -0.5 dBFS, TA = 25°C to TMAX fIN = 498 MHz, VIN = -0.5 dBFS, TA = TMIN 2nd Harm 3rd Harm Second Harmonic Distortion Third Harmonic Distortion fIN = 248 MHz, VIN = -0.5 dBFS fIN = 498 MHz, VIN = -0.5 dBFS fIN = 248 MHz, VIN = -0.5 dBFS fIN = 498 MHz, VIN = -0.5 dBFS 8.1 8.9 7.8 8 8.9 7.7 50.3 55.3 48.5 49.8 55.3 48.0 50.9 55.6 49.0 50.5 55.9 48.5 -59.5 -67.0 -58.5 -58.5 -64.3 -58.0 −75 −68 −72 −68 dBc dBc dBc dBc dBc 6 dBc dBc 6 4, 5 dBc dBc 6 4, 5 dBc dBc 6 4, 5 dB dBc 6 4, 5 dB dB 6 4, 5 bits dB 6 4, 5 bits bits 6 4, 5 bits 4, 5 www.national.com 18 ADC10D1000QML Symbol SFDR Parameter Spurious-Free Dynamic Range Conditions fIN = 248 MHz, VIN = -0.5 dBFS, TA = 25°C to TMAX fIN = 248 MHz, VIN = -0.5 dBFS, TA = TMIN fIN = 498 MHz, VIN = -0.5 dBFS, TA = 25°C to TMAX fIN = 498 MHz, VIN = -0.5 dBFS, TA = TMIN Notes Typical Min 57.5 Max Units dBc dBc dBc dBc Subgroups 4, 5 6 4, 5 6 66.7 53.0 57.5 66.7 54.5 Non-Demux Non-DES Mode, Non-Extended Control Mode, FSR = VA ENOB SINAD SNR THD 2nd Harm 3rd Harm SFDR Effective Number of Bits Signal-to-Noise Plus Distortion Ratio Signal-to-Noise Ratio Total Harmonic Distortion Second Harmonic Distortion Third Harmonic Distortion Spurious-Free Dynamic Range Effective Number of Bits Signal-to-Noise Plus Distortion Ratio Signal-to-Noise Ratio Total Harmonic Distortion Second Harmonic Distortion Third Harmonic Distortion Spurious-Free Dynamic Range fIN = 498 MHz, VIN = -0.5 dBFS fIN = 498 MHz, VIN = -0.5 dBFS fIN = 498 MHz, VIN = -0.5 dBFS fIN = 498 MHz, VIN = -0.5 dBFS fIN = 498 MHz, VIN = -0.5 dBFS fIN = 498 MHz, VIN = -0.5 dBFS fIN = 498 MHz, VIN = -0.5 dBFS 9.0 56.2 56.7 -65.7 −75 −68 67.6 bits (min) dB (min) dBc (min) dBc (max) dBc dBc dBc (min) bits (min) dB (min) dBc (min) dBc (max) dBc dBc dBc (min) 1:4 Demux DES Mode (Q-channel only), ECM, Offset/Gain Adjusted ENOB SINAD SNR THD 2nd Harm 3rd Harm SFDR fIN = 498 MHz, VIN = -0.5 dBFS fIN = 498 MHz, VIN = -0.5 dBFS fIN = 498 MHz, VIN = -0.5 dBFS fIN = 498 MHz, VIN = -0.5 dBFS fIN = 498 MHz, VIN = -0.5 dBFS fIN = 498 MHz, VIN = -0.5 dBFS fIN = 498 MHz, VIN = -0.5 dBFS 8.7 54.2 55.3 60.7 −78 −67 63.6 19 www.national.com ADC10D1000QML TABLE 7. Analog Input/Output and Reference Characteristics Symbol VIN_FSR Parameter Analog Differential Input Full Scale Range Conditions FSR Pin Y3 Low FSR Pin Y3 High Extended Control Mode FM(14:0) = 0000h FM(14:0) = 4000h (default) FM(14:0) = 7FFFh CIN Analog Input Capacitance, Differential Non-DES Mode Each input pin to ground Analog Input Capacitance, Differential DES Mode Each input pin to ground RIN VBG TC_VBG Differential Input Resistance Bandgap Reference Output Voltage Bandgap Reference Voltage Temperature Coefficient IBG = ±100 µA IBG = ±100µA 50 ppm/°C (Note 9, Note 10) (Note 9, Note 10) 600 790 980 0.02 1.6 0.08 2.2 103.5 1.25 100 108 1.15 1.35 mVP-P mVP-P mVP-P pF pF pF pF Ω Ω V V 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 Notes Typical 630 820 Min 560 680 750 890 Max Units mVP-P mVP-P mVP-P mVP-P Subgroups 4, 5, 6 4, 5, 6 4, 5, 6 4, 5, 6 CLOAD VBG Maximum Bandgap Reference Load Capacitance 80 pF TABLE 8. Channel-to-Channel Characteristics Symbol Parameter Offset Match Positive Full-Scale Match Zero offset selected in Control Register Conditions Notes Typical 2 2 2