COP87L88RGV-XE

COP87L88RG 8-Bit One-Time Programmable (OTP) Microcontroller with 32 Kbytes of Program Memory PRELIMINARY September 1996 COP87L88RG 8-Bit One-Time Programmable (OTP) Microcontroller with 32 Kbytes of Program Memory General Description The COP87L88RG is a member of the COP8TM OTP microcontroller family It is pin and software compatible to the mask ROM COP888GG product family (Continued) Y Y Schmitt trigger inputs on ports G and L Packages 44 PLCC with 40 I O pins 40 DIP with 36 I O pins CPU Instruction Set Features Y Y Key Features Y Y Y Full duplex UART Three 16-bit timers each with two 16-bit registers supporting Processor independent PWM mode External event counter mode Input capture mode 32 kbytes on-board EPROM with security feature Note Mask ROMed devices with equivalent on-chip features and program memory sizes of 4k 8k 16k 20k and 24k are available (see Table I) Y Y Y Y 512 bytes on-board RAM Additional Peripheral Features Y Y Y Y Y 1 ms instruction cycle time Fourteen multi-source vectored interrupts servicing External interrupt Idle timer T0 Two timers (each with 2 interrupts) MICROWIRE PLUS Multi-Input Wake Up Software trap UART (2) Default VIS (default interrupt) Versatile instruction set with true bit manipulation 8-bit Stack Pointer SP (stack in RAM) Two 8-bit register indirect data memory pointers (B and X) Idle timer Multi-Input Wake Up (MIWU) with optional interrupts (8) Two analog comparators WATCHDOGTM and clock monitor logic MICROWIRE PLUSTM serial I O Fully Static CMOS Y Y Y Two power saving modes HALT and IDLE Single supply operation 2 7V – 5 5V Temperature range b40 C to a 85 C I O Features Y Y Development Support Y Y Memory mapped I O Software selectable I O options (TRI-STATE output push-pull output weak pull-up input high impedance input Emulation device for the COP888EG COP888GG and COP888HG Real time emulation and full program debug offered by MetaLink Development System Block Diagram TL DD12860 – 1 FIGURE 1 Block Diagram TRI-STATE is a registered trademark of National Semiconductor Corporation COP8TM MICROWIRETM MICROWIRE PLUSTM and WATCHDOGTM are trademarks of National Semiconductor Corporation iceMASTERTM is a trademark of MetaLink Corporation C1996 National Semiconductor Corporation TL DD12860 RRD-B30M106 Printed in U S A http www national com General Description (Continued) The device is a fully static part fabricated using double-metal silicon gate microCMOS technology Features include an 8-bit memory mapped architecture MICROWIRE PLUSTM serial I O three 16-bit timer counters supporting three modes (Processor Independent PWM generation External Event counter and Input Capture mode capabilities) full duplex UART and two comparators Each I O pin has software selectable configurations The devices operates over a voltage range of 2 7V to 5 5V High throughput is achieved with an efficient regular instruction set operating at a maximum rate of 1 ms per instruction TABLE I COP888CG EG GG HG Family Members Device COP888CG COP888EG COP888GG COP87L88GG COP888HG COP87L88RG ROM EPROM (Bytes) 4k ROM 8k ROM 16k ROM 16k OTP EPROM 20k ROM 32k OTP EPROM RAM (Bytes) 192 256 512 512 512 512 Key Common Features 3 Timers UART 2 Comparators Connection Diagrams Plastic Chip Carrier Dual-In-Line Package TL DD12860–2 Top View Order Number COP87L88RGV-XE See NS Package Number V44A Note -X Crystal Oscillator -E Halt Enable TL DD12860 – 3 Top View Order Number COP87L88RGN-XE See NS Package Number N40A FIGURE 2 Connection Diagrams http www national com 2 Connection Diagrams (Continued) Pinouts for 40- and 44-Pin Packages Port L0 L1 L2 L3 L4 L5 L6 L7 G0 G1 G2 G3 G4 G5 G6 G7 D0 D1 D2 D3 D4 D5 D6 D7 I0 I1 I2 I3 I4 I5 I6 I7 C0 C1 C2 C3 C4 C5 C6 C7 VCC GND CKI RESET I I I I I I I I Type O O O O O O O O Alt Fun MIWU MIWU MIWU MIWU MIWU MIWU MIWU MIWU INT T1B T1A SO SK SI HALT Restart Alt Fun 40-Pin DIP 17 18 19 20 21 22 23 24 35 36 37 38 3 4 5 6 25 26 27 28 29 30 31 32 COMP1INb COMP1IN a COMP1OUT COMP2INb COMP2IN a COMP2OUT O O O O O O O O 9 10 11 12 13 14 15 16 39 40 1 2 44-Pin PLCC 17 18 19 20 25 26 27 28 39 40 41 42 3 4 5 6 29 30 31 32 33 34 35 36 9 10 11 12 13 14 15 16 43 44 1 2 21 22 23 24 8 37 7 38 CKX TDX RDX T2A T2B T3A T3B IO WDOUT IO IO IO IO I I CKO O O O O O O O O I I I I I I I I I I I I I I I I 8 33 7 34 3 http www national com Absolute Maximum Ratings (Note) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage (VCC) Voltage at Any Pin Total Current into VCC Pin (Source) 7V b 0 3V to VCC a 0 3V 100 mA Total Current out of GND Pin (Sink) Storage Temperature Range 110 mA b 65 C to a 140 C Note Absolute maximum ratings indicate limits beyond which damage to the device may occur DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings DC Electrical Characteristics Parameter Operating Voltage Power Supply Ripple (Note 1) Supply Current (Note 2) CKI e 10 MHz CKI e 4 MHz HALT Current (Note 3) IDLE Current CKI e 10 MHz CKI e 1 MHz Input Levels RESET Logic High Logic Low CKI (External and Crystal Osc Modes) Logic High Logic Low All Other Inputs Logic High Logic Low Hi-Z Input Leakage Input Pullup Current G and L Port Input Hysteresis Output Current Levels D Outputs Source Sink (Note 4) All Others Source (Weak Pull-Up Mode) Source (Push-Pull Mode) Sink (Push-Pull Mode) TRI-STATE Leakage Allowable Sink Source Current per Pin D Outputs (Sink) All others Maximum Input Current without Latchup (Note 5) RAM Retention Voltage Vr Input Capacitance Load Capacitance on D2 Note 1 Rate of voltage change must be less then 0 5 V ms b 40 C s TA s a 85 C unless otherwise specified Conditions Peak-to-Peak VCC e 5 5V tc e 1 ms VCC e 4 0V tc e 2 5 ms VCC e 5 5V CKI e 0 MHz VCC e 4 0V CKI e 0 MHz VCC e 5 5V tc e 1 ms VCC e 4 0V tc e 10 ms Min 27 Typ Max 55 0 1 VCC 16 5 65 12 8 35 07 Units V V mA mA mA mA mA mA 0 8 VCC 0 2 VCC 0 7 VCC 0 2 VCC 0 7 VCC 0 2 VCC VCC e 5 5V VCC e 5 5V b2 a2 V V V V V V mA mA V 40 0 05 VCC 250 0 35 VCC VCC e 4 5V VOH e 3 3V VCC e 4 5V VOL e 1V VCC e 4 5V VOH e 2 7V VCC e 4 5V VOH e 3 3V VCC e 4 5V VOL e 0 4V VCC e 5 5V 04 10 10 04 16 b2 mA mA 100 mA mA mA mA a2 15 3 TA e 25 C 500 ns Rise and Fall Time (Min) 2 7 1000 g 100 mA mA mA V pF pF Note 2 Supply current is measured after running 2000 cycles with a square wave CKI input CKO open inputs at rails and outputs open Note 3 The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations by bringing CKI high Test conditions All inputs tied to VCC L and G ports in the TRI-STATE mode and tied to ground all outputs low and tied to ground The clock monitor is disabled Note 4 The user must guarantee that D2 pin does not source more than 10 mA during RESET If D2 sources more than 10 mA during reset the device will go into programming mode Note 5 Pins G6 and RESET are designed with a high voltage input network for factory testing These pins allow input voltages greater than VCC and the pins will have sink current to VCC when biased at voltages greater than VCC (the pins do not have source current when biased at a voltage below VCC) The effective resistance to VCC is 750X (typical) These two pins will not latch up The voltage at the pins must be limited to less than 14V http www national com 4 AC Electrical Characteristics Parameter Instruction Cycle Time (tc) Crystal Resonator R C Oscillator Inputs tSETUP tHOLD Output Propagation Delay tPD1 tPD0 SO SK All Others MICROWIRETM Setup Time (tUWS) MICROWIRE Hold Time (tUWH) MICROWIRE Output Propagation Delay (tUPD) Input Pulse Width Interrupt Input High Time Interrupt Input Low Time Timer Input High Time Timer Input Low Time Reset Pulse Width b 40 C s TA s a 85 C unless otherwise specified Conditions Min 1 3 200 60 Typ Max DC DC Units ms ms ns ns RL e 2 2k CL e 100 pF 07 1 20 56 220 1 1 1 1 1 ms ms ns ns ns tc tc tc tc ms Comparators AC and DC Characteristics VCC e 5V Parameter Input Offset Voltage Input Common Mode Voltage Range Low Level Output Current High Level Output Current DC Supply Current Per Comparator (When Enabled) Response Time TBD mV Step TBD mV Overdrive 100 pF Load VOL e 0 4V VOH e 4 6V Conditions 0 4V s VIN s VCC b 1 5V TA e 25 C Typ g 10 Min Max g 25 Units mV V mA mA 04 16 16 VCC b 1 5 250 1 mA ms TL DD12860 – 5 FIGURE 3 MICROWIRE PLUS Timing 5 http www national com Pin Descriptions VCC and GND are the power supply pins CKI is the clock input This can come from an R C generated oscillator or a crystal oscillator (in conjunction with CKO) See Oscillator Description section RESET is the master reset input See Reset Description section The device contains three bidirectional 8-bit I O ports (C G and L) where each individual bit may be independently configured as an input (Schmitt trigger inputs on ports L and G) output or TRI-STATE under program control Three data memory address locations are allocated for each of these I O ports Each I O port has two associated 8-bit memory mapped registers the CONFIGURATION register and the output DATA register A memory mapped address is also reserved for the input pins of each I O port (See the memory map for the various addresses associated with the I O ports ) Figure 4 shows the I O port configurations The DATA and CONFIGURATION registers allow for each port bit to be individually configured under software control as shown below CONFIGURATION Register 0 0 1 1 DATA Register 0 1 0 1 Port Set-Up Hi-Z Input (TRI-STATE Output) Input with Weak Pull-Up Push-Pull Zero Output Push-Pull One Output PORT L is an 8-bit I O port All L-pins have Schmitt triggers on the inputs Port L supports Multi-Input Wake Up (MIWU) on all eight pins L1 is used for the UART external clock L2 and L3 are used for the UART transmit and receive L4 and L5 are used for the timer input functions T2A and T2B L6 and L7 are used for the timer input functions T3A and T3B Port L has the following alternate features L0 MIWU L1 MIWU or CKX L2 MIWU or TDX L3 MIWU or RDX L4 MIWU or T2A L5 MIWU or T2B L6 MIWU or T3A L7 MIWU or T3B Port G is an 8-bit port with 5 I O pins (G0 G2 – G5) an input pin (G6) and two dedicated output pins (G1 and G7) Pins G0 and G2 – G6 all have Schmitt Triggers on their inputs Pin G1 serves as the dedicated WDOUT WATCHDOG output while pin G7 is either input or output depending on the oscillator mask option selected With the crystal oscillator option selected G7 serves as the dedicated output pin for the CKO clock output With the single-pin R C oscillator mask option selected G7 serves as a general purpose input pin but is also used to bring the device out of HALT mode with a low to high transition on G7 There are two registers associated with the G Port a data register and a configuration register Therefore each of the 5 I O bits (G0 G2 – G5) can be individually configured under software control TL DD12860 – 6 FIGURE 4 I O Port Configurations http www national com 6 Pin Descriptions (Continued) Since G6 is an input only pin and G7 is the dedicated CKO clock output pin (crystal clock option) or general purpose input (R C clock option) the associated bits in the data and configuration registers for G6 and G7 are used for special purpose functions as outlined below Reading the G6 and G7 data bits will return zeros Note that the chip will be placed in the HALT mode by writing a ‘‘1’’ to bit 7 of the Port G Data Register Similarly the chip will be placed in the IDLE mode by writing a ‘‘1’’ to bit 6 of the Port G Data Register Writing a ‘‘1’’ to bit 6 of the Port G Configuration Register enables the MICROWIRE PLUS to operate with the alternate phase of the SK clock The G7 configuration bit if set high enables the clock start up delay after HALT when the R C clock configuration is used Config Reg G7 G6 CLKDLY Alternate SK Data Reg HALT IDLE Functional Description The architecture of the device is modified Harvard architecture With the Harvard architecture the control store program memory (ROM) is separated from the data store memory (RAM) Both ROM and RAM have their own separate addressing space with separate address buses The architecture though based on Harvard architecture permits transfer of data from ROM to RAM CPU REGISTERS The CPU can do an 8-bit addition subtraction logical or shift operation in one instruction (tc) cycle time There are six CPU registers A is the 8-bit Accumulator Register PC is the 15-bit Program Counter Register PU is the upper 7 bits of the program counter (PC) PL is the lower 8 bits of the program counter (PC) B is an 8-bit RAM address pointer which can be optionally post auto incremented or decremented X is an 8-bit alternate RAM address pointer which can be optionally post auto incremented or decremented SP is the 8-bit stack pointer which points to the subroutine interrupt stack (in RAM) The SP is initialized to RAM address 06F with reset S is the 8-bit Data Segment Address Register used to extend the lower half of the address range (00 to 7F) into 256 data segments of 128 bytes each All the CPU registers are memory mapped with the exception of the Accumulator (A) and the Program Counter (PC) PROGRAM MEMORY The program memory consists of 32 kbytes of OTP EPROM These bytes may hold program instructions or constant data (data tables for the LAID instruction jump vectors for the JID instruction and interrupt vectors for the VIS instruction) The program memory is addressed by the 15-bit program counter (PC) All interrupts in the devices vector to program memory location 0FF Hex The device can be configured to inhibit external reads of the program memory This is done by programming the Security Byte Note Mask ROMed devices with equivalent on-chip features and program memory sizes of 4k 8k 16k 20k and 24k are available Port G has the following alternate features G0 INTR (External Interrupt Input) G2 T1B (Timer T1 Capture Input) G3 T1A (Timer T1 I O) G4 SO (MICROWIRE Serial Data Output) G5 SK (MICROWIRE Serial Clock) G6 SI (MICROWIRE Serial Data Input) Port G has the following dedicated functions G1 WDOUT WATCHDOG and or Clock Monitor dedicated output G7 CKO Oscillator dedicated output or general purpose input Port C is an 8-bit I O port The 40-pin device does not have a full complement of Port C pins The unavailable pins are not terminated A read operation for these unterminated pins will return unpredictable values PORT I is an eight-bit Hi-Z input port Port I1 – I3 are used for Comparator 1 Port I4–I6 are used for Comparator 2 The Port I has the following alternate features I1 COMP1bIN (Comparator 1 Negative Input) I2 COMP1 a IN (Comparator 1 Positive Input) I3 COMP1OUT (Comparator 1 Output) I4 COMP2bIN (Comparator 2 Negative Input) I5 COMP2 a IN (Comparator 2 Positive Input) I6 COMP2OUT (Comparator 2 Output) Port D is a recreated 8-bit output port that is preset high when RESET goes low D port recreation is one clock cycle behind normal port timing The user can tie two or more D port outputs (except D2) together in order to get a higher drive SECURITY FEATURE The program memory array has an associate Security Byte that is located outside of the program address range This byte can be addressed only from programming mode by a programmer tool Security is an optional feature and can only be asserted after the memory array has been programmed and verified A secured part will read all 00(hex) by a programmer The part will fail Blank Check and will fail Verify operations A Read operaiton will fill the programmer’s memory with 00(hex) The Security Byte itself is always readable with value of 00(hex) if unsecure and FF(hex) if secure DATA MEMORY The data memory address space includes the on-chip RAM and data registers the I O registers (Configuration Data and Pin) the control registers the MICROWIRE PLUS SIO shift register and the various registers and counters associated with the timers (with the exception of the IDLE timer) Data memory is addressed directly by the instruction or indirectly by the B X SP pointers and S register 7 http www national com Functional Description (Continued) The data memory consists of 512 bytes of RAM Sixteen bytes of RAM are mapped as ‘‘registers’’ at addresses 0F0 to 0FF Hex These registers can be loaded immediately and also decremented and tested with the DRSZ (decrement register and skip if zero) instruction The memory pointer registers X SP B and S are memory mapped into this space at address locations 0FC to 0FF Hex respectively with the other registers being available for general usage The instruction set permits any bit in memory to be set reset or tested All I O and registers (except A and PC) are memory mapped therefore I O bits and register bits can be directly and individually set reset and tested The accumulator (A) bits can also be directly and individually tested Note RAM contents are undefined upon power-up Data Memory Segment RAM Extension Data memory address 0FF is used as a memory mapped location for the Data Segment Address Register (S) The data store memory is either addressed directly by a single byte address within the instruction or indirectly relative to the reference of the B X or SP pointers (each contains a single-byte address) This single-byte address allows an addressing range of 256 locations from 00 to FF hex The upper bit of this single-byte address divides the data store memory into two separate sections as outlined previously With the exception of the RAM register memory from address locations 00F0 to 00FF all RAM memory is memory mapped with the upper bit of the single-byte address being equal to zero This allows the upper bit of the single-byte address to determine whether or not the base address range (from 0000 to 00FF) is extended If this upper bit equals one (representing address range 0080 to 00FF) then address extension does not take place Alternatively if this upper bit equals zero then the data segment extension register S is used to extend the base address range (from 0000 to 007F) from XX00 to XX7F where XX represents the 8 bits from the S register Thus the 128-byte data segment extensions are located from addresses 0100 to 017F for data segment 1 0200 to 027F for data segment 2 etc up to FF00 to FF7F for data segment 255 The base address range from 0000 to 007F represents data segment 0 Figure 5 illustrates how the S register data memory extension is used in extending the lower half of the base address range (00 to 7F hex) into 256 data segments of 128 bytes each with a total addressing range of 32 kbytes from XX00 to XX7F This organization allows a total of 256 data segments of 128 bytes each with an additional upper base segment of 128 bytes Furthermore all addressing modes are available for all data segments The S register must be changed under program control to move from one data segment (128 bytes) to another However the upper base segment (containing the 16 memory registers I O registers control registers etc ) is always available regardless of the contents of the S register since the upper base segment (address range 0080 to 00FF) is independent of data segment extension The instructions that utilize the stack pointer (SP) always reference the stack as part of the base segment (Segment 0) regardless of the contents of the S register The S register is not changed by these instructions Consequently the stack (used with subroutine linkage and interrupts) is always located in the base segment The stack pointer will be intitialized to point at data memory location 006F as a result of reset The 128 bytes of RAM contained in the base segment are split between the lower and upper base segments The first 116 bytes of RAM are resident from address 0000 to 006F in the lower base segment while the remaining 16 bytes of RAM represent the 16 data memory registers located at addresses 00F0 to 00FF of the upper base segment No RAM is located at the upper sixteen addresses (0070 to 007F) of the lower base segment Additional RAM beyond these initial 128 bytes however will always be memory mapped in groups of 128 bytes (or less) at the data segment address extensions (XX00 to XX7F) of the lower base segment The additional 128 bytes of RAM are memory mapped at address locations 0100 to 017F hex Reset The RESET input when pulled low initializes the microcontroller Initialization will occur whenever the RESET input is pulled low Upon initialization the data and configuration registers for ports L G and C are cleared resulting in these Reads as all ones TL DD12860 – 7 FIGURE 5 RAM Organization http www national com 8 Reset (Continued) Ports being initialized to the TRI-STATE mode Pin G1 of the G Port is an exception (as noted below) since pin G1 is dedicated as the WATCHDOG and or Clock Monitor error output pin Port D is set high The PC PSW ICNTRL CNTRL T2CNTRL and T3CNTRL control registers are cleared The UART registers PSR ENU (except that TBMT bit is set) ENUR and ENUI are cleared The Comparator Select Register is cleared The S register is initialized to zero The Multi-Input Wake Up registers WKEN WKEDG and WKPND are cleared The stack pointer SP is initialized to 6F Hex The device comes out of reset with both the WATCHDOG logic and the Clock Monitor detector armed with the WATCHDOG service window bits set and the Clock Monitor bit set The WATCHDOG and Clock Monitor circuits are inhibited during reset The WATCHDOG service window bits being initialized high default to the maximum WATCHDOG service window of 64k tc clock cycles The Clock Monitor bit being initialized high will cause a Clock Monitor error following reset if the clock has not reached the minimum specified frequency at the termination of reset A Clock Monitor error will cause an active low error output on pin G1 This error output will continue until 16 tc – 32 tc clock cycles following the clock frequency reaching the minimum specified value at which time the G1 output will enter the TRI-STATE mode The external RC network shown in Figure 6 should be used to ensure that the RESET pin is held low until the power supply to the chip stabilizes Note Continual state of reset will cause the device to draw excessive current CRYSTAL OSCILLATOR CKI and CKO can be connected to make a closed loop crystal (or resonator) controlled oscillator Table I shows the component values required for various standard crystal values TABLE I Crystal Oscillator Configuration TA e 25 C R1 (kX) 0 0 0 R2 (MX) 1 1 1 C1 (pF) 30 30 200 C2 (pF) 30 – 36 30 – 36 100 – 150 CKI Freq (MHz) 10 4 0 455 Conditions VCC e 5V VCC e 5V VCC e 5V R C OSCILLATOR By selecting CKI as a single pin oscillator input a single pin R C oscillator circuit can be connected to it CKO is available as a general purpose input and or HALT restart pin Table II shows the variation in the oscillator frequencies as functions of the component (R and C) values TABLE II R C Oscillator Configuration TA e 25 C R (kX) 33 56 68 C (pF) 82 100 100 CKI Freq (MHz) 2 2–2 7 1 1–1 3 0 9–1 1 Instr Cycle (ms) 3 7–4 6 7 4–9 0 8 8 – 10 8 Conditions VCC e 5V VCC e 5V VCC e 5V Note 3k s R s 200k 50 pF s C s 200 pF Control Registers CNTRL Register (Address X 00EE) The Timer1 (T1) and MICROWIRE PLUS control register contains the following bits SL1 SL0 Select the MICROWIRE PLUS clock divide by (00 e 2 01 e 4 1x e 8) IEDG External interrupt edge polarity select (0 e Rising edge 1 e Falling edge) MSEL Selects G5 and G4 as MICROWIRE PLUS signals SK and SO respectively T1C0 Timer T1 Start Stop control in timer modes 1 and 2 Timer T1 Underflow Interrupt Pending Flag in timer mode 3 T1C1 Timer T1 mode control bit T1C2 Timer T1 mode control bit T1C3 Timer T1 mode control bit T1C3 T1C2 T1C1 T1C0 MSEL IEDG Bit 7 SL1 SL0 Bit 0 TL DD 12860 – 8 RC l 5 c Power Supply Rise Time FIGURE 6 Recommended Reset Circuit Oscillator Circuits The chip can be driven by a clock input on the CKI input pin which can be between DC and 10 MHz The CKO output clock is on pin G7 (crystal configuration) The CKI input frequency is divided down by 10 to produce the instruction cycle clock (1 tc) Figure 7 shows the Crystal and R C diagrams TL DD12860 – 9 FIGURE 7 Crystal and R C Oscillator Diagrams 9 http www national com Control Registers (Continued) PSW Register (Address X 00EF) The PSW register contains the following select bits GIE EXEN BUSY EXPND T1ENA Global interrupt enable (enables interrupts) Enable external interrupt MICROWIRE PLUS busy shifting flag External interrupt pending Timer T1 Interrupt Enable for Timer Underflow or T1A Input capture edge T1PNDA Timer T1 Interrupt Pending Flag (Autoreload RA in mode 1 T1 Underflow in Mode 2 T1A capture edge in mode 3) C Carry Flag HC Half Carry Flag HC C T1PNDA T1ENA EXPND BUSY EXEN GIE T2C1 T2C2 T2C3 Timer T2 mode control bit Timer T2 mode control bit Timer T2 mode control bit T2C3 T2C2 T2C1 T2C0 T2PNDA T2ENA T2PNDB T2ENB Bit 7 Bit 0 Bit 7 Bit 0 The Half-Carry bit is also affected by all the instructions that affect the Carry flag The SC (Set Carry) and RC (Reset Carry) instructions will respectively set or clear both the carry flags In addition to the SC and RC instructions ADC SUBC RRC and RLC instructions affect the carry and Half Carry flags ICNTRL Register (Address X 00E8) The ICNTRL register contains the following bits T1ENB Timer T1 Interrupt Enable for T1B Input capture edge T1PNDB Timer T1 Interrupt Pending Flag for T1B capture edge WEN Enable MICROWIRE PLUS interrupt WPND MICROWIRE PLUS interrupt pending T0EN Timer T0 Interrupt Enable (Bit 12 toggle) T0PND Timer T0 Interrupt pending LPEN L Port Interrupt Enable (Multi-Input Wake Up Interrupt) Bit 7 could be used as a flag Unused LPEN T0PND T0EN WPND Bit 7 WEN T1PNDB T1ENB Bit 0 T3CNTRL Register (Address X 00B6) The T3CNTRL register contains the following bits T3ENB Timer T3 Interrupt Enable for T3B T3PNDB Timer T3 Interrupt Pending Flag for T3B pin (T3B capture edge) T3ENA Timer T3 Interrupt Enable for Timer Underflow or T3A pin T3PNDA Timer T3 Interrupt Pending Flag (Autoload RA in mode 1 T3 Underflow in mode 2 T3a capture edge in mode 3) T3C0 Timer T3 Start Stop control in timer modes 1 and 2 Timer T3 Underflow Interrupt Pending Flag in timer mode 3 Timer T3 mode control bit Timer T3 mode control bit Timer T3 mode control bit T3C1 T3C0 T3PNDA T3ENA T3PNDB T3ENB Bit 0 T3C1 T3C2 T3C3 T3C3 Bit 7 T3C2 Timers The device contains a very versatile set of timers (T0 T1 T2 T3) All timers and associated autoreload capture registers power up containing random data TIMER T0 (IDLE TIMER) The devices support applications that require maintaining real time and low power with the IDLE mode This IDLE mode support is furnished by the IDLE timer T0 which is a 16-bit timer The Timer T0 runs continuously at the fixed rate of the instruction cycle clock tc The user cannot read or write to the IDLE Timer T0 which is a count down timer The Timer T0 supports the following functions Exit out of the Idle Mode (See Idle Mode description) WATCHDOG logic (See WATCHDOG description) Start up delay out of the HALT mode The IDLE Timer T0 can generate an interrupt when the thirteenth bit toggles This toggle is latched into the T0PND pending flag and will occur every 4 ms at the maximum clock frequency (tc e 1 ms) A control flag T0EN allows the interrupt from the thirteenth bit of Timer T0 to be enabled or disabled Setting T0EN will enable the interrupt while resetting it will disable the interrupt T2CNTRL Register (Address X 00C6) The T2CNTRL register contains the following bits T2ENB Timer T2 Interrupt Enable for T2B Input capture edge T2PNDB Timer T2 Interrupt Pending Flag for T2B capture edge T2ENA Timer T2 Interrupt Enable for Timer Underflow or T2A Input capture edge T2PNDA Timer T2 Interrupt Pending Flag (Autoreload RA in mode 1 T2 Underflow in mode 2 T2A capture edge in mode 3) T2C0 Timer T2 Start Stop control in timer modes 1 and 2 Timer T2 Underflow Interrupt Pending Flag in timer mode 3 http www national com 10 Timers (Continued) TIMER T1 TIMER T2 AND TIMER T3 The devices have a set of three powerful timer counter blocks T1 T2 and T3 The associated features and functioning of a timer block are described by referring to the timer block Tx Since the three timer blocks T1 T2 and T3 are identical all comments are equally applicable to any of the three timer blocks Each timer block consists of a 16-bit timer Tx and two supporting 16-bit autoreload capture registers RxA and RxB Each timer block has two pins associated with it TxA and TxB The pin TxA supports I O required by the timer block while the pin TxB is an input to the timer block The powerful and flexible timer block allows the device to easily perform all timer functions with minimal software overhead The timer block has three operating modes Processor Independent PWM mode External Event Counter mode and Input Capture mode The control bits TxC3 TxC2 and TxC1 allow selection of the different modes of operation Mode 1 Processor Independent PWM Mode As the name suggests this mode allows the device to generate a PWM signal with very minimal user intervention The user only has to define the parameters of the PWM signal (ON time and OFF time) Once begun the timer block will continuously generate the PWM signal completely independent of the microcontroller The user software services the timer block only when the PWM parameters require updating In this mode the timer Tx counts down at a fixed rate of tc Upon every underflow the timer is alternately reloaded with the contents of supporting registers RxA and RxB The very first underflow of the timer causes the timer to reload from the register RxA Subsequent underflows cause the timer to be reloaded from the registers alternately beginning with the register RxB The Tx Timer control bits TxC3 TxC2 and TxC1 set up the timer for PWM mode operation TL DD12860 – 10 FIGURE 8 Timer in PWM Mode Mode 2 External Event Counter Mode This mode is quite similar to the processor independent PWM mode described above The main difference is that the timer Tx is clocked by the input signal from the TxA pin The Tx timer control bits TxC3 TxC2 and TxC1 allow the timer to be clocked either on a positive or negative edge from the TxA pin Underflows from the timer are latched into the TxPNDA pending flag Setting the TxENA control flag will cause an interrupt when the timer underflows In this mode the input pin TxB can be used as an independent positive edge sensitive interrupt input if the TxENB control flag is set The occurrence of a positive edge on the TxB input pin is latched into the TxPNDB flag Figure 9 shows a block diagram of the timer in External Event Counter mode Note The PWM output is not available in this mode since the TxA pin is being used as the counter input clock Figure 8 shows a block diagram of the timer in PWM mode The underflows can be programmed to toggle the TxA output pin The underflows can also be programmed to generate interrupts Underflows from the timer are alternately latched into two pending flags TxPNDA and TxPNDB The user must reset these pending flags under software control Two control enable flags TxENA and TxENB allow the interrupts from the timer underflow to be enabled or disabled Setting the timer enable flag TxENA will cause an interrupt when a timer underflow causes the RxA register to be reloaded into the timer Setting the timer enable flag TxENB will cause an interrupt when a timer underflow causes the RxB register to be reloaded into the timer Resetting the timer enable flags will disable the associated interrupts Either or both of the timer underflow interrupts may be enabled This gives the user the flexibility of interrupting once per PWM period on either the rising or falling edge of the PWM output Alternatively the user may choose to interrupt on both edges of the PWM output TL DD12860 – 11 FIGURE 9 Timer in External Event Counter Mode Mode 3 Input Capture Mode The device can precisely measure external frequencies or time external events by placing the timer block Tx in the input capture mode In this mode the timer Tx is constantly running at the fixed tc rate The two registers RxA and RxB act as capture registers Each register acts in conjunction with a pin The register RxA acts in conjunction with the TxA pin and the register RxB acts in conjunction with the TxB pin 11 http www national com Timers (Continued) The timer value gets copied over into the register when a trigger event occurs on its corresponding pin Control bits TxC3 TxC2 and TxC1 allow the trigger events to be specified either as a positive or a negative edge The trigger condition for each input pin can be specified independently The trigger conditions can also be programmed to generate interrupts The occurrence of the specified trigger condition on the TxA and TxB pins will be respectively latched into the pending flags TxPNDA and TxPNDB The control flag TxENA allows the interrupt on TxA to be either enabled or disabled Setting the TxENA flag enables interrupts to be generated when the selected trigger condition occurs on the TxA pin Similarly the flag TxENB controls the interrupts from the TxB pin Underflows from the timer can also be programmed to generate interrupts Underflows are latched into the timer TxC0 pending flag (the TxC0 control bit serves as the timer underflow interrupt pending flag in the Input Capture mode) Consequently the TxC0 control bit should be reset when entering the Input Capture mode The timer underflow interrupt is enabled with the TxENA control flag When a TxA interrupt occurs in the Input Capture mode the user must check both the TxPNDA and TxC0 pending flags in order to determine whether a TxA input capture or a timer underflow (or both) caused the interrupt TL DD12860 – 12 FIGURE 10 Timer in Input Capture Mode TIMER CONTROL FLAGS The timers T1 T2 and T3 have indentical control structures The control bits and their functions are summarized below TxC0 Timer Start Stop control in Modes 1 and 2 (Processor Independent PWM and External Event Counter) where 1 e Start 0 e Stop Timer Underflow Interrupt Pending Flag in Mode 3 (Input Capture) TxPNDA Timer Interrupt Pending Flag TxPNDB Timer Interrupt Pending Flag TxENA Timer Interrupt Enable Flag TxENB Timer Interrupt Enable Flag 1 e Timer Interrupt Enabled 0 e Timer Interrupt Disabled TxC3 Timer mode control TxC2 Timer mode control TxC1 Timer mode control Figure 10 shows a block diagram of the timer in Input Capture mode http www national com 12 Timers (Continued) The timer mode control bits (TxC3 TxC2 and TxC1) are detailed below TxC3 0 0 1 1 0 TxC2 0 0 0 0 1 TxC1 0 1 1 0 0 Timer Mode MODE 2 (External Event Counter) MODE 2 (External Event Counter) MODE 1 (PWM) TxA Toggle MODE 1 (PWM) No TxA Toggle MODE 3 (Capture) Captures TxA Pos Edge TxB Pos Edge MODE 3 (Capture) Captures TxA Pos Edge TxB Neg Edge MODE 3 (Capture) Captures TxA Neg Edge TxB Pos Edge MODE 3 (Capture) Captures TxA Neg Edge TxB Neg Edge Interrupt A Source Timer Underflow Timer Underflow Autoreload RA Autoreload RA Pos TxA Edge or Timer Underflow Pos TxA Edge or Timer Underflow Neg TxA Edge or Timer Underflow Neg TxA Edge or Timer Underflow Interrupt B Source Pos TxB Edge Pos TxB Edge Autoreload RB Autoreload RB Pos TxB Edge Timer Counts On TxA Pos Edge TxA Neg Edge tc tc tc 1 1 0 Neg TxB Edge tc 0 1 1 Pos TxB Edge tc 1 1 1 Neg TxB Edge tc Power Save Modes The devices offer the user two power save modes of operation HALT and IDLE In the HALT mode all microcontroller activities are stopped In the IDLE mode the on-board oscillator circuitry the WATCHDOG logic the Clock Monitor and timer T0 are active but all other microcontroller activities are stopped In either mode all on-board RAM registers I O states and timers (with the exception of T0) are unaltered HALT MODE The devices can be placed in the HALT mode by writing a ‘‘1’’ to the HALT flag (G7 data bit) All microcontroller activities including the clock and timers are stopped The WATCHDOG logic on the device is disabled during the HALT mode However the clock monitor circuitry if enabled remains active and will cause the WATCHDOG output pin (WDOUT) to go low If the HALT mode is used and the user does not want to activate the WDOUT pin the Clock Monitor should be disabled after the device comes out of reset (resetting the Clock Monitor control bit with the first write to the WDSVR register) In the HALT mode the power requirements of the device are minimal and the applied voltage (VCC) may be decreased to Vr (Vr e 2 0V) without altering the state of the machine The devices support three different ways of exiting the HALT mode The first method of exiting the HALT mode is with the Multi-Input Wake Up feature on the L port The second method is with a low to high transition on the CKO (G7) pin This method precludes the use of the crystal clock configuration (since CKO becomes a dedicated output) and so may be used with an RC clock configuration The third method of exiting the HALT mode is by pulling the RESET pin low Since a crystal or ceramic resonator may be selected as the oscillator the Wake Up signal is not allowed to start the chip running immediately since crystal oscillators and ceramic resonators have a delayed start up time to reach full amplitude and frequency stability The IDLE timer is used to generate a fixed delay to ensure that the oscillator has indeed stabilized before allowing instruction execution In this case upon detecting a valid Wake Up signal only the oscillator circuitry is enabled The IDLE timer is loaded with a value of 256 and is clocked with the tc instruction cycle clock The tc clock is derived by dividing the oscillator clock down by a factor of 10 The Schmitt trigger following the CKI inverter on the chip ensures that the IDLE timer is clocked only when the oscillator has a sufficiently large amplitude to meet the Schmitt trigger specifications This Schmitt trigger is not part of the oscillator closed loop The startup timeout from the IDLE timer enables the clock signals to be routed to the rest of the chip If an RC clock option is being used the fixed delay is introduced optionally A control bit CLKDLY mapped as configuration bit G7 controls whether the delay is to be introduced or not The delay is included if CLKDLY is set and excluded if CLKDLY is reset The CLKDLY bit is cleared on reset 13 http www national com Power Save Modes (Continued) The WATCHDOG detector circuit is inhibited during the HALT mode However the clock monitor circuit if enabled remains active during HALT mode in order to ensure a clock monitor error if the device inadvertently enters the HALT mode as a result of a runaway program or power glitch IDLE MODE The device is placed in the IDLE mode by writing a ‘‘1’’ to the IDLE flag (G6 data bit) In this mode all activities except the associated on-board oscillator circuitry the WATCHDOG logic the clock monitor and the IDLE Timer T0 are stopped The power supply requirements of the micro-controller in this mode of operation are typically around 30% of normal power requirement of the microcontroller As with the HALT mode the device can be returned to normal operation with a reset or with a Multi-Input Wake Up from the L Port Alternately the microcontroller resumes normal operation from the IDLE mode when the thirteenth bit (representing 4 096 ms at internal clock frequency of 1 MHz tc e 1 ms) of the IDLE Timer toggles This toggle condition of the thirteenth bit of the IDLE Timer T0 is latched into the T0PND pending flag The user has the option of being interrupted with a transition on the thirteenth bit of the IDLE Timer T0 The interrupt can be enabled or disabled via the T0EN control bit Setting the T0EN flag enables the interrupt and vice versa The user can enter the IDLE mode with the Timer T0 interrupt enabled In this case when the T0PND bit gets set the device will first execute the Timer T0 interrupt service routine and then return to the instruction following the ‘‘Enter Idle Mode’’ instruction Alternatively the user can enter the IDLE mode with the IDLE Timer T0 interrupt disabled In this case the device will resume normal operation with the instruction immediately following the ‘‘Enter IDLE Mode’’ instruction Note It is necessary to program two NOP instructions following both the set HALT mode and set IDLE mode instructions These NOP instructions are necessary to allow clock resynchronization following the HALT or IDLE modes Due to the on-board 8k EPROM with port recreation logic the HALT IDLE current is much higher compared to the equivalent masked port Multi-Input Wake Up The Multi-Input Wake Up feature is ued to return (Wake Up) the device from either the HALT or IDLE modes Alternately Multi-Input Wake Up Interrupt feature may also be used to generate up to 8 edge selectable external interrupts Figure 11 shows the Multi-Input Wake Up logic The MultiInput Wake Up feature utilizes the L Port The user selects which particular L port bit (or combination of L Port bits) will cause the device to exit the HALT or IDLE modes The selection is done through the Reg WKEN The Reg WKEN TL DD12860 – 13 FIGURE 11 Multi-Input Wake Up Logic http www national com 14 Multi-Input Wake Up (Continued) is an 8-bit read write register which contains a control bit for every L port bit Setting a particular WKEN bit enables a Wake Up from the associated L port pin The user can select whether the trigger condition on the selected L Port pin is going to be either a positive edge (low to high transition) or a negative edge (high to low transition) This selection is made via the Reg WKEDG which is an 8-bit control register with a bit assigned to each L Port pin Setting the control bit will select the trigger condition to be a negative edge on that particular L Port pin Resetting the bit selects the trigger condition to be a positive edge Changing an edge select entails several steps in order to avoid a pseudo Wake Up condition as a result of the edge change First the associated WKEN bit should be reset followed by the edge select change in WKEDG Next the associated WKPND bit should be cleared followed by the associated WKEN bit being re-enabled An example may serve to clarify this procedure Suppose we wish to change the edge select from positive (low going high) to negative (high going low) for L Port bit 5 where bit 5 has previously been enabled for an input interrupt The program would be as follows RBIT 5 WKEN SBIT 5 WKEDG RBIT 5 WKPND SBIT 5 WKEN If the L port bits have been used as outputs and then changed to inputs with Multi-Input Wake Up Interrupt a safety procedure should also be followed to avoid inherited pseudo wakeup conditions After the selected L port bits have been changed from output to input but before the associated WKEN bits are enabled the associated edge select bits in WKEDG should be set or reset for the desired edge selects followed by the associated WKPND bits being cleared This same procedure should be used following reset since the L port inputs are left floating as a result of reset The occurrence of the selected trigger condition for Multi-Input Wake Up is latched into a pending register called WKPND The respective bits of the WKPND register will be set on the occurrence of the selected trigger edge on the corresponding Port L pin The user has the responsibility of clearing these pending flags Since WKPND is a pending register for the occurrence of selected Wake Up conditions the device will not enter the HALT mode if any Wake Up bit is both enabled and pending Consequently the user has the responsibility of clearing the pending flags before attempting to enter the HALT mode WKEN WKPND and WKEDG are all read write registers and are cleared at reset PORT L INTERRUPTS Port L provides the user with an additional eight fully selectable edge sensitive interrupts which are all vectored into the same service subroutine The interrupt from Port L shares logic with the wake up circuitry The register WKEN allows interrupts from Port L to be individually enabled or disabled The register WKEDG specifies the trigger condition to be either a positive or a negative edge Finally the register WKPND latches in the pending trigger conditions The GIE (Global Interrupt Enable) bit enables the interrupt function A control flag LPEN functions as a global interrupt enable for Port L interrupts Setting the LPEN flag will enable interrupts and vice versa A separate global pending flag is not needed since the register WKPND is adequate Since Port L is also used for waking the device out of the HALT or IDLE modes the user can elect to exit the HALT or IDLE modes either with or without the interrupt enabled If he elects to disable the interrupt then the device will restart execution from the instruction immediately following the instruction that placed the microcontroller in the HALT or IDLE modes In the other case the device will first execute the interrupt service routine and then revert to normal operation The Wake Up signal will not start the chip running immediately since crystal oscillators or ceramic resonators have a finite start up time The IDLE Timer (T0) generates a fixed delay to ensure that the oscillator has indeed stabilized before allowing the device to execute instructions In this case upon detecting a valid Wake Up signal only the oscillator circuitry and the IDLE Timer T0 are enabled The IDLE Timer is loaded with a value of 256 and is clocked from the tc instruction cycle clock The tc clock is derived by dividing down the oscillator clock by a factor of 10 A Schmitt trigger following the CKI on-chip inverter ensures that the IDLE timer is clocked only when the oscillator has a sufficiently large amplitude to meet the Schmitt trigger specifications This Schmitt trigger is not part of the oscillator closed loop The startup timeout from the IDLE timer enables the clock signals to be routed to the rest of the chip If the RC clock option is used the fixed delay is under software control A control flag CLKDLY in the G7 configuration bit allows the clock start up delay to be optionally inserted Setting CLKDLY flag high will cause clock start up delay to be inserted and resetting it will exclude the clock start up delay The CLKDLY flag is cleared during reset so the clock start up delay is not present following reset with the RC clock options 15 http www national com UART The device contains a full-duplex software programmable UART The UART (Figure 12) consists of a transmit shift register a receiver shift register and seven addressable registers as follows a transmit buffer register (TBUF) a receiver buffer register (RBUF) a UART control and status register (ENU) a UART receive control and status register (ENUR) a UART interrupt and clock source register (ENUI) a prescaler select register (PSR) and baud (BAUD) register The ENU register contains flags for transmit and receive functions this register also determines the length of the data frame (7 8 or 9 bits) the value of the ninth bit in transmission and parity selection bits The ENUR register flags framing data overrun and parity errors while the UART is receiving Other functions of the ENUR register include saving the ninth bit received in the data frame enabling or disabling the UART’s attention mode of operation and providing additional receiver transmitter status information via RCVG and XMTG bits The determination of an internal or external clock source is done by the ENUI register as well as selecting the number of stop bits and enabling or disabling transmit and receive interrupts A control flag in this register can also select the UART mode of operation asynchronous or synchronous TL DD12860 – 14 FIGURE 12 UART Block Diagram http www national com 16 UART (Continued) UART CONTROL AND STATUS REGISTERS The operation of the UART is programmed through three registers ENU ENUR and ENUI The function of the individual bits in these registers is as follows ENU-UART Control and Status Register (Address at 0BA) PSEL1 XBIT9 CHL1 PSEL0 0RW 0RW 0RW 0RW Bit 7 PEN CHL0 0RW ERR 0R RBFL TBMT 0R 1R Bit 0 PSEL1 e 1 PSEL0 e 0 PSEL1 e 1 PSEL1 e 1 Mark(1) (if Parity enabled) Space(0) (if Parity enabled) PEN This bit enables disables Parity (7- and 8-bit modes only) PEN e 0 Parity disabled PEN e 1 Parity enabled ENUR UART RECEIVE CONTROL AND STATUS REGISTER RCVG This bit is set high whenever a framing error occurs and goes low when RDX goes high XMTG This bit is set to indicate that the UART is transmitting It gets reset at the end of the last frame (end of last Stop bit) ATTN ATTENTION Mode is enabled while this bit is set This bit is cleared automatically on receiving a character with data bit nine set RBIT9 Contains the ninth data bit received when the UART is operating with nine data bits per frame SPARE Reserved for future use PE Flags a Parity Error PE e 0 Indicates no Parity Error has been detected since the last time the ENUR register was read PE e 1 Indicates the occurrence of a Parity Error FE Flags a Framing Error FE e 0 Indicates no Framing Error has been detected since the last time the ENUR register was read FE e 1 Indicates the occurrence of a Framing Error DOE Flags a Data Overrun Error DOE e 0 Indicates no Data Overrun Error has been detected since the last time the ENUR register was read DOE e 1 Indicates the occurrence of a Data Overrun Error ENUI UART INTERRUPT AND CLOCK SOURCE REGISTER ETI This bit enables disables interrupt from the transmitter section ETI e 0 Interrupt from the transmitter is disabled ETI e 1 Interrupt from the transmitter is enabled ERI This bit enables disables interrupt from the receiver section ERI e 0 Interrupt from the receiver is disabled ERI e 1 Interrupt from the receiver is enabled XTCLK This bit selects the clock source for the transmitter section XTCLK e 0 The clock source is selected through the PSR and BAUD registers XTCLK e 1 Signal on CKX (L1) pin is used as the clock XRCLK This bit selects the clock source for the receiver section XRCLK e 0 The clock source is selected through the PSR and BAUD registers XRCLK e 1 Signal on CKX (L1) pin is used as the clock SSEL UART mode select SSEL e 0 Asynchronous Mode SSEL e 1 Synchronous Mode ENUR-UART Receive Control and Status Register (Address at 0BB) DOE 0RD Bit7 FE 0RD PE SPARE RBIT9 ATTN XMTG RCVG 0RD 0RW 0R 0RW 0R 0R Bit0 ENUI-UART Interrupt and Clock Source Register (Address at 0BC) STP2 STP78 ETDX 0RW 0RW 0RW Bit7 Bit is not used 0 1 R D Bit is cleared on reset Bit is set to one on reset Bit is read-only it cannot be written by software Bit is cleared on read when read by software as a one it is cleared automatically Writing to the bit does not affect its state SSEL XRCLK XTCLK ERI 0RW 0RW 0RW 0RW ETI 0RW Bit0 RW Bit is read write DESCRIPTION OF UART REGISTER BITS ENU UART CONTROL AND STATUS REGISTER TBMT This bit is set when the UART transfers a byte of data from the TBUF register into the TSFT register for transmission It is automatically reset when software writes into the TBUF register RBFL This bit is set when the UART has received a complete character and has copied it into the RBUF register It is automatically reset when software reads the character from RBUF ERR This bit is a global UART error flag which gets set if any or a combination of the errors (DOE FE PE) occur CHL1 CHL0 These bits select the character frame format Parity is not included and is generated verified by hardware CHL1 e 0 CHL0 e 0 The frame contains eight data bits CHL1 e 0 CHL0 e 1 The frame contains seven data bits CHL1 e 1 CHL0 e 0 The frame contains nine data bits CHL1 e 1 CHL0 e 1 Loopback Mode selected Transmitter output internally looped back to receiver input Nine bit framing format is used XBIT9 PSEL0 Programs the ninth bit for transmission when the UART is operating with nine data bits per frame For seven or eight data bits per frame this bit in conjunction with PSEL1 selects parity PSEL1 PSEL0 Parity select bits PSEL1 e 0 PSEL0 e 0 Odd Parity (if Parity enabled) PSEL1 e 0 PSEL0 e 1 Odd Parity (if Parity enabled) 17 http www national com UART (Continued) ETDX TDX (UART Transmit Pin) is the alternate function assigned to Port L pin L2 it is selected by setting ETDX bit To simulate line break generation software should reset ETDX bit and output logic zero to TDX pin through Port L data and configuration registers STP78 This bit is set to program the last Stop bit to be 7 8th of a bit in length STP2 This bit programs the number of Stop bits to be transmitted STP2 e 0 One Stop bit transmitted STP2 e 1 Two Stop bits transmitted when a framing error occurs and goes low once RDX goes high TBMT XMTG RBFL and RCVG are read only bits SYNCHRONOUS MODE In this mode data is transferred synchronously with the clock Data is transmitted on the rising edge and received on the falling edge of the synchronous clock This mode is selected by setting SSEL bit in the ENUI register The input frequency to the UART is the same as the baud rate When an external clock input is selected at the CKX pin data transmit and receive are performed synchronously with this clock through TDX RDX pins If data transmit and receive are selected with the CKX pin as clock output the device generates the synchronous clock output at the CKX pin The internal baud rate generator is used to produce the synchronous clock Data transmit and receive are performed synchronously with this clock FRAMING FORMATS The UART supports several serial framing formats (Figure 13) The format is selected using control bits in the ENU ENUR and ENUI registers The first format (1 1a 1b 1c) for data transmission (CHL0 e 1 CHL1 e 0) consists of Start bit seven Data bits (excluding parity) and 7 8 one or two Stop bits In applications using parity the parity bit is generated and verified by hardware The second format (CHL0 e 0 CHL1 e 0) consists of one Start bit eight Data bits (excluding parity) and 7 8 one or two Stop bits Parity bit is generated and verified by hardware The third format for transmission (CHL0 e 0 CHL1 e 1) consists of one Start bit nine Data bits and 7 8 one or two Stop bits This format also supports the UART ‘‘ATTENTION’’ feature When operating in this format all eight bits of TBUF and RBUF are used for data The ninth data bit is transmitted and received using two bits in the ENU and ENUR registers called XBIT9 and RBIT9 RBIT9 is a read only bit Parity is not generated or verified in this mode For any of the above framing formats the last Stop bit can be programmed to be 7 8th of a bit in length If two Stop bits are selected and the 7 8th bit is set (selected) the second Stop bit will be 7 8th of a bit in length The parity is enabled disabled by PEN bit located in the ENU register Parity is selected for 7- and 8-bit modes only If parity is enabled (PEN e 1) the parity selection is then performed by PSEL0 and PSEL1 bits located in the ENU register Note that the XBIT9 PSEL0 bit located in the ENU register serves two mutually exclusive functions This bit programs the ninth bit for transmission when the UART is operating with nine data bits per frame There is no parity selection in this framing format For other framing formats XBIT9 is not needed and the bit is PSEL0 used in conjunction with PSEL1 to select parity The frame formats for the receiver differ from the transmitter in the number of Stop bits required The receiver only requires one Stop bit in a frame regardless of the setting of the Stop bit selection bits in the control register Note that an implicit assumption is made for full duplex UART operation that the framing formats are the same for the transmitter and receiver Associated I O Pins Data is transmitted on the TDX pin and received on the RDX pin TDX is the alternate function assigned to Port L pin L2 it is selected by setting ETDX (in the ENUI register) to one RDX is an inherent function of Port L pin L3 requiring no setup The baud rate clock for the UART can be generated onchip or can be taken from an external source Port L pin L1 (CKX) is the external clock I O pin The CKX pin can be either an input or an output as determined by Port L Configuration and Data registers (Bit 1) As an input it accepts a clock signal which may be selected to drive the transmitter and or receiver As an output it presents the internal Baud Rate Generator output UART Operation The UART has two modes of operation asynchronous mode and synchronous mode ASYNCHRONOUS MODE This mode is selected by resetting the SSEL (in the ENUI register) bit to zero The input frequency to the UART is 16 times the baud rate The TSFT and TBUF registers double-buffer data for transmission While TSFT is shifting out the current character on the TDX pin the TBUF register may be loaded by software with the next byte to be transmitted When TSFT finishes transmitting the current character the contents of TBUF are transferred to the TSFT register and the Transmit Buffer Empty Flag (TBMT in the ENU register) is set The TBMT flag is automatically reset by the UART when software loads a new character into the TBUF register There is also the XMTG bit which is set to indicate that the UART is transmitting This bit gets reset at the end of the last frame (end of last Stop bit) TBUF is a read write register The RSFT and RBUF registers double-buffer data being received The UART receiver continually monitors the signal on the RDX pin for a low level to detect the beginning of a Start bit Upon sensing this low level it waits for half a bit time and samples again If the RDX pin is still low the receiver considers this to be a valid Start bit and the remaining bits in the character frame are each sampled a single time at the mid-bit position Serial data input on the RDX pin is shifted into the RSFT register Upon receiving the complete character the contents of the RSFT register are copied into the RBUF register and the Received Buffer Full Flag (RBFL) is set RBFL is automatically reset when software reads the character from the RBUF register RBUF is a read only register There is also the RCVG bit which is set high http www national com 18 UART Operation (Continued) TL DD12860 – 15 FIGURE 13 Framing Formats UART INTERRUPTS The UART is capable of generating interrupts Interrupts are generated on Receive Buffer Full and Transmit Buffer Empty Both interrupts have individual interrupt vectors Two bytes of program memory space are reserved for each interrupt vector The two vectors are located at addresses 0xEC to 0xEF Hex in the program memory space The interrupts can be individually enabled or disabled using Enable Transmit Interrupt (ETI) and Enable Receive Interrupt (ERI) bits in the ENUI register The interrupt from the transmitter is set pending and remains pending as long as both the TBMT and ETI bits are set To remove this interrupt software must either clear the ETI bit or write to the TBUF register (thus clearing the TBMT bit) The interrupt from the receiver is set pending and remains pending as long as both the RBFL and ERI bits are set To remove this interrupt software must either clear the ERI bit or read from the RBUF register (thus clearing the RBFL bit) source selected in the PSR and BAUD registers Internally the basic baud clock is created from the oscillator frequency through a two-stage divider chain consisting of a 1 – 16 (increments of 0 5) prescaler and an 11-bit binary counter (Figure 14) The divide factors are specified through two read write registers shown in Figure 15 Note that the 11-bit Baud Rate Divisor spills over into the Prescaler Select Register (PSR) PSR is cleared upon reset As shown in Table III a Prescaler Factor of 0 corresponds to NO CLOCK NO CLOCK condition is the UART power down mode where the UART clock is turned off for power saving purpose The user must also turn the UART clock off when a different baud rate is chosen The correspondences between the 5-bit Prescaler Select and Prescaler factors are shown in Table III There are many ways to calculate the two divisor factors but one particularly effective method would be to achieve a 1 8432 MHz frequency coming out of the first stage The 1 8432 MHz prescaler output is then used to drive the software programmable baud rate counter to create a x16 clock for the following baud rates 110 134 5 150 300 600 1200 1800 2400 3600 4800 7200 9600 19200 and 38400 (Table IV) Other baud rates may be created by using appropriate divisors The x16 clock is then divided by 16 to provide the rate for the serial shift registers of the transmitter and receiver Baud Clock Generation The clock inputs to the transmitter and receiver sections of the UART can be individually selected to come either from an external source at the CKX pin (port L pin L1) or from a 19 http www national com Baud Clock Generation (Continued) TL DD12860 – 16 FIGURE 14 UART BAUD Clock Generation TL DD12860 – 17 FIGURE 15 UART BAUD Clock Divisor Registers TABLE III Prescaler Factors Prescaler Select 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 Prescaler Factor NO CLOCK 1 15 2 25 3 35 4 45 5 55 6 65 7 75 8 Prescaler Select 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Prescaler Factor 85 9 95 10 10 5 11 11 5 12 12 5 13 13 5 14 14 5 15 15 5 16 TABLE IV Baud Rate Divisors (1 8432 MHz Prescaler Output) Baud Rate 110 (110 03) 134 5 (134 58) 150 300 600 1200 1800 2400 3600 4800 7200 9600 19200 38400 Baud Rate Divisor b 1 (N-1) 1046 855 767 383 191 95 63 47 31 23 15 11 5 2 Note The entries in Table IV assume a prescaler output of 1 8432 MHz In the asynchronous mode the baud rate could be as high as 625k As an example considering the Asynchronous Mode and a CKI clock of 4 608 MHz the prescaler factor selected is 4 608 1 8432 e 2 5 The 2 5 entry is available in Table III The 1 8432 MHz prescaler output is then used with proper Baud Rate Divisor (Table II) to obtain different baud rates For a baud rate of 19200 e g the entry in Table IV is 5 N b 1 e 5 (N b 1 is the value from Table IV) N e 6 (N is the Baud Rate Divisor) Baud Rate e 1 8432 MHz (16 c 6) e 19200 The divide by 16 is performed because in the asynchronous mode the input frequency to the UART is 16 times the baud rate The equation to calculate baud rates is given below The actual Baud Rate may be found from BR e Fc (16 c N c P) http www national com 20 Baud Clock Generation (Continued) Where BR is the Baud Rate Fc is the CKI frequency N is the Baud Rate Divisor (Table IV) P is the Prescaler Divide Factor selected by the value in the Prescaler Select Register (Table III) Note In the Synchronous Mode the divisor 16 is replaced by two Note that the framing format for this mode is the nine bit format one Start bit nine data bits and 7 8 one or two Stop bits Parity is not generated or verified in this mode Attention Mode The UART Receiver section supports an alternate mode of operation referred to as ATTENTION Mode This mode of operation is selected by the ATTN bit in the ENUR register The data format for transmission must also be selected as having nine Data bits and either 7 8 one or two Stop bits The ATTENTION mode of operation is intended for use in networking the device with other processors Typically in such environments the messages consists of device addresses indicating which of several destinations should receive them and the actual data This Mode supports a scheme in which addresses are flagged by having the ninth bit of the data field set to a 1 If the ninth bit is reset to a zero the byte is a Data byte While in ATTENTION mode the UART monitors the communication flow but ignores all characters until an address character is received Upon receiving an address character the UART signals that the character is ready by setting the RBFL flag which in turn interrupts the processor if UART Receiver interrupts are enabled The ATTN bit is also cleared automatically at this point so that data characters as well as address characters are recognized Software examines the contents of the RBUF and responds by deciding either to accept the subsequent data stream (by leaving the ATTN bit reset) or to wait until the next address character is seen (by setting the ATTN bit again) Operation of the UART Transmitter is not affected by selection of this Mode The value of the ninth bit to be transmitted is programmed by setting XBIT9 appropriately The value of the ninth bit received is obtained by reading RBIT9 Since this bit is located in ENUR register where the error flags reside a bit operation on it will reset the error flags Example Asynchronous Mode Crystal Frequency e 5 MHz Desired baud rate e 9600 Using the above equation N c P can be calculated first N c P e (5 c 106) (16 c 9600) e 32 552 Now 32 552 is divided by each Prescaler Factor (Table III) to obtain a value closest to an integer This factor happens to be 6 5 (P e 6 5) N e 32 552 6 5 e 5 008 (N e 5) The programmed value (from Table IV) should be 4 (N b 1) Using the above values calculated for N and P BR e (5 c 106) (16 c 5 c 6 5) e 9615 384 % error e (9615 385 b 9600) 9600 e 0 16 Effect of HALT IDLE The UART logic is reinitialized when either the HALT or IDLE modes are entered This reinitialization sets the TBMT flag and resets all read only bits in the UART control and status registers Read Write bits remain unchanged The Transmit Buffer (TBUF) is not affected but the Transmit Shift register (TSFT) bits are set to one The receiver registers RBUF and RSFT are not affected The device will exit from the HALT IDLE modes when the Start bit of a character is detected at the RDX (L3) pin This feature is obtained by using the Multi-Input Wake Up scheme provided on the device Before entering the HALT or IDLE modes the user program must select the Wake Up source to be on the RDX pin This selection is done by setting bit 3 of WKEN (Wake Up Enable) register The Wake Up trigger condition is then selected to be high to low transition This is done via the WKEDG register (Bit 3 is one ) If the device is halted and crystal oscillator is used the Wake Up signal will not start the chip running immediately because of the finite start up time requirement of the crystal oscillator The idle timer (T0) generates a fixed (256 tc) delay to ensure that the oscillator has indeed stabilized before allowing the device to execute code The user has to consider this delay when data transfer is expected immediately after exiting the HALT mode Comparators The devices contain two differential comparators each with a pair of inputs (positive and negative) and an output Ports I1 – I3 and I4 – I6 are used for the comparators The following is the Port I assignment I1 Comparator1 negative input I2 Comparator1 positive input I3 Comparator1 output I4 Comparator2 negative input I5 Comparator2 positive input I6 Comparator2 output A Comparator Select Register (CMPSL) is used to enable the comparators read the outputs of the comparators internally and enable the outputs of the comparators to the pins Two control bits (enable and output enable) and one result bit are associated with each comparator The comparator result bits (CMP1RD and CMP2RD) are read only bits which will read as zero if the associated comparator is not enabled The Comparator Select Register is cleared with reset resulting in the comparators being disabled The comparators should also be disabled before entering either the HALT or IDLE modes in order to save power The configuration of the CMPSL register is as follows Diagnostic Bits CHARL0 and CHARL1 in the ENU register provide a loopback feature for diagnostic testing of the UART When these bits are set to one the following occur The receiver input pin (RDX) is internally connected to the transmitter output pin (TDX) the output of the Transmitter Shift Register is ‘‘looped back’’ into the Receive Shift Register input In this mode data that is transmitted is immediately received This feature allows the processor to verify the transmit and receive data paths of the UART 21 http www national com Comparators (Continued) CMPSL REGISTER (ADDRESS X’00B7) The CMPSL register contains the following bits CMP1EN Enable comparator 1 CMP1RD Comparator 1 result (this is a read only bit which will read as 0 if the comparator is not enabled) CMP10E Selects pin I3 as comparator 1 output provided that CMPIEN is set to enable the comparator CMP2EN Enable comparator 2 CMP2RD Comparator 2 result (this is a read only bit which will read as 0 if the comparator is not enabled) CMP20E Selects pin I6 as comparator 2 output provided that CMP2EN is set to enable the comparator Unused CMP20E CMP2RD CMP2EN CMP10E CMP1RD CMP1EN Unused Bit 7 Bit 0 Interrupts The devices support a vectored interrupt scheme It supports a total of fourteen interrupt sources The following table lists all the possible device interrupt sources their arbitration ranking and the memory locations reserved for the interrupt vector for each source Two bytes of program memory space are reserved for each interrupt source All interrupt sources except the software interrupt are maskable Each of the maskable interrupts have an Enable bit and a Pending bit A maskable interrupt is active if its associated enable and pending bits are set If GIE e 1 and an interrupt is active then the processor will be interrupted as soon as it is ready to start executing an instruction except if the above conditions happen during the Software Trap service routine This exception is described in the Software Trap sub-section The interruption process is accomplished with the INTR instruction (opcode 00) which is jammed inside the Instruction Register and replaces the opcode about to be executed The following steps are performed for every interrupt 1 The GIE (Global Interrupt Enable) bit is reset 2 The address of the instruction about to be executed is pushed into the stack 3 The PC (Program Counter) branches to address 00FF This procedure takes 7 tc cycles to execute Vector Address Hi-Low Byte 0yFE – 0yFF 0yFC – 0yFD 0yFA – 0yFB 0yF8 – 0yF9 0yF6 – 0yF7 0yF4 – 0yF5 0yF2 – 0yF3 0yF0 – 0yF1 0yEE – 0yEF 0yEC – 0yED 0yEA – 0yEB 0yE8 – 0yE9 0yE6 – 0yE7 0yE4 – 0yE5 0yE2 – 0yE3 0yE0 – 0yE1 Note that the two unused bits of CMPSL may be used as software flags Comparator outputs have the same spec as Ports L and G except that the rise and fall times are symmetrical Arbitration Ranking (1) Highest (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) Lowest y is VIS page y i Source Software Reserved External Timer T0 Timer T1 Timer T1 MICROWIRE PLUS Reserved UART UART Timer T2 Timer T2 Timer T3 Timer T3 Port L Wake Up Default 0 Description INTR Instruction for Future Use Pin G0 Edge Underflow T1A Underflow T1B BUSY Goes Low for Future Use Receive Transmit T2A Underflow T2B T3A Underflow T3B Port L Edge VIS Instr Execution without Any Interrupts http www national com 22 Interrupts (Continued) At this time since GIE e 0 other maskable interrupts are disabled The user is now free to do whatever context switching is required by saving the context of the machine in the stack with PUSH instructions The user would then program a VIS (Vector Interrupt Select) instruction in order to branch to the interrupt service routine of the highest priority interrupt enabled and pending at the time of the VIS Note that this is not necessarily the interrupt that caused the branch to address location 00FF Hex prior to the context switching Thus if an interrupt with a higher rank than the one which caused the interruption becomes active before the decision of which interrupt to service is made by the VIS then the interrupt with the higher rank will override any lower ones and will be acknowledged The lower priority interrupt(s) are still pending however and will cause another interrupt immediately following the completion of the interrupt service routine associated with the higher priority interrupt just serviced This lower priority interrupt will occur immediately following the RETI (Return from Interrupt) instruction at the end of the interrupt service routine just completed Inside the interrupt service routine the associated pending bit has to be cleared by software The RETI (Return from Interrupt) instruction at the end of the interrupt service routine will set the GIE (Global Interrupt Enable) bit allowing the processor to be interrupted again if another interrupt is active and pending The VIS instruction looks at all the active interrupts at the time it is executed and performs an indirect jump to the beginning of the service routine of the one with the highest rank The addresses of the different interrupt service routines called vectors are chosen by the user and stored in ROM in a table starting at 01E0 (assuming that VIS is located between 00FF and 01DF) The vectors are 15-bit wide and therefore occupy 2 ROM locations VIS and the vector table must be located in the same 256-byte block (0y00 to 0yFF) except if VIS is located at the last address of a block In this case the table must be in the next block The vector table cannot be inserted in the first 256-byte block (y i 0) The vector of the maskable interrupt with the lowest rank is located at 0yE0 (Hi-Order byte) and 0yE1 (Lo-Order byte) and so forth in increasing rank number The vector of the maskable interrupt with the highest rank is located at 0yFA (Hi-Order byte) and 0yFB (Lo-Order byte) The Software Trap has the highest rank and its vector is located at 0yFE and 0yFF If by accident a VIS gets executed and no interrupt is active then the PC (Program Counter) will branch to a vector located at 0yE0 – 0yE1 WARNING A Default VIS interrupt handler routine must be present As a minimum this handler should confirm that the GIE bit is cleared (this indicates that the interrupt sequence has been taken) take care of any required housekeeping restore context and return Some sort of Warm Restart procedure should be implemented These events can occur without any error on the part of the system designer or programmer Note There is always the possibility of an interrupt occurring during an instruction which is attempting to reset the GIE bit or any other interrupt enable bit If this occurs when a single cycle instruction is being used to reset the interrupt enable bit the interrupt enable bit will be reset but an interrupt may still occur This is because interrupt processing is started at the same time as the interrupt bit is being reset To avoid this scenario the user should always use a two three or four cycle instruction to reset interrupt enable bits Figure 16 shows the Interrupt block diagram SOFTWARE TRAP The Software Trap (ST) is a special kind of non-maskable interrupt which occurs when the INTR instruction (used to acknowledge interrupts) is fetched from ROM and placed inside the instruction register This may happen when the PC is pointing beyond the available ROM address space or when the stack is over-popped TL DD12860 – 18 FIGURE 16 Interrupt Block Diagram 23 http www national com Interrupts (Continued) When an ST occurs the user can re-initialize the stack pointer and do a recovery procedure (similar to reset but not necessarily containing all of the same initialization procedures) before restarting The occurrence of an ST is latched into the ST pending bit The GIE bit is not affected and the ST pending bit (not accessible by the user) is used to inhibit other interrupts and to direct the program to the ST service routine with the VIS instruction The RPND instruction is used to clear the software interrupt pending bit This pending bit is also cleared on reset The ST has the highest rank among all interrupts Nothing (except another ST) can interrupt an ST being serviced TABLE VI WATCHDOG Service Window Select WDSVR Bit 7 0 0 1 1 WDSVR Bit 6 0 1 0 1 Service Window (Lower-Upper Limits) 2k –8k tc Cycles 2k – 16k tc Cycles 2k – 32k tc Cycles 2k – 64k tc Cycles Clock Monitor The Clock Monitor aboard the device can be selected or deselected under program control The Clock Monitor is guaranteed not to reject the clock if the instruction cycle clock (1 tc) is greater or equal to 10 kHz This equates to a clock input rate on CKI of greater or equal to 100 kHz WATCHDOG The devices contain a WATCHDOG and clock monitor The WATCHDOG is designed to detect the user program getting stuck in infinite loops resulting in loss of program control or ‘‘runaway’’ programs The Clock Monitor is used to detect the absence of a clock or a very slow clock below a specified rate on the CKI pin The WATCHDOG consists of two independent logic blocks WD UPPER and WD LOWER WD UPPER establishes the upper limit on the service window and WD LOWER defines the lower limit of the service window Servicing the WATCHDOG consists of writing a specific value to a WATCHDOG Service Register named WDSVR which is memory mapped in the RAM This value is composed of three fields consisting of a 2-bit Window Select a 5-bit Key Data field and the 1-bit Clock Monitor Select field Table V shows the WDSVR register The lower limit of the service window is fixed at 2048 instruction cycles Bits 7 and 6 of the WDSVR register allow the user to pick an upper limit of the service window Table VI shows the four possible combinations of lower and upper limits for the WATCHDOG service window This flexibility in choosing the WATCHDOG service window prevents any undue burden on the user software Bits 5 4 3 2 and 1 of the WDSVR register represent the 5bit Key Data field The key data is fixed at 01100 Bit 0 of the WDSVR Register is the Clock Monitor Select bit TABLE V WATCHDOG Service Register (WDSVR) Window Select X 7 X 6 0 5 1 4 Key Data 1 3 0 2 0 1 Clock Monitor Y 0 WATCHDOG Operation The WATCHDOG and Clock Monitor are disabled during reset The device comes out of reset with the WATCHDOG armed the WATCHDOG Window Select bits (bits 6 7 of the WDSVR Register) set and the Clock Monitor bit (bit 0 of the WDSVR Register) enabled Thus a Clock Monitor error will occur after coming out of reset if the instruction cycle clock frequency has not reached a minimum specified value including the case where the oscillator fails to start The WDSVR register can be written to only once after reset and the key data (bits 5 through 1 of the WDSVR Register) must match to be a valid write This write to the WDSVR register involves two irrevocable choices (i) the selection of the WATCHDOG service window (ii) enabling or disabling of the Clock Monitor Hence the first write to WDSVR Register involves selecting or deselecting the Clock Monitor select the WATCHDOG service window and match the WATCHDOG key data Subsequent writes to the WDSVR register will compare the value being written by the user to the WATCHDOG service window value and the key data (bits 7 through 1) in the WDSVR Register Table VII shows the sequence of events that can occur The user must service the WATCHDOG at least once before the upper limit of the service window expires The WATCHDOG may not be serviced more than once in every lower limit of the service window The user may service the WATCHDOG as many times as wished in the time period between the lower and upper limits of the service window The first write to the WDSVR Register is also counted as a WATCHDOG service The WATCHDOG has an output pin associated with it This is the WDOUT pin on pin 1 of the port G WDOUT is active low The WDOUT pin is in the high impedance state in the inactive state Upon triggering the WATCHDOG the logic will pull the WDOUT (G1) pin low for an additional 16 tc –32 tc cycles after the signal level on WDOUT pin goes below the lower Schmitt trigger threshold After this delay the device will stop forcing the WDOUT output low TABLE VII WATCHDOG Service Actions Key Data Match Don’t Care Mismatch Don’t Care Window Data Match Mismatch Don’t Care Don’t Care Clock Monitor Match Don’t Care Don’t Care Mismatch Action Valid Service Restart Service Window Error Generate WATCHDOG Output Error Generate WATCHDOG Output Error Generate WATCHDOG Output http www national com 24 WATCHDOG Operation (Continued) The WATCHDOG service window will restart when the WDOUT pin goes high It is recommended that the user tie the WDOUT pin back to VCC through a resistor in order to pull WDOUT high A WATCHDOG service while the WDOUT signal is active will be ignored The state of the WDOUT pin is not guaranteed on reset but if it powers up low then the WATCHDOG will time out and WDOUT will enter high impedance state The Clock Monitor forces the G1 pin low upon detecting a clock frequency error The Clock Monitor error will continue until the clock frequency has reached the minimum specified value after which the G1 output will enter the high impedance TRI-STATE mode following 16 tc – 32 tc clock cycles The Clock Monitor generates a continual Clock Monitor error if the oscillator fails to start or fails to reach the minimum specified frequency The specification for the Clock Monitor is as follows 1 tc l 10 kHz No clock rejection 1 tc k 10 Hz Guaranteed clock rejection WATCHDOG AND CLOCK MONITOR SUMMARY The following salient points regarding the WATCHDOG and CLOCK MONITOR should be noted  The WATCHDOG detector circuit is inhibited during both the HALT and IDLE modes  The CLOCK MONITOR detector circuit is active during both the HALT and IDLE modes Consequently the COP888 inadvertently entering the HALT mode will be detected as a CLOCK MONITOR error (provided that the CLOCK MONITOR enable option has been selected by the program)  With the single-pin R C oscillator mask option selected and the CLKDLY bit reset the WATCHDOG service window will resume following HALT mode from where it left off before entering the HALT mode  With the crystal oscillator mask option selected or with the single-pin R C oscillator mask option selected and the CLKDLY bit set the WATCHDOG service window will be set to its selected value from WDSVR following HALT Consequently the WATCHDOG should not be serviced for at least 2048 instruction cycles following HALT but must be serviced within the selected window to avoid a WATCHDOG error  The IDLE timer T0 is not initialized with RESET  The user can sync in to the IDLE counter cycle with an IDLE counter (T0) interrupt or by monitoring the T0PND flag The T0PND flag is set whenever the thirteenth bit of the IDLE counter toggles (every 4096 instruction cycles) The user is responsible for resetting the T0PND flag  Both the WATCHDOG and CLOCK MONITOR detector circuits are inhibited during RESET  Following RESET the WATCHDOG and CLOCK MONITOR are both enabled with the WATCHDOG having the maximum service window selected  A hardware WATCHDOG service occurs just as the device exits the IDLE mode Consequently the WATCHDOG should not be serviced for at least 2048 instruction cycles following IDLE but must be serviced within the selected window to avoid a WATCHDOG error  The WATCHDOG service window and CLOCK MONITOR enable disable option can only be changed once during the initial WATCHDOG service following RESET  The initial WATCHDOG service must match the key data value in the WATCHDOG Service register WDSVR in order to avoid a WATCHDOG error  Following RESET the initial WATCHDOG service (where the service window and the CLOCK MONITOR enable disable must be selected) may be programmed anywhere within the maximum service window (65 536 instruction cycles) initialized by RESET Note that this initial WATCHDOG service may be programmed within the initial 2048 instruction cycles without causing a WATCHDOG error  Subsequent WATCHDOG services must match all three data fields in WDSVR in order to avoid WATCHDOG errors  The correct key data value cannot be read from the WATCHDOG Service register WDSVR Any attempt to read this key data value of 01100 from WDSVR will read as key data value of all 0’s 25 http www national com Detection of Illegal Conditions The device can detect various illegal conditions resulting from coding errors transient noise power supply voltage drops runaway programs etc Reading of undefined ROM gets zeros The opcode for software interrupt is zero If the program fetches instructions from undefined ROM this will force a software interrupt thus signaling that an illegal condition has occurred The subroutine stack grows down for each call (jump to subroutine) interrupt or PUSH and grows up for each return or POP The stack pointer is initialized to RAM location 06F Hex during reset Consequently if there are more returns than calls the stack pointer will point to addresses 070 and 071 Hex (which are undefined RAM) Undefined RAM from addresses 070 to 07F (Segment 0) 140 to 17F (Segment 1) and all other segments (i e Segments 3 etc ) is read as all 1’s which in turn will cause the program to return to address 7FFF Hex This is an undefined ROM location and the instruction fetched (all 0’s) from this location will generate a software interrupt signaling an illegal condition Thus the chip can detect the following illegal conditions 1 Executing from undefined ROM 2 Over ‘‘POP’’ing the stack by having more returns than calls When the software interrupt occurs the user can re-initialize the stack pointer and do a recovery procedure before restarting (this recovery program is probably similar to that following reset but might not contain the same program initialization procedures) The recovery program should reset the software interrupt pending bit using the RPND instruction MICROWIRE PLUS MICROWIRE PLUS is a serial synchronous communications interface The MICROWIRE PLUS capability enables the device to interface with any of National Semiconductor’s MICROWIRE peripherals (i e A D converters display drivers E2PROMs etc ) and with other microcontrollers which support the MICROWIRE interface It consists of an 8-bit serial shift register (SIO) with serial data input (SI) serial data output (SO) and serial shift clock (SK) Figure 17 shows a block diagram of the MICROWIRE PLUS logic TL DD12860 – 19 FIGURE 17 MICROWIRE PLUS Block Diagram The shift clock can be selected from either an internal source or an external source Operating the MICROWIRE PLUS arrangement with the internal clock source is called the Master mode of operation Similarly operating the MICROWIRE PLUS arrangement with an external shift clock is called the Slave mode of operation The CNTRL register is used to configure and control the MICROWIRE PLUS mode To use the MICROWIRE PLUS the MSEL bit in the CNTRL register is set to one In the master mode the SK clock rate is selected by the two bits SL0 and SL1 in the CNTRL register Table VIII details the different clock rates that may be selected TABLE VIII MICROWIRE PLUS Master Mode Clock Select SL1 0 0 1 SL0 0 1 x SK 2 c tc 4 c tc 8 c tc Where tc is the instruction cycle clock http www national com 26 MICROWIRE PLUS (Continued) MICROWIRE PLUS OPERATION Setting the BUSY bit in the PSW register causes the MICROWIRE PLUS to start shifting the data It gets reset when eight data bits have been shifted The user may reset the BUSY bit by software to allow less than 8 bits to shift If enabled an interrupt is generated when eight data bits have been shifted The device may enter the MICROWIRE PLUS mode either as a Master or as a Slave Figure 18 shows how two devices microcontrollers and several peripherals may be interconnected using the MICROWIRE PLUS arrangements Warning The SIO register should only be loaded when the SK clock is low Loading the SIO register while the SK clock is high will result in undefined data in the SIO register SK clock is normally low when not shifting Setting the BUSY flag when the input SK clock is high in the MICROWIRE PLUS slave mode may cause the current SK clock for the SIO shift register to be narrow For safety the BUSY flag should only be set when the input SK clock is low MICROWIRE PLUS Master Mode Operation In the MICROWIRE PLUS Master mode of operation the shift clock (SK) is generated internally by the device The MICROWIRE Master always initiates all data exchanges The MSEL bit in the CNTRL register must be set to enable the SO and SK functions onto the G Port The SO and SK pins must also be selected as outputs by setting appropriate bits in the Port G configuration register Table IX summarizes the bit settings required for Master mode of operation MICROWIRE PLUS Slave Mode Operation In the MICROWIRE PLUS Slave mode of operation the SK clock is generated by an external source Setting the MSEL bit in the CNTRL register enables the SO and SK functions onto the G Port The SK pin must be selected as an input and the SO pin is selected as an output pin by setting and resetting the appropriate bit in the Port G configuration register Table IX summarizes the settings required to enter the Slave mode of operation The user must set the BUSY flag immediately upon entering the Slave mode This will ensure that all data bits sent by the Master will be shifted properly After eight clock pulses the BUSY flag will be cleared and the sequence may be repeated Alternate SK Phase Operation The device allows either the normal SK clock or an alternate phase SK clock to shift data in and out of the SIO register In both the modes the SK is normally low In the normal mode data is shifted in on the rising edge of the SK clock and the data is shifted out on the falling edge of the SK clock The SIO register is shifted on each falling edge of the SK clock In the alternate SK phase operation data is shifted in on the falling edge of the SK clock and shifted out on the rising edge of the SK clock A control flag SKSEL allows either the normal SK clock or the alternate SK clock to be selected Resetting SKSEL causes the MICROWIRE PLUS logic to be clocked from the normal SK signal Setting the SKSEL flag selects the alternate SK clock The SKSEL is mapped into the G6 configuration bit The SKSEL flag will power up in the reset condition selecting the normal SK signal TABLE IX MICROWIRE PLUS Mode Selection G4 (SO) G5 (SK) Config Bit Config Bit 1 0 1 0 1 1 0 0 G4 Fun SO G5 Fun Operation Int MICROWIRE PLUS SK Master TRI- Int MICROWIRE PLUS STATE SK Master SO Ext MICROWIRE PLUS SK Slave TRI- Ext MICROWIRE PLUS STATE SK Slave Note This table assumes that the control flag MSEL is set TL DD12860 – 20 FIGURE 18 MICROWIRE PLUS Application 27 http www national com Memory Map All RAM ports and registers (except A and PC) are mapped into data memory address space Address S ADD REG 0000 to 006F 0070 to 007F xx80 to xxAF xxB0 xxB1 xxB2 xxB3 xxB4 xxB5 xxB6 xxB7 xxB8 xxB9 xxBA xxBB xxBC xxBD xxBE xxBF xxC0 xxC1 xxC2 xxC3 xxC4 xxC5 xxC6 xxC7 xxC8 xxC9 xxCA xxCB xxCC xxCD to xxCF Contents On-Chip RAM bytes (112 bytes) Unused RAM Address Space (Reads As All Ones) Unused RAM Address Space (Reads Undefined Data) Timer T3 Lower Byte Timer T3 Upper Byte Timer T3 Autoload Register T3RA Lower Byte Timer T3 Autoload Register T3RA Upper Byte Timer T3 Autoload Register T3RB Lower Byte Timer T3 Autoload Register T3RB Upper Byte Timer T3 Control Register Comparator Select Register (CMPSL) UART Transmit Buffer (TBUF) UART Receive Buffer (RBUF) UART Control and Status Register (ENU) UART Receive Control and Status Register (ENUR) UART Interrupt and Clock Source Register (ENUI) UART Baud Register (BAUD) UART Prescale Select Register (PSR) Reserved for UART Timer T2 Lower Byte Timer T2 Upper Byte Timer T2 Autoload Register T2RA Lower Byte Timer T2 Autoload Register T2RA Upper Byte Timer T2 Autoload Register T2RB Lower Byte Timer T2 Autoload Register T2RB Upper Byte Timer T2 Control Register WATCHDOG Service Register (Reg WDSVR) MIWU Edge Select Register (Reg WKEDG) MIWU Enable Register (Reg WKEN) MIWU Pending Register (Reg WKPND) Reserved Reserved Reserved Address S ADD REG xxD0 xxD1 xxD2 xxD3 xxD4 xxD5 xxD6 xxD7 xxD8 xxD9 xxDA xxDB xxDC xxDD to DF xxE0 to xxE5 xxE6 xxE7 xxE8 xxE9 xxEA xxEB xxEC xxED xxEE xxEF xxF0 to FB xxFC xxFD xxFE xxFF 0100 – 017F 0200 – 027F 0200 – 037F Contents Port L Data Register Port L Configuration Register Port L Input Pins (Read Only) Reserved for Port L Port G Data Register Port G Configuration Register Port G Input Pins (Read Only) Port I Input Pins (Read Only) Port C Data Register Port C Configuration Register Port C Input Pins (Read Only) Reserved for Port C Port D Reserved for Port D Reserved for EE Control Registers Timer T1 Autoload Register T1RB Lower Byte Timer T1 Autoload Register T1RB Upper Byte ICNTRL Register MICROWIRE PLUS Shift Register Timer T1 Lower Byte Timer T1 Upper Byte Timer T1 Autoload Register T1RA Lower Byte Timer T1 Autoload Register T1RA Upper Byte CNTRL Control Register PSW Register On-Chip RAM Mapped as Registers X Register SP Register B Register S Register On-Chip 128 RAM Bytes On-Chip 128 RAM Bytes On-Chip 128 RAM Bytes Note Reading memory locations 0070H–007FH (Segment 0) will return all ones Reading unused memory locations 0080H–00AFH (Segment 0) will return undefined data Reading memory locations from other Segments (i e Segment 4 Segment 5 etc ) will return all ones http www national com 28 Addressing Modes There are ten addressing modes six for operand addressing and four for transfer of control OPERAND ADDRESSING MODES Register Indirect This is the ‘‘normal’’ addressing mode The operand is the data memory addressed by the B pointer or X pointer Register Indirect (with auto post increment or decrement of pointer) This addressing mode is used with the LD and X instructions The operand is the data memory addressed by the B pointer or X pointer This is a register indirect mode that automatically post increments or decrements the B or X register after executing the instruction Direct The instruction contains an 8-bit address field that directly points to the data memory for the operand Immediate The instruction contains an 8-bit immediate field as the operand Short Immediate This addressing mode is used with the Load B Immediate instruction The instruction contains a 4-bit immediate field as the operand Indirect This addressing mode is used with the LAID instruction The contents of the accumulator are used as a partial address (lower 8 bits of PC) for accessing a data operand from the program memory TRANSFER OF CONTROL ADDRESSING MODES Relative This mode is used for the JP instruction with the instruction field being added to the program counter to get the new program location JP has a range from b31 to a 32 to allow a 1-byte relative jump (JP a 1 is implemented by a NOP instruction) There are no ‘‘pages’’ when using JP since all 15 bits of PC are used Absolute This mode is used with the JMP and JSR instructions with the instruction field of 12 bits replacing the lower 12 bits of the program counter (PC) This allows jumping to any location in the current 4k program memory segment Absolute Long This mode is used with the JMPL and JSRL instructions with the instruction field of 15 bits replacing the entire 15 bits of the program counter (PC) This allows jumping to any location up to 32k in the program memory space Symbols B X MD Mem Meml Imm Reg Bit Memory Indirectly Addressed by B Register Memory Indirectly Addressed by X Register Direct Addressed Memory Direct Addressed Memory or B Direct Addressed Memory or B or Immediate Data 8-Bit Immediate Data Register Memory Addresses F0 to FF (Includes B X and SP) Bit Number (0 to 7) Loaded with Exchanged with Indirect This mode is used with the JID instruction The contents of the accumulator are used as a partial address (lower 8 bits of PC) for accessing a location in the program memory The contents of this program memory location serve as a partial address (lower 8 bits of PC) for the jump to the next instruction Note The VIS is a special case of the Indirect Transfer of Control addressing mode where the double byte vector associated with the interrupt is transferred from adjacent addresses in the program memory into the program counter (PC) in order to jump to the associated interrupt service routine Instruction Set Register and Symbol Definition Registers A B X SP PC PU PL C HC GIE VU VL 8-Bit Accumulator Register 8-Bit Address Register 8-Bit Address Register 8-Bit Stack Pointer Register 15-Bit Program Counter Register Upper 7 Bits of PC Lower 8 Bits of PC 1 Bit of PSW Register for Carry 1 Bit of PSW Register for Half Carry 1 Bit of PSW Register for Global Interrupt Enable Interrupt Vector Upper Byte Interrupt Vector Lower Byte w 29 http www national com Instruction Set (Continued) INSTRUCTION SET ADD ADC SUBC AND ANDSZ OR XOR IFEQ IFEQ IFNE IFGT IFBNE DRSZ SBIT RBIT IFBIT RPND X X LD LD LD LD LD X X LD LD LD CLR INC DEC LAID DCOR RRC RLC SWAP SC RC IFC IFNC POP PUSH VIS JMPL JMP JP JSRL JSR JID RET RETSK RETI INTR NOP A Meml A Meml A Meml A Meml A Imm A Meml A Meml MD Imm A Meml A Meml A Meml Reg Mem Mem Mem A Mem AX A Meml AX B Imm Mem Imm Reg Imm A Bg A Xg A Bg A Xg B g Imm A A A A A A A ADD ADD with Carry Subtract with Carry Logical AND Logical AND Immed Skip if Zero Logical OR Logical EXclusive OR IF EQual IF EQual IF Not Equal IF Greater Than If B Not Equal Decrement Reg Skip if Zero Set BIT Reset BIT IF BIT Reset PeNDing Flag EXchange A with Memory EXchange A with Memory X LoaD A with Memory LoaD A with Memory X LoaD B with Immed LoaD Memory Immed LoaD Register Memory Immed EXchange A with Memory B EXchange A with Memory X LoaD A with Memory B LoaD A with Memory X LoaD Memory B Immed CLeaR A INCrement A DECrementA Load A InDirect from ROM Decimal CORrect A Rotate A Right thru C Rotate A Left thru C SWAP nibbles of A Set C Reset C IF C IF Not C POP the stack into A PUSH A onto the stack Vector to Interrupt Service Routine Jump absolute Long Jump absolute Jump relative short Jump SubRoutine Long Jump SubRoutine Jump InDirect RETurn from subroutine RETurn and SKip RETurn from Interrupt Generate an Interrupt No OPeration A w A a Meml A w A a Meml a C C w Carry HC w Half Carry A w A b MemI a C C w Carry HC w Half Carry A w A and Meml Skip next if (A and Imm) e 0 A w A or Meml A w A xor Meml Compare MD and Imm Do next if MD e Imm Compare A and Meml Do next if A e Meml Compare A and Meml Do next if A i Meml Compare A and Meml Do next if A l Meml Do next if lower 4 bits of B i Imm Reg w Reg b 1 Skip if Reg e 0 1 to bit Mem (bit e 0 to 7 immediate) 0 to bit Mem If bit in A or Mem is true do next instruction Reset Software Interrupt Pending Flag A Mem A X A w Meml Aw X B w Imm Mem w Imm Reg w Imm A B (B w B g 1) A X (X w g 1) A w B (B w B g 1) A w X (X w X g 1) B w Imm (B w B g 1) Aw0 AwA a 1 AwA b 1 A w ROM (PU A) A w BCD correction of A (follows ADC SUBC) C x A7 x x A0 x C C w A7 w w A0 w C A7 A4 A3 A0 C w 1 HC w 1 C w 0 HC w 0 IF C is true do next instruction If C is not true do next instruction SP w SP a 1 A w SP SP w A SP w SP b 1 PU w VU PL w VL PC w ii (ii e 15 bits 0k to 32k) PC9 0 w i (i e 12 bits) PC w PC a r (r is b31 to a 32 except 1) SP w PL SPb1 w PU SPb2 PC w ii SP w PL SPb1 w PU SPb2 PC9 0wi PL w ROM (PU A) SP a 2 PL w SP PU w SPb1 SP a 2 PL w SP PU w SPb1 SP a 2 PL w SP PU w SPb1 GIE w 1 SP w PL SPb1 w PU SPb2 PC w 0FF PC w PC a 1 A A Addr Addr Disp Addr Add http www national com 30 Instruction Execution Time Most instructions are single byte (with immediate addressing mode instructions taking two bytes) Most single byte instructions take one cycle time to execute Skipped instructions require x number of cycles to be skipped where x equals the number of bytes in the skipped instruction opcode See the BYTES and CYCLES per INSTRUCTION table for details Bytes and Cycles per Instruction The following table shows the number of bytes and cycles for each instruction in the format of byte cycle Logic and Arithmetic Instructions B ADD ADC SUBC AND OR XOR IFEQ IFGT IFBNE DRSZ SBIT RBIT IFBIT RPND 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Direct 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 Immed 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Instructions Using A and C CLRA INCA DECA LAID DCORA RRCA RLCA SWAPA SC RC IFC IFNC PUSHA POPA ANDSZ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 3 1 1 1 1 1 1 1 1 3 3 2 Transfer of Control Instructions JMPL JMP JP JSRL JSR JID VIS RET RETSK RETI INTR NOP 3 2 1 3 2 1 1 1 1 1 1 1 4 3 3 5 5 3 5 5 5 5 7 1 13 11 11 11 11 34 34 34 Memory Transfer Instructions Register Indirect B XA LD A LD B Imm LD B Imm LD Mem Imm LD Reg Imm IFEQ MD Imm 11 11 X 13 13 23 23 22 11 23 Register Indirect Auto Incr and Decr B a Bb 12 12 X a Xb 13 13 (IF B k 16) (IF B l 15) 22 Direct Immed 22 22 33 23 33 e l Memory location addressed by B or X or directly 31 http www national com http Opcode Table UPPER NIBBLE E i i i i i i i i i i i i i i i i DRSZ 0FF LD B i RETI DRSZ 0FE LD A X LD A B LD B i RET DRSZ 0FD DIR JSRL LD A Md RETSK DRSZ 0FC LD Md i JMPL X A Md POPA SBIT RBIT 4B 4B SBIT RBIT 5B 5B SBIT RBIT 6B 6B SBIT RBIT 7B 7B DRSZ 0FB LD A Xb LD A Bb LD Bb i DECA SBIT RBIT 3B 3B DRSZ 0FA LD A Xa LD A Ba LD B a i INCA SBIT RBIT 2B 2B LD B LD B LD B LD B LD B LD B DRSZ 0F9 IFNE AB IFEQ Md i IFNE Ai IFNC SBIT RBIT 1B 1B LD B DRSZ 0F8 NOP RLCA LD A i IFC SBIT RBIT 0B 0B LD B 07 IFBNE 8 06 IFBNE 9 DRSZ 0F7 OR A i OR A B IFBIT PUSHA LD B 7B 08 IFBNE 7 DRSZ 0F6 X A X XA B XOR A i XOR A B IFBIT DCORA LD B 6B 09 IFBNE 6 JSR x600 –x6FF JSR x700 –x7FF JSR x800 –x8FF JSR x900 –x9FF DRSZ 0F5 RPND JID AND A i AND A B IFBIT SWAPA LD B 5B 0A IFBNE 5 JSR x500 –x5FF DRSZ 0F4 VIS LAID ADD A i ADD A B IFBIT CLRA 4B LD B 0B IFBNE 4 JSR x400 –x4FF DRSZ 0F3 X A Xb XA Bb IFGT A i IFGT A B IFBIT 3B LD B 0C IFBNE 3 JSR x300 –x3FF JMP x300 –x3FF JMP x400 –x4FF JMP x500 –x5FF JMP x600 –x6FF JMP x700 –x7FF JMP x800 –x8FF JMP x900 –x9FF DRSZ 0F2 X A Xa XA Ba IFEQ A i IFEQ A B IFBIT 2B LD B 0D IFBNE 2 JSR x200 –x2FF JMP x200 –x2FF DRSZ 0F1 SC SUBC A i SUB A B IFBIT 1B LD B 0E IFBNE 1 JSR x100 –x1FF JMP x100 –x1FF DRSZ 0F0 RRCA RC ADC A i ADC A B IFBIT ANDSZ LD B 0B A i 0F IFBNE 0 JSR x000 –x0FF JMP x000 –x0FF JP a 17 INTR JP a 18 JP a 2 JP a 19 JP a 3 JP a 20 JP a 4 JP a 21 JP a 5 JP a 22 JP a 6 JP a 23 JP a 7 JP a 24 JP a 8 JP a 25 JP a 9 D C B A 9 8 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 8 JP a 26 JP a 10 9 05 IFBNE 0A JSR JMP JP a 27 JP a 11 A xA00 –xAFF xA00 –xAFF 04 IFBNE 0B JSR JMP JP a 28 JP a 12 B xB00 –xBFF xB00 –xBFF 03 IFBNE 0C JSR JMP JP a 29 JP a 13 C xC00 –xCFF xC00 –xCFF 02 IFBNE 0D JSR JMP JP a 30 JP a 14 D xD00 –xDFF xD00 –xDFF 01 IFBNE 0E JSR JMP JP a 31 JP a 15 E xE00 –xEFF xE00 –xEFF 00 IFBNE 0F JSR JMP JP a 32 JP a 16 F xF00 –xFFF xF00 –xFFF F www national com iA JP b15 JP b31 LD 0F0 JP b14 JP b30 LD 0F1 JP b13 JP b29 LD 0F2 JP b12 JP b28 LD 0F3 JP b11 JP b27 LD 0F4 JP b10 JP b26 LD 0F5 JP b9 JP b25 LD 0F6 JP b8 JP b24 LD 0F7 LOWER NIBBLE 32 JP b7 JP b23 LD 0F8 JP b6 JP b22 LD 0F9 JP b5 JP b21 LD 0FA JP b4 JP b20 LD 0FB JP b3 JP b19 LD 0FC JP b2 JP b18 LD 0FD JP b1 JP b17 LD 0FE JP b0 JP b16 LD 0FF where i is the immediate data Md is a directly addressed memory location is an unused opcode Note The opcode 60 Hex is also the opcode for IFBIT Development Support SUMMARY  A full 64k hardware configurable break trace on trace off control and pass count increment events  iceMASTERTM IM-COP8 400 Full feature in-circuit emulation for all COP8 products A full set of COP8 Basic and Feature Family device and package specific probes are available  Tool set integrated interactive symbolic debugger supports both assembler (COFF) and C Compiler ( COD) linked object formats  COP8 Debug Module Moderate cost in-circuit emulation and development programming unit  Real time performance profiling analysis selectable bucket definition  COP8 Evaluation and Programming Unit EPUCOP888GG low cost in-circuit simulation and development programming unit development Assembler Linker Librarian and Utility Software Development Tool Kit  Watch windows content updated automatically at each execution break  Instruction by instruction memory register changes displayed on source window when in single step operation  Assembler COP8-DEV-IBMA A DOS installable cross  Single base unit and debugger software reconfigurable to support the entire COP8 family only the probe personality needs to change Debugger software is processor customized and reconfigured from a master model file  C Compiler COP8C A DOS installable cross development Software Tool Kit  OTP EPROM Programmer Support Covering needs from engineering prototype pilot production to full production environments iceMASTER (IM) IN-CIRCUIT EMULATION The iceMASTER IM-COP8 400 is a full feature PC based in-circuit emulation tool developed and marketed by MetaLink Corporation to support the whole COP8 family of products National is a resale vendor for these products See Figure 19 for configuration The iceMASTER IM-COP8 400 with its device specific COP8 Probe provides a rich feature set for developing testing and maintaining product  Processor specific symbolic display of registers and bit level assignments configured from master model file  Halt Idle mode notification  On-line HELP customized to specific processor using master model file  Includes a copy of COP8-DEV-IBMA assembler and linker SDK IM Order Information Base Unit IM-COP8 400-1 IM-COP8 400-2 iceMASTER Probe MHW-888GG40DWPC MHW-888GG44PWPC 40 DIP 44 PLCC iceMASTER Base Unit 110V Power Supply iceMASTER Base Unit 220V Power Supply  Real-time in-circuit emulation full 2 4V–5 5V operation range full DC-10 MHz clock Chip options are programmable or jumper selectable  Direct connection to application board by package compatible socket or surface mount assembly  Full 32 kbytes of loadable programming space that overlays (replaces) the on-chip ROM or EPROM On-chip RAM and I O blocks are used directly or recreated on the probe as necessary  Full 4k frame synchronous trace memory Address instruction and 8 unspecified circuit connectable trace lines Display can be HLL source (e g C source) assembly or mixed TL DD 12860 – 21 FIGURE 19 COP8 iceMASTER Environment 33 http www national com Development Support (Continued) iceMASTER DEBUG MODULE (DM) The iceMASTER Debug Module is a PC based combination in-circuit emulation tool and COP8 based OTP EPROM programming tool developed and marketed by MetaLink Corporation to support the whole COP8 family of products National is a resale vendor for these products See Figure 20 for configuration The iceMASTER Debug Module is a moderate cost development tool It has the capability of in-circuit emulation for a specific COP8 microcontroller and in addition serves as a programming tool for COP8 OTP and EPROM product families Summary of features is as follows  Instruction by instruction memory register changes displayed when in single step operation  Debugger software is processor customized and reconfigured from a master model file  Processor specific symbolic display of registers and bit level assignments configured from master model file  Halt Idle mode notification  Programming menu supports full product line of programmable OTP and EPROM COP8 products Program data is taken directly from the overlay RAM  Programming of 44 PLCC and 68 PLCC parts requires external programming adapters  Real-time in-circuit emulation full operating voltage range operation full DC-10 MHz clock  All processor I O pins can be cabled to an application development board with package compatible cable to socket and surface mount assembly  Includes wallmount power supply  On-board VPP generator from 5V input or connection to external supply supported Rquires VPP level adjustment per the family programming specification (correct level is provided on an on-screen pop-down display)  Full 32 kbytes of loadable programming space that overlays (replaces) the on-chip ROM or EPROM On-chip RAM and I O blocks are used directly or recreated as necessary  On-line HELP customized to specific processor using master model file  Includes a copy of COP8-DEV-IBMA assembler and linker SDK DM Order Information Debug Module Unit COP8-DM 888GG Cable Adapters DM-COP8 40D DM-COP8 44P 40 DIP 44 PLCC  100 frames of synchronous trace memory The display can be HLL source (C source) assembly or mixed The most recent history prior to a break is available in the trace memory  Configured break points uses INTR instruction which is modestly intrusive  Software only supported features are selectable  Tool set integrated interactive symbolic debugger supports both assembler (COFF) and C Compiler ( COD) SDK linked object formats TL DD 12860 – 22 FIGURE 20 COP8-DM Environment http www national com 34 Development Support (Continued) iceMASTER EVALUATION PROGRAMMING UNIT (EPU) The iceMASTER EPU-COP888GG is a PC based in-circuit simulation tool to support the feature family COP8 products See Figure 21 for configuration The simulation capability is a very low cost means of evaluating the general COP8 architecture In addition the EPU has programming capability with added adapters for programming the whole COP8 product family of OTP and EPROM products The product includes the following features  Tool set integrated interactive symbolic debugger supports both assembler (COFF) and C Compiler ( COD) SDK linked object formats  Instruction by instruction memory register changes displayed when in single step operation  Processor specific symbolic display of registers and bit level assignments configured from master model file  Halt Idle mode notification Restart requires special handling  Programming menu supports full product line of programmable OTP and EPROM COP8 products Only a 40 ZIF socket is available on the EPU unit Adapters are available for other part package configurations  Non-real-time in-circuit simulation Program overlay memory is PC resident instructions are downloaded over RS-232 as executed Approximate performance is 20 kHz ages are not supported All processor I O pins are cabled to the application development environment  Integral wall mount power supply provides 5V and develops the required VPP to program parts  Includes a 40-pin DIP cable adapter Other target pack-  Includes a copy of COP8-DEV-IBMA assembler linker SDK EPU Order Information Evaluation Programming Unit EPU-COP888GG Evaluation Programming Unit with debugger and programmer control software with 40 ZIF programming socket  Full 32 kbytes of loadable programming space that overlays (replaces) the on-chip ROM or EPROM On-chip RAM and I O blocks are used directly or recreated as necessary  On-chip timer and WATCHDOG execution are not well synchronized to the instruction simulation  100 frames of synchronous trace memory The display can be HLL source (e g C source) assembly or mixed The most recent history prior to a break is available in the trace memory General Programming Adapters COP8-PGMA-DS44P 28 and 20 DIP and SOIC plus 44 PLCC adapter  Up to eight software configured break points uses INTR instruction which is modestly intrusive  Common look-feel debugger software across all MetaLink products only supported features are selectable TL DD 12860 – 23 FIGURE 21 EPU-COP8 Tool Environment 35 http www national com Development Support (Continued) COP8 ASSEMBLER LINKER SOFTWARE DEVELOPMENT TOOL KIT National Semiconductor offers a relocateable COP8 macro cross assembler linker librarian and utility software development tool kit Features are summarized as follows COP8 C COMPILER A C Compiler is developed and marketed by Byte Craft Limited The COP8C compiler is a fully integrated development tool specifically designed to support the compact embedded configuration of the COP8 family of products Features are summarized as follows  Basic and Feature Family instruction set by ‘‘device’’ type  ANSI C with some restrictions and extensions that optimize development for the COP8 embedded application Integrated utilities to generate ROM code file outputs DUMPCOFF utility This product is integrated as a part of MetaLink tools as a development kit fully supported by the MetaLink debugger It may be ordered separately or it is bundled with the MetaLink products at no additional cost Order Information Assembler SDK COP8-DEV-IBMA Assembler SDK on installable 3 5 PC DOS Floppy Disk Drive format Periodic upgrades and most recent version is available on National’s BBS and Internet        Nested macro capability Extensive set of assembler directives Supported on PC DOS platform Generates National standard COFF output files Integrated Linker and Librarian  BITS data type extension Register declaration with direct bit level definitions pragma  C language support for interrupt routines  Expert system rule based code generation and optimization  Performs consistency checks against the architectural definitions of the target COP8 device  Generates program memory code  Supports linking of compiled object or COP8 assembled object formats  Global optimization of linked code  Symbolic debug load format fully sourced level supported by the MetaLink debugger INDUSTRY WIDE OTP EPROM PROGRAMMING SUPPORT Programming support in addition to the MetaLink development tools is provided by a full range of independent approved vendors to meet the needs from the engineering laboratory to full production Approved List Manufacturer BP Microsystems Data I O North America (800) 225-2102 (713) 688-4600 Fax (713) 688-0920 (800) 426-1045 (206) 881-6444 Fax (206) 882-1043 (510) 623-8860 Europe a 49-8152-4183 a 49-8856-932616 a 44-0734-440011 Asia a 852-234-16611 a 852-2710-8121 Call North America a 886-2-764-0215 Fax a 886-2-756-6403 HI-LO Call Asia ICE Technology MetaLink (800) 624-8949 (919) 430-7915 (800) 638-2423 (602) 926-0797 Fax (602) 693-0681 (408) 263-6667 (916) 924-8037 Fax (916) 924-8065 a 44-1226-767404 Fax 0-1226-370-434 a 49-80 9156 96-0 Fax a 49-80 9123 86 a 41-1-9450300 a 852-737-1800 Systems General Needhams a 886-2-9173005 Fax a 886-2-911-1283 http www national com 36 Development Support (Continued) AVAILABLE LITERATURE For more information please see the COP8 Basic Family User’s Manual Literature Number 620895 COP8 Feature Family User’s Manual Literature Number 620897 and National’s Family of 8-bit Microcontrollers COP8 Selection Guide Literature Number 630009 DIAL-A-HELPER SERVICE Dial-A-Helper is a service provided by the Microcontroller Applications group The Dial-A-Helper is an Electronic Information System that may be accessed as a Bulletin Board System (BBS) via data modem as an FTP site on the Internet via standard FTP client application or as an FTP site on the Internet using a standard Internet browser such as Netscape or Mosaic The Dial-A-Helper system provides access to an automated information storage and retrieval system The system capabilities include a MESSAGE SECTION (electronic mail when accessed as a BBS) for communications to and from the Microcontroller Applications Group and a FILE SECTION which consists of several file areas where valuable application software and utilities could be found DIAL-A-HELPER BBS via Standard Modem Modem CANADA U S (800) NSC-MICRO (800) 672-6427 EUROPE ( a 49) 0-8141-351332 Baud 14 4k Set-Up Length 8-Bit Parity None Stop Bit 1 Operation 24 Hours 7 Days DIAL-A-HELPER via FTP ftp nscmicro nsc com user anonymous password username yourhost site domain AUSTRALIA INDIA DIAL-A-HELPER via WorldWide Web Browser ftp nscmicro nsc com National Semiconductor on the WorldWide Web See us on the WorldWide Web at http www natsemi com CUSTOMER RESPONSE CENTER Complete product information and technical support is available from National’s customer response centers CANADA U S Tel email EUROPE email Deutsch Tel English Tel Fran ais Tel Italiano Tel JAPAN S E ASIA Tel Beijing Tel Shanghai Tel (800)272-9959 support tevm2 nsc com europe support nsc com a 49 (0) 180-530 85 85 a 49 (0) 180-532 78 32 a 49 (0) 180-532 93 58 a 49 (0) 180-534 16 80 a 81-043-299-2309 ( a 86) 10-6856-8601 ( a 86) 21-6415-4092 Hong Kong Tel ( a 852) 2737-1600 Korea Tel Malaysia Tel Singapore Tel Taiwan Tel Tel Tel ( a 82) 2-3771-6909 ( a 60-4) 644-9061 ( a 65) 255-2226 a 886-2-521-3288 ( a 61) 3-9558-9999 ( a 91) 80-559-9467 37 http www national com http www national com 38 Physical Dimensions inches (millimeters) unless otherwise noted Molded Dual-In-Line Package (N) Order Number COP87L88RGN-XE NS Package Number N40A 39 http www national com COP87L88RG 8-Bit One-Time Programmable (OTP) Microcontroller with 32 Kbytes of Program Memory Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Plastic Leaded Chip Carrier (V) Order Number COP87L88RGV-XE NS Package Number V44A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1(800) 272-9959 Fax 1(800) 737-7018 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness http www national com National Semiconductor Europe Fax a49 (0) 180-530 85 86 Email europe support nsc com Deutsch Tel a49 (0) 180-530 85 85 English Tel a49 (0) 180-532 78 32 Fran ais Tel a49 (0) 180-532 93 58 Italiano Tel a49 (0) 180-534 16 80 National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel (852) 2737-1600 Fax (852) 2736-9960 National Semiconductor Japan Ltd Tel 81-043-299-2308 Fax 81-043-299-2408 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications