LM3450

LM3450 LED Driver with Active Power Factor Correction and Phase Dimming Decoder November 18, 2010 LM3450 LED Driver with Active Power Factor Correction and Phase Dimming Decoder General Description The LM3450 is a power factor controller (PFC) with separate phase dimming decoder. The PFC regulates an accurate output voltage while maintaining excellent power factor at the input. The phase dimming decoder interprets the phase angle and remaps it to a 500Hz PWM output. This combination of features is ideal for implementing a dimmable off-line LED driver for 10-100W loads. The phase dimming decoder has several unique features. A programmable mapping from input to output increases design flexibility, while a dynamic filter and variable sampling rate provide a fast, smooth response to dimmer movement. A dynamic hold circuit ensures that the phase dimmer angle is decoded properly while minimizing the extra power losses associated with holding current. Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Critical conduction mode PFC Over-voltage protection Feedback short circuit protection 70:1 PWM decoded from phase dimmer Analog dimming Programmable dimming range Digital angle and dimmer detection Dynamic holding current Smooth dimming transitions Low power operation Start-up pre-regulator bias Precision voltage reference Applications ■ Dimmable downlights, troffers, and lowbays ■ Indoor and outdoor area SSL ■ Power supply PFC Typical Application 30127401 © 2010 National Semiconductor Corporation 301274 www.national.com LM3450 Connection Diagram Top View 30127402 16-Lead TSSOP NS Package Number MTC16 Ordering Information Order Number LM3450 LM3450MTX Spec. NOPB NOPB Package Type TSSOP-16 TSSOP-16 NSC Package Drawing MTC16 MTC16 92 Units, Rail 2500 Units, Tape and Reel Supplied As www.national.com 2 LM3450 Pin Descriptions Pin 1 Name VREF Description 3V Reference Application Information Reference Output: Connect directly to VADJ or to resistor divider feeding VADJ and to necessary external circuits. Analog Dim and Phase Dimming Range Input: Connect directly to VREF to force standard 70% phase dimming range. Connect to resistor divider from VREF to extend usable range of some phase dimmers or for analog dimming. Connect to GND for low power mode. Ramp Comparator Input: Connect a series resistor from FLT1 capacitor and a capacitor to GND to establish second filter pole. Angle Decoder Output: Connect a series resistor to a capacitor to GND to establish first filter pole. Open Drain PWM Dim Output: Connect to dimming input of output stage LED driver (directly or with isolation) to provide decoded dimming command. Multiplier and Angle Decoder Input: Connect to resistor divider from rectified AC line. Error Amplifier Output and PWM Comparator Input: Connect a capacitor to GND to set the compensation. Error Amplifier Inverting Input: Connect to output voltage via resistor divider to control PFC voltage loop for non-isolated designs. Connect a 5.11kΩ resistor to GND for isolated designs (bypasses error amplifier). Also includes over-voltage protection and shutdown modes. Input Current Sense Non-Inverting Input: Connect to diode bridge return and resistor to GND to sense input current for dynamic hold. Connect a 0.1µF capacitor and Schottky diode to GND, and a 0.22µF capacitor to HOLD. System Ground MosFET Current Sense Input: Connect to positive terminal of sense resistor in PFC MosFET source. Gate Drive Output: Connect to gate of main power MosFET for PFC. Power Supply Input: Connect to primary bias supply. Connect a 0.1µF bypass capacitor to ground. Demagnetization Sense Input: Connect a 100kΩ resistor to transformer/inductor winding to detect when all energy has been transferred. Open Drain Dynamic Hold Input: Connect to holding resistor which is connected to source of passFET. Pre-regulator Gate Bias Output: Connect to gate of passFET and through resistor to rectified AC (drain of passFET) to aid with startup. 2 VADJ Analog Adjust 3 4 5 6 7 FLT2 FLT1 DIM VAC COMP Filter 2 Filter 1 500 Hz PWM Output Sampled Rectified Line Compensation 8 FB Feedback 9 10 11 12 13 14 15 16 ISEN GND CS GATE VCC ZCD HOLD BIAS Input Current Sense Power Ground Current Sense Gate Drive Input Supply Zero Crossing Detector Dynamic Hold Pre-regulator Gate Bias 3 www.national.com LM3450 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VCC, HOLD, DIM, BIAS HOLD Power BIAS Current ZCD Current COMP, FB, VAC, FLT1, FLT2, VREF, CS, VADJ ISEN GATE -0.3V to 25.0V 250 mW Continuous 5.0mA Continuous +/- 10mA -0.3V to 7.0V -7.0V to 7.0V -0.3V to 18V Continuous -2.5V for 100ns 20.5V for 100ns -1mA to +1mA Continuous Continuous Power Dissipation Maximum Junction Temperature Storage Temperature Range Maximum Lead Temperature (Solder and Reflow) (Note 2) ESD Susceptibility (Note 3) HBM MM FICDM Internally Limited Internally Limited -65°C to +150°C 260°C 2kV 200V 750V (Note 1) 8.5V to 20V -40°C to +125°C Operating Conditions VCC Range Junction Temperature Range (Note 1) Unless otherwise specified VCC = 14V. Specifications in standard type face are for TJ = 25°C and those with boldface type apply over the full Operating Temperature Range ( TJ = −40°C to +125°C). Typical values represent the most likely parametric norm at TA = TJ = +25°C, and are provided for reference purposes only. Symbol Parameter Conditions Min (Note 4) 12.2 7.4 Typ (Note 5) 13.0 7.9 9 40 No Switching VFB = 0V 2.43 VFB = 2.5V VFB = 2.5V VFB < 1.8V VCMP Falling VFB Falling VFB Falling 150 328 69 60 43 1.6 515 2.50 100 115 85 51 5 VTHM -0.08 20 168 20 346 20 1.20 x VFB VCMP = 0.5V 415 1.47 334 Both edges 0 to 5.5 VTHM to VTHM +2 500 V kΩ 356 8 378 1.22 x VFB V µA V mV µs 368 186 mV 161 110 59 625 2.57 Max (Note 4) 13.6 8.5 Units Electrical Characteristics SUPPLY VOLTAGE INPUT (VCC) VCC-RISE VCC-FALL Controller Enable Threshold Controller Disable Threshold Glitch Filter Delay Turn-on Delay IQ IQ-SD VFB GM VCC Quiescent Current VCC Shutdown Current FB Reference (Normal Operation) Input Bias Current Transconductance Output Source / Sink Capability FB Pull-up Current Source COMP Pull-up Resistor VCMP-B VFB-SD VFB-EAD VFB-OV VTHM VAC-DET COMP Low Threshold (Burst) COMP Low Hysteresis Low Threshold (Shutdown) FB Low Hysteresis FB Mid Threshold (EA Disabled) FB Mid Hysteresis FB High Threshold (Over-voltage) COMP Pre-bias Source Current Minimum COMP Voltage (Normal) VAC Angle Detection Threshold Angle Demodulation Delay Time VAC Dynamic Input Voltage Range COMP Dynamic Input Voltage Range VAC Input Impedance VCC Rising VCC Falling V µs mA µA V nA µS µA kΩ V ERROR AMPLIFIER & COMPENSATION (FB, COMP) ANGLE DEMODULATION & MULTIPLIER (COMP, VAC) www.national.com 4 LM3450 Symbol KM Parameter Multiplier Gain (Includes Internal Resistor Divider) ZCD Input Threshold Hysteresis Delay to Output Conditions VAC = 3V, VCMP = VTHM+1.5V VZCD Rising Min (Note 4) Typ (Note 5) 0.5 Max (Note 4) Units 1/V ZERO CURRENT DETECTOR (ZCD) VZCD-RIS 1.45 150 IZCD = 1mA IZCD = -50µA 1.5 200 135 6.0 0.61 30 20 1.40 1.50 100 1 140 56 75 50 1 VADJ Open ISEN Short to GND 3 1.60 1.55 250 V mV ns V VZCD-H VZCD-L VOS VLIM Positive Clamp Voltage Negative Clamp Voltage PWM Comparator Input Offset Voltage PWM Comparator Input Bias Current CS Current Limit Threshold CS Delay to Output CS Blanking Sinking Impedance PWM COMPARATOR (CS) mV nA V ns kΩ ns tLEB VADJ-LP Leading Edge Blanking (LEB) Time VADJ Low Threshold (Low Power Mode) VADJ Falling VADJ Low Hysteresis VADJ Pull-up Current Source VADJ Open Voltage ANALOG ADJUST INPUT (VADJ) mV µA V DYNAMIC HOLD CIRCUIT (HOLD, ISEN) RDSON-HD VSEN-REF HOLD MosFET On-Resistance ISEN Reference Voltage ISEN Bias Current PRE-REGULATOR GATE DRIVE OUTPUT (BIAS) VBIAS BIAS High Voltage @ 100µA BIAS Low Voltage @ 100µA GATE DRIVER OUTPUT (GATE) VGATE-H GATE Voltage High GATE Pull Down Resistance GATE Peak Current REFERENCE VOLTAGE OUTPUT (VREF) VREF Reference Voltage Current Limit DIMMING OUTPUT (DIM, FLT1, FLT2) FLT1 Output Impedance Standby Mode Transition Mode Triangle Waveform Compared to FLT2 High Low fDIM tOFF-MAX tOFF-LP DIM Frequency Maximum Off-Time (Normal Operation) Off-Time (Low Power Mode) 180 OFF-TIMERS 340 42 µs 500 1.6 1.49 15 460 700 kΩ V mV Hz No Load 2.85 1.5 3 2.0 3.15 3.0 V mA (Note 6) IGATE = 20mA IGATE = 200mA 11.5 10.5 2 ±1.5 8 V Ω A VCC < VCC-FALL VCC > VCC-RISE 18.8 13.5 21 14 22.6 14.5 V 22 162 30 200 5 42 232 Ω mV µA 5 www.national.com LM3450 Symbol THERMAL SHUTDOWN Parameter Conditions Min (Note 4) Typ (Note 5) 160 20 Max (Note 4) Units Thermal Limit Threshold Thermal Limit Hysteresis THERMAL RESISTANCE θJA θJC Junction to Ambient Junction to Case (Note 6) °C TSSOP-16 (Note 6, Note 7) 38.0 10.0 °C/W Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is guaranteed and do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics table. All voltages are with respect to the potential at the GND pin, unless otherwise specified. Note 2: Refer to National’s packaging website for more detailed information and mounting techniques. http://www.national.com/analog/packaging/ Note 3: Human Body Model, applicable std. JESD22-A114-C. Machine Model, applicable std. JESD22-A115-A. Field Induced Charge Device Model, applicable std. JESD22-C101-C. Note 4: All limits guaranteed at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are 100% production tested. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL). Note 5: Typical numbers are at 25°C and represent the most likely norm. Note 6: These electrical parameters are guaranteed by design, and are not verified by test. Note 7: Junction-to-ambient thermal resistance is highly board-layout dependent. In applications where high maximum power dissipation exists, namely driving a large MOSFET at high switching frequency from a high input voltage, special care must be paid to thermal dissipation issues during board design. In high-power dissipation applications, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C for Q1, or 150°C for Q0), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX). www.national.com 6 LM3450 Typical Performance Characteristics HOLD RDSON vs. Junction Temperature TA=+25°C and VCC = 14V unless otherwise specified Leading Edge Blanking vs. Junction Temperature 30127415 30127404 Current Limit Threshold vs. Junction Temperature VAC = 3V; VCMP = VTHM + 1.5V Multiplier Gain vs. Junction Temperature VAC = 3V; VCMP = VTHM + 1.5V 30127405 30127406 Transconductance VFB = 2.5V; ΔVFB = 50mV BIAS Voltage vs. Junction Temperature High @ VCC < VCCFALL; Low @ VCC > VCCRISE 30127407 30127408 7 www.national.com LM3450 VCC UVLO Threshold vs. Junction Temperature Shutdown Current vs. Junction Temperature 30127409 30127410 VREF Reference vs. Junction Temperature FB Reference vs. Junction Temperature 30127411 30127412 ISEN Reference vs. Junction Temperature VAC Detection Threshold vs. Junction Temperature 30127413 30127414 www.national.com 8 LM3450 Transconductance vs. VFB Current Sense Threshold vs. VCOMP and VAC 30127416 30127417 9 www.national.com LM3450 Block Diagram 30127421 www.national.com 10 LM3450 30127422 FIGURE 1. Typical Flyback Application Theory of Operation The LM3450 is a single device with both power factor control (PFC) and phase dimming decoder functions. This device is designed to control isolated flyback converters and provide active power factor correction. In addition to being a PFC, the LM3450 can interpret a phase dimming (frequently called triac dimming) input and provide a corresponding PWM output to properly dim an LED load. This combination of features provides an excellent method to convert a standard AC mains input to a dimmable LED output of 10-100W. It should be noted that the LM3450 can control a boost converter in a similar manner. However, this datasheet will focus mostly on the flyback topology due to the high demand for isolated LED driver applications. Discussion of the LM3450 functionality will refer to Figure 1 component designators. The PFC control operates in critical conduction mode (CRM) using zero crossing detection (ZCD) to terminate the off-time. The PFC portion of this device includes an error amplifier, multiplier, current sense circuit, zero crossing detector, and gate driver. The internal error amplifier is used for feedback of the output voltage in non-isolated designs. However, it can be disabled for isolated designs where the error amplifier needs to be on the secondary side. The phase dimmer decoder detects the dimming angle of the rectified AC line, decodes, filters and remaps it to a 500Hz PWM output. The PWM output can then be sent directly, or through optical isolation, to the dimming input of a second stage LED driver. To ensure the decoder properly interprets the dimming angle, dynamic hold is provided which prevents the phase dimmer from misfiring. The input current is sensed and when the current drops below a preset minimum, the system adds more current. Both the dynamic hold and the decoder are sampled synchronously to reduce the overall efficiency drop due to the additional hold current. When a decoding sample period occurs, the dynamic hold is activated to ensure a proper angle is decoded. Because of this sampling method, non-sampled cycles will potentially cause the phase dimmer to misfire but should not affect the output LED current regulation. Finally, the dynamic filter and variable sampling rate provide fast, smooth dimming transitions. 11 www.national.com LM3450 30127423 FIGURE 2. PFC System Architecture PFC BACKGROUND Power factor (PF) is a number between 0 and 1 that indicates how well energy is transmitted from input to output of a system. It can be described by average power (PAVG), RMS voltage (VRMS), and RMS current (IRMS): quency content is removed with large energy storage capacitance at the output. With minimal input capacitance, the converter is able to provide two important functions at the same time: • Shape the input current • Regulate the output voltage The PFC control approach requires two separate control loops to achieve both functions: a fast loop which shapes the input current, and a slow loop that regulates the output voltage. The fast control loop shapes the input current to have the same sinusoidal shape as the AC input voltage. Assuming both are perfect sinusoids with zero distortion or phase shift, the power factor will be perfect (unity). Unfortunately, distortion is always present in switching converters. An input filter, which is required to comply with EMI standards, helps to attenuate the switching content, thereby reducing distortion. However, the added filter capacitance will increase the phase shift at the same time. Though perfect PF is not achievable within real applications, extremely high PF (>.99) is possible using most active PFCs. The output voltage has to be regulated slowly to ensure the converter ignores the twice line frequency ripple present on the output. Therefore, the voltage loop containing the error amplifier should have a bandwidth at least an order of magnitude slower (.95) is still possible. Or by distortion factor (KDIST) and displacement factor (KDISP): With a purely resistive system, PF = 1. The addition of reactive elements necessary in any converter, such as EMI filters and energy storage, will induce some amount of displacement (phase shift between the input voltage and input current). The addition of switching devices will also create distortion (energy present in the harmonics relative to the switching frequencies). These non-idealities decrease the PF towards zero. Active power factor correction attempts to make the input impedance look as resistive as possible to the power source. Since the output of the converter is usually a regulated voltage or current, there is a need for large energy storage elements to remove the twice line frequency (100Hz or 120Hz) ripple. A power factor control architecture, as shown in Figure 2, has very little capacitance at the input. Instead, the twice line fre- www.national.com 12 LM3450 30127424 FIGURE 3. Basic CRM Inductor Current Waveform CRM BACKGROUND During critical conduction mode (CRM), a converter operates at the boundary of continuous conduction mode (CCM) and discontinuous conduction mode (DCM). This is usually implemented as follows. The main switching MosFET (QSW) is turned on and the inductor current rises to a peak threshold. QSW is then turned off and the current falls until it reaches zero. At this point, QSW is turned on and the cycle repeats. Near zero voltage switching, enabled by the inductor current return to zero, gives CRM topologies an efficiency improvement compared to CCM topologies. Figure 3 shows the resulting inductor current waveform, where the average inductor current (IL) is half of the peak current (IL-MAX). In a CRM flyback PFC application, the rectified AC input is fed forward to the control loop, creating a sinusoidal primary peak current envelope (IP-pk) as shown in Figure 4. The secondary peak current envelope (IS-pk) will simply be a scaled version of the primary according to the turns ratio of the transformer. Assuming good attenuation of the switching ripple via the EMI filter, the average input current (IIN), represented by the red line in Figure 4, can also be approximated as a sinusoid proportional to the duty cycle (D(t)): Since CRM operation is hysteretic and the input voltage is fedforward, the input current shaping loop is as fast as possible. Only the output voltage needs to be regulated with a narrow bandwidth error amplifier, which greatly simplifies the system dynamics. 30127425 FIGURE 4. CRM Flyback Current Waveforms 13 www.national.com LM3450 30127426 FIGURE 5. PFC Control Circuit POWER FACTOR CONTROLLER The LM3450 uses CRM control to regulate the output voltage and provide power factor correction. In a non-isolated boost topology, an external voltage divider (RFB1, RFB2) is used to sense the output voltage, as shown in Figure 5. The divider is connected to the inverting input (FB) of the internal error amplifier. The LM3450 regulates the feedback voltage (VFB) to 2.5V in a closed loop fashion. The FB pin has a shutdown mode to protect against a feedback short which can cause excessive energy transfer to the output. In the same manner, the FB pin also has an OVP mode which terminates switching when output over-voltage is sensed. With the FB shutdown mode, it is necessary to have a preliminary biasing method for the output of the error amplifier (COMP). Otherwise, the converter would never start. COMP is pre-biased with a 415µA current until the voltage at COMP (VCMP) exceeds the minimum operational voltage (VTHM). For an isolated topology flyback topology, where the error amplifier is on the secondary, the LM3450 internal error amplifier can be bypassed engaging a 5kΩ pull-up resistor at COMP. COMP can then be connected directly to the optical isolation as shown in Figure 5. COMP and the sensed rectified AC input voltage (VAC), provided via a resistor divider (RAC1, RAC2), are inputs to the multiplier. The current through the sense resistor (RCS) produces a voltage (VCS) that is compared to the multiplier output. When VCS exceeds the multiplier output, QSW is turned off. The peak detect threshold and the current slope during an on-time are proportionally changing which yields a nearly constant on-time, shown in Figure 4: Once QSW is turned off, the LM3450 waits until the inductor (boost) or transformer (flyback) is demagnetized to turn Q SW on again. Demagnetization, sensed at ZCD, occurs when the current through the magnetic component falls to zero. Since the output voltage is regulated, the slope of the current remains relatively constant and, coupled with the variable peak detect, creates a variable off-time. The sinusoidal peak detection envelope creates an input current that is sinusoidal and in phase with the input voltage providing excellent PF. The PWM comparator 30mV input offset voltage ensures current is also drawn at the zero-crossings of the rectified AC line, reducing distortion and further improving PF. CURRENT SENSE The LM3450 senses current through QSW via a sense resistor (RCS) between the source of QSW and GND. When VCS exceeds the output of the multiplier (VMLT), QSW is turned off. VMLT is variable over the line cycle and is a function of the scaled rectified AC voltage (VAC), the COMP voltage referenced from its operational minimum (VCOMP-VTHM), the multiplier gain (KM) and the PWM comparator offset (VOS): It should be noted that the LM3450 leading edge blanking (LEB) circuit pulls the current sense input to the PWM comparator low for 140µs at the beginning of each on-time. The LEB blanks the current spike and associated ringing due to the turn-on transient of QSW, limiting the minimum achievable duty cycle. OVER CURRENT PROTECTION The LM3450 has a current limit threshold (VLIM = 1.5V) at CS to protect QSW along with the rest of the system from overcurrent conditions. If VCS exceeds VLIM, QSW is immediately turned off. www.national.com 14 LM3450 30127427 FIGURE 6. ZCD Waveforms for Flyback Design ZERO CURRENT DETECTION ZCD is implemented with a 100kΩ resistor from the ZCD pin to a coupled winding on the transformer or inductor as shown in Figure 5. This winding is also used to bootstrap VCC after start-up. When QSW turns off, the voltage at the ZCD pin (VZCD) increases as energy is transferred through the auxiliary winding. The circuit arms when VZCD exceeds 1.5V. Then, when the energy is fully transferred, VZCD decreases towards zero. When VZCD falls below 1.3V, the transformer is assumed to be fully demagnetized, the circuit disarms, and QSW is turned back on as shown in Figure 6. The ZCD pin will remain low until QSW is turned off via peak detection and the cycle repeats. SWITCHING FREQUENCY With a constant on-time and variable off-time, there is a variable switching frequency: complex and cumbersome. To aid the designer, Table 1 in the Appendix gives compensation recommendations for a variety of applications. If a detailed analysis is desired, see Application Note AN-2098. If the COMP pin voltage (VCMP) falls below 1.4V at any time, the device enters burst mode where the GATE is off for 340µs then is turned on. If VCMP is still below 1.4V at the end of the on-time then another 340µs off-time occurs. However, if VCMP has risen above 1.4V, the converter continues switching until it falls below the threshold again. This feature is necessary to prevent the output of the converter from rising arbitrarily high because the minimum on-time of the device prevents less energy transfer. The LM3450 also implements both feedback short circuit protection and output over-voltage protection (OVP) functions at the FB pin. If VFB exceeds 3V, then OVP is engaged and the part stops switching until VFB falls below 3V. In the same manner, if VFB falls below 168mV, then shutdown is engaged and switching stops until VFB exceeds 188mV. The flyback topology is frequently used to provide isolation from input to output. Since, the current transfer ratio (CTR) of standard optical isolation varies over temperature, proper regulation using primary error amplifiers is difficult. An error amplifier is usually placed in the secondary to regulate the output voltage accurately. To accommodate isolated designs, the LM3450 internal error amplifier can be bypassed by placing a 5.11kΩ resistor from FB to GND. This engages a 5kΩ pull-up resistor from COMP to an internal 5V rail. SECONDARY ERROR AMPLIFIER For isolated designs, the error amplifier on the secondary should take the form of a proportional integral (PI) compensator. The amplifier is frequently implemented with a LM431 (low cost with internal reference). The output voltage resistor divider (RFB1, RFB2) provides the scaled output voltage to the LM431 inverting input. The PI compensation is achieved by connecting RSC and CSC in between the LM431 input and output, shown in Figure 7. In addition to the basic error amplifier, a soft-start circuit can be implemented using a capacitor, two diodes and a Zener diode as shown in Figure 7. CCMP is placed from COMP to GND for high frequency noise attenuation. Figure 4 shows that the minimum switching frequency occurs at the peak of the rectified AC waveform, while the maximum switching frequency occurs at the valley. ERROR AMPLIFIER The LM3450 internal error amplifier is used for non-isolated designs (boost) where the output voltage can be directly sensed, via a resistor divider, at the FB pin. The FB pin is the inverting input of the trans-conductance amplifier which is regulated to 2.5V. The COMP pin is the output of the amplifier and external compensation is placed from COMP to GND in the form of a single capacitor (CCMP) as shown in Figure 5, a series resistor and capacitor, or both. The output of the amplifier sources or sinks current as necessary to force the inputs of the amplifier to be equal. The compensation method depends upon the transient performance desired and requires a loop gain analysis. This analysis can be somewhat 30127428 FIGURE 7. Secondary Error Amplifier 15 www.national.com LM3450 PHASE DIMMER OPERATION A simplified schematic of a phase dimmer is shown in Figure 8. An RC network consisting of R1, R2, and C1 delay the turnon of the triac until the voltage on C1 reaches the trigger voltage of the diac. Increasing the resistance of the potentiometer (wiper moving downward) increases the turn-on delay which decreases the on-time or “conduction angle” of the triac (θ). This reduces the average power delivered to the load. 30127429 FIGURE 8. Basic Forward Phase Dimmer Phase dimmer voltage waveforms are shown in Figure 9. Figure 9a shows the full sinusoid of the input voltage. Even when set to full brightness; few dimmers will provide 100% conduction angle. Figure 9b shows a waveform from a forward phase dimmer. The off-time can be referred to as the firing angle and is simply 180° – θ. Figure 9c shows the waveform of a reverse phase dimmer (also called an electronic dimmer in the lighting industry). These typically or more expensive, microcontroller based dimmers that use switching devices other than triacs. Note that the conduction angle starts from the zero-crossing, and terminates some time later. This method of control reduces the noise spike at the transition. Any form of phase dimming modulates the incoming AC waveform by chopping part of the sinusoid, reducing the average power to the load. These dimmers work very well with standard incandescent bulbs, but not with power converters. A converter attempts to regulate the load in with presence of any input, effectively ignoring the phase angle. To implement a dimmable converter, the angle must be sensed at the input, decoded and used to properly control the LED current regulator. 30127430 FIGURE 9. Phase Dimming Waveforms PRECISION VOLTAGE REFERENCE The LM3450 provides a 3V voltage reference (VREF) for biasing the VADJ pin as well as any external circuitry. VREF is regulated once VCC exceeds 3V. There is a 2mA current limit for the reference. A 10nF ceramic bypass capacitor should be placed from VREF to GND. LOW POWER SHUTDOWN The LM3450 can be placed into a low power shutdown by grounding the VADJ pin (any voltage below 75mV). During low power shutdown, the device will turn on the GATE for one cycle followed by a fixed off-time of 42µs and the cycle repeats. During shutdown, the DIM output will be high (zero light output) since the buffer rail at FLT1 will be at or near zero. This feature is designed to hold up the PFC output voltage while removing the load (turning the LEDs off). THERMAL SHUTDOWN Internal thermal shutdown circuitry is provided to protect the IC in the event that the maximum junction temperature is exceeded. The threshold for thermal shutdown is 160°C with a 20°C hysteresis. During thermal shutdown GATE is disabled. www.national.com 16 LM3450 30127431 FIGURE 10. Dimming Decoder Circuit PHASE DIMMING DECODER The LM3450 uses the rectified AC line voltage to interpret the conduction angle. Figure 10 shows the LM3450 decoder circuit with associated external circuitry. The rectified AC line voltage is scaled via a resistor divider (RAC1, RAC2) and connected to the VAC pin. VAC is compared to a 356mV reference to generate a twice line frequency PWM signal with corresponding duty cycle as shown in Figure 11. of low dimming levels to the human eye. A minimum duty cycle limits the maximum achievable contrast ratio to approximately 70:1. The remapped PWM signal is buffered and output at FLT1 with amplitude equal to VADJ as shown in Figure 12. 30127433 FIGURE 12. FLT1 to FLT2 Mapping The FLT1 signal is routed through a 2 pole low pass filter (RF1, CF1, RF2, CF2), as shown in Figure 10, to remove the twice line frequency ripple. The resulting analog signal at FLT2 is compared to a 500Hz Triangle wave to create the inverted PWM signal at the DIM pin as shown in Figure 13: 30127432 FIGURE 11. Phase Angle Demodulation For best results, RAC1 and RAC2 are suggested to be sized so that the VAC voltage crosses the 356mV threshold when the rectified AC line is as follows: • 120V systems: 20V to 30V • 230V systems: 40V to 60V The demodulated duty cycle is sampled and logarithmically remapped to a 300Hz PWM signal improving the resolution 30127434 FIGURE 13. FLT2 to DIM Mapping 17 www.national.com LM3450 This PWM signal at the DIM pin can be used as the dim input to a secondary LED driver. DIM is an open drain output designed for isolated solutions. Optical isolation is used to transmit signals across the isolation boundary. With most optoisolators, the edge rate is dependent on the amount of drive current through the photodiode. The open-drain configuration allows the primary bias supply (VCC) to provide the current as shown in Figure 10. The choice of resistor (RPB) between VCC and the photodiode anode will set the drive current. This enables the user to trade-off PWM accuracy with system efficiency. The open drain configuration also ensures that the secondary has a resistor from the phototransistor’s emitter to secondary ground (not from collector to secondary bias). During system turn-off, this prevents an undesired LED blink because the secondary stage LED driver is forced off. A variable sample rate and dynamic filter ensure fast, smooth dimming transitions (movement of the dimmer) while maintaining robust flicker-free behavior when the dimmer is static. The sample rate depends on past and present angle information. The dynamic filter is a dual mode filter. During standby mode, when a transition has not been made and the dimmer is static, a 500kΩ series resistor is connected between the buffered output and FLT1 as shown in Figure 10. The 500kΩ resistor is shorted when the LM3450 senses a large transition of the dimmer. This increases the filter speed while the dimmer is transitioning between levels to improve response time. The FLT1 and FLT2 poles created by each RC pair (RF1 and CF1, RF2 and CF2) should be set as follows: • CF1 and CF2 can be 1µF ceramic capacitors for all designs. RF1 and RF2 should be set between 15kΩ (~10Hz) and 75kΩ (~2Hz). 2 Hz poles provide a “smooth fade” while 10Hz poles create a “snappy” response. These component values ensure that the static filter condition in standby mode has 1 pole approximately a decade lower than the nominal in order to provide good noise immunity to the system. Since the buffered decoder output has amplitude equal to VADJ and the resulting PWM signal is filtered into an analog voltage at FLT2, the VADJ pin can be used to change the mapping (extend the usable range of some dimmers). The maximum LED current (DIM = 0) when VADJ = 3V corresponds to decoded angles of 70% or greater. Some dimmers have a maximum angle greater than this. If VADJ is reduced to 2.5V, the maximum LED current will correspond to an angle of 80% and at VADJ = 2V the maximum will occur at a decoded angle of 95%. The VADJ pin can also be used to implement a standard analog adjust function. If the demodulated phase angle at VAC is above 85%, then the fast filter is always enabled (500kΩ shorted) and the VADJ pin can solely be used to scale the DIM pin duty cycle. When VADJ is pulled below 75mV the part enters low power shutdown so the maximum attainable contrast ratio using VADJ only is approximately 40:1. Both FLT1 and FLT2 have pull-down MosFETs that are turned on when VCC UVLO falling threshold is triggered. This provides a quick discharge path for the capacitors and eliminates the possibility of an undesired light level at the next startup. • www.national.com 18 LM3450 30127435 FIGURE 14. Dynamic Hold Circuit DYNAMIC HOLD A forward phase “triac” dimmer requires a minimum amount of current to be flowing through it during the entire conduction angle. This is referred to as hold current. If the minimum hold current requirement is not met, the triac will shut off (misfire). During normal operation, the converter will demand some amount of input current. However, at any point during the cycle, the input current can be low enough to cause a misfire. During an LM3450 sampling period, the triac should not misfire or the decoded angle will be inaccurate as shown in Figure 15. Since the triac is asymmetrical phase-to-phase, misfires can occur at different points in the waveform. After the triac misfires, the voltage returns to zero exponentially. This can create a large difference between decoded angles which can be observed as a “fluttering” of the light. a voltage across the resistance (RHLD) from the source of QPS to HOLD. This extra current is drawn from the input through the triac, but is not processed by the converter. Figure 16 shows a typical dynamic hold waveform where interval 1 is a non-sampled conduction angle, 2 is the firing angle, and 3 is a sampled conduction angle. 30127437 FIGURE 16. Dynamic Hold Waveform The dynamic hold function is also necessary for reverse phase dimmers, but for a different reason. Reverse phase dimmers do not use triacs, therefore they do not require a minimum “holding” current. Instead, they need what is commonly called bleeder current. When a reverse phase dimmer turns off, the AC voltage is at a high value. There is an RC time constant associated with discharging the total effective input capacitance (EMI capacitors, PFC capacitor, damper capacitance). The decoder does not record the angle until the voltage reaches the 356mV threshold. This can cause the decoded angle to be much larger than it actually is and dependent on the RC time constant as shown in Figure 17. 30127436 FIGURE 15. Forward Phase Waveform To ensure the triac does not misfire during a sampling period and the angle is correctly decoded, a dynamic hold function is enabled. The input current is sensed with a resistor (RSEN) from GND to ISEN (the return of the full bridge rectifier). If the voltage across this resistor is less than 200mV, the device adds holding current via the HOLD circuitry to maintain 200mV across RSEN. The hold current is added by linearly adjusting the gate voltage of QHLD as shown in Figure 14. As the gate voltage of QHLD is increased, the HOLD pin voltage decreases, forcing 19 www.national.com LM3450 The maximum possible additional holding current (which can occur when HOLD is still transitioning usually at the rising edge of the triac firing) can be approximated: 30127438 FIGURE 17. Reverse Phase Waveforms The dynamic hold will quickly bleed off the excess charge in an attempt to regulate the voltage across RSEN. This will preserve the accuracy of the decoded phase angle. During the conduction angle (θ), dynamic hold is enabled only during a sample period. However, during the firing angle (delay time), dynamic hold is always enabled to ensure the rectified line voltage does not begin to rise due to leakage currents through the phase dimmer. The minimum regulated input current can be calculated: It is recommended that the maximum hold current is set 10-15% higher than the minimum regulated input current. A minimum of 0.1µF capacitance should be placed between ISEN and HOLD to limit the bandwidth of the dynamic hold circuit to well below the switching frequency. However, if too large a capacitor is used, the bandwidth will be too low to respond to line transients. A maximum of 0.47µF should ensure good performance. Finally, a small Schottky diode should be placed from GND to ISEN to absorb the large current spikes associated with the triac firing edge. This diode should have a VF above 200mV at the worst-case operating temperature so that it won’t interfere with dynamic hold regulation. www.national.com 20 LM3450 PRIMARY BIAS SUPPLY The LM3450 requires a supply voltage at VCC, not to exceed 25V. The device has VCC under-voltage lockout (UVLO) with rising and falling thresholds of 12.9V and 7.9V respectively. A 24V Zener diode should be placed from the VCC pin to GND to protect the device from substantial spikes that could cause damage. Figure 18 shows how the LM3450 provides a quick way to generate the necessary primary bias supply at start-up. Since the AC line peak voltage is always higher than the rating of the controller, all designs require an N-channel MosFET (passFET). The passFET (QPS) is connected with its drain attached to the rectified AC. The gate of QPS is connected to the BIAS pin which has a stack of 2 Zener diodes internal to the device. These diodes are then biased from the rectified AC line through series resistance (RBS). The source of QPS is held at a VGS below the Zener voltage and current flows through QPS to charge up whatever capacitance is present. If the capacitance is large enough, the source voltage will remain relatively constant over the line cycle and this becomes the input bias supply at VCC. This bias circuit enables instant turn-on. However, once the circuit is operational it is desirable to bootstrap VCC to an auxiliary winding of the inductor or transformer (also used for ZCD). The two bias paths are each connected to VCC through a diode to ensure the higher of the two is providing VCC current. This bootstrapping greatly improves efficiency when quick start-up is necessary. To ensure that the auxiliary winding is powering VCC at all times except start-up, the LM3450 has a dual BIAS mode. The BIAS voltage at startup is 20V through two Zener diodes. When the VCC UVLO rising threshold is exceeded and the device turns on, the BIAS pin voltage is reduced to 14V (bottom 6V Zener is shorted). Once the VCC UVLO falling threshold is reached again, the BIAS pin will return to 20V to attempt to restart the device. It should be noted that the large hysteresis of VCC UVLO and the dual BIAS mode allow for a large variation of the auxiliary bias circuitry easing the design of the magnetics. 30127439 FIGURE 18. Primary Bias Circuitry 21 www.national.com LM3450 Applications Information See AN-2098 for detailed design and application information. TWO STAGE LED DRIVER – LM3450 Primary and LM3409 Secondary 30127440 www.national.com 22 LM3450 15W TWO STAGE DESIGN SPECIFICATIONS AC Input Voltage: 120VAC nominal (90VAC - 135VAC) Regulated Flyback Output Voltage: 50V Regulated LED Current: 350mA LED Stack Voltage Maximum: 45V Bill of Materials Reference Designator LM3450 LM3409 LMV431 C1a, C1b, C5a, C5b C2, C3 C4 C6 C7a C7b, C8b, C9b, C15 C8a, C9a C10 C11 C12, C13 C14, C21 C16 C17 C18 C19 C20 C22 D1, D2 D3, D5 D4 D6 D7 D8 D9 D10 D11, D12 D13 D14 D15 D16 L1 L2, L3 L4 Q1 Q2 Q3, Q4 Q5 R1 R2 R3 Part Value IC PFC CONT 16-TSSOP IC LED DRIVR 10-eMSOP IC SHUNT REG SOT-23 CAP CER 0.22µF 250V 1210 CAP MPY 47nF 250VAC X1 RAD CAP MPY 0.1µF 400V RAD CAP CER 4.7nF 500VAC Y1 RAD CAP ELEC 470µF 63V RAD CAP CER 1µF 50V 1206 CAP ELEC 100µF 50V RAD CAP CER 10nF 25V 0603 CAP CER 47µF 6.3V 0805 CAP CER 1µF 16V 0603 CAP CER 0.22µF 16V 0603 CAP CER 10µF 16V 1206 CAP CER 1µF 100V 1206 CAP CER 2.2µF 6.3V 0603 CAP CER 4.7µF 100V 2220 CAP CER 470pF 100V 0603 DIODE ULTRAFAST 200V 1A SMA DIODE ULTRAFAST 100V 0.2A SOT-23 DIODE SCHOTTKY 20V 0.5A SOT-23 DIODE TVS 150V 600W UNI SMB DIODE ULTRAFAST 600V 1A SMA DIODE ZENER 24V 3W SMA DIODE SCHOTTKY 20V 3A SMA DIODE RECT 600V 0.5A Minidip DIODE ZENER 10V 500mW SOD-123 DIODE ULTRAFAST 70V 0.2A SOT-23 DIODE ZENER 3.3V 500mW SOD-123 DIODE ZENER 1.8V 500MW SOD-123 DIODE SCHOTTKY 60V 2A SMB IND LINE FILTER 6mH 0.3A 11M IND SHIELD 1mH 0.46A SMT IND SHIELD 470µH 1.06A SMT MOSFET N-CH 800V 3A DPAK MOSFET N-CH 600V 4.4A DPAK TRANS NPN 40V 0.6A SOT-23 MOSFET P-CH 70V 5.7A DPAK RES 330Ω 5% 1W 2512 RES 430Ω 5% 1W 2512 RES 953kΩ 1% 0.25W 1206 23 Manufacturer NSC NSC NSC MURATA EPCOS EPCOS EPCOS NICHICON TDK NICHICON MURATA TAIYO YUDEN MURATA TDK MURATA TDK TDK TDK TDK FAIRCHILD FAIRCHILD NXP SEMI LITTLEFUSE FAIRCHILD MICRO-SEMI FAIRCHILD COMCHIP FAIRCHILD FAIRCHILD ON-SEMI ON-SEMI ON-SEMI PANASONIC COILCRAFT COILCRAFT ST MICRO INFINEON FAIRCHILD ZETEX VISHAY VISHAY VISHAY Part Number LM3450 LM3409HVMY LMV431AIM5 GRM32DR72E224KW01L B32912A3333M B32612A4104J008 VY1472M63Y5UQ63V0 UPW1J471MHD3 C3216X7R1H105K UHE1H101MPD GRM188R71E103KA01D JMK212BJ476MG-T GRM188R71C105KA12D C1608X7R1C224K GRM31CR71C106KAC7L C3216X7R2A105M C1608X5R0J225M C5750X7R2A475K C1608C0G2A471J ES1D MMBD914 PMEG2005ET,215 SMBJ150A ES1J SMAJ5934B-TP ES2AA-13-F HD06 MMSZ5240B BAV99 MMSZ3V3T1G MMSZ4678T1G SS26T3G ELF-11M030E MSS1038-105KL MSS1260-474KLB STD3NK80ZT4 IPD60R950C6 MMBT4401 ZXMP7A17K CRCW2512330RJNEG CRCW2512430RJNEG CRCW1206953KFKEA www.national.com LM3450 R4 R5, R7, R10 R6 R8, R9 R11 R12 R13 R14a R14b R15a, R15b R16 R17 R18 R19 R20 R21 R22 R23 R24, R25 R26 R27 OPTO1, OPTO2 T1 RES 100Ω 1%1W 2512 RES 100kΩ 1% 0.1W 0603 RES 3.01kΩ 1% 0.1W 0603 RES 75.0kΩ 1% 0.1W 0603 RES 1.00MΩ 1% 0.25W 1206 RES 14.0kΩ 1% 0.1W 0603 RES 5.11kΩ 1% 0.1W 0603 RES 10Ω 1% 0.25W 1206 RES 1.00Ω 1% 0.33W 1210 RES 5.62Ω 1% 0.25W 1206 RES 2.00kΩ 1% 0.125W 0805 RES 20.0kΩ 1% 0.1W 0603 RES 105kΩ 1% 0.125W 0805 RES 2.67kΩ 1% 0.1W 0603 RES 6.04kΩ 1% 0.125W 0805 RES 10.0kΩ 1% 0.125W 0805 RES 80.6kΩ 1% 0.1W 0603 RES .62Ω 1% 0.5 2010 SMD RES 10kΩ 1% 0.1W 0603 RES 2.49kΩ 1% 0.125W 0805 RES 22Ω 10% 2W FILM OPTO-ISOLATOR SMD XFORMER 120V 15W OUTPUT 50V VISHAY VISHAY VISHAY VISHAY VISHAY VISHAY VISHAY VISHAY VISHAY VISHAY VISHAY VISHAY VISHAY VISHAY VISHAY VISHAY VISHAY ROHM VISHAY VISHAY WELWYN LITE ON WURTH WSL2512100RFKEA CRCW0603100KFKEA CRCW06033K01FKEA CRCW060375K0FKEA CRCW12061M00FKEA CRCW060314K0FKEA CRCW06035K11FKEA CRCW120610R0FKEA CRCW12101R00FNEA CRCW12065R62FNEA CRCW08052K00FKEA CRCW060320K0FKEA CRCW0805105KFKEA CRCW06032K67FKEA CRCW08056K04FKEA CRCW080510K0FKEA CRCW060380K6FKEA MCR50JZHFLR620 CRCW060310K0FKEA CRCW08052K49FKEA EMC2-22R0 CNY17F-3S 750813550 www.national.com 24 LM3450 25 www.national.com LM3450 Physical Dimensions inches (millimeters) unless otherwise noted TSSOP-16 Pin Package (MTC) For Ordering, Refer to Ordering Information Table NS Package Number MTC16 www.national.com 26 LM3450 Notes 27 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