INTEGRATED CIRCUITS
74ABT16823A
18-bit bus interface D-type flip-flop
with reset and enable (3-State)
Product data
Replaces data sheet 74ABT16823A/ABTH16823A of 1998 Feb 27
2004 Feb 02
Philips Semiconductors
Product data
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
74ABT16823A
FEATURES
DESCRIPTION
• Two sets of high speed parallel registers with positive
The 74ABT16823A 18-bit bus interface register is designed to
eliminate the extra packages required to buffer existing registers and
provide extra data width for wider data/address paths of buses
carrying parity.
edge-triggered D-type flip-flops
• Ideal where high speed, light loading, or increased fan-in are
required with MOS microprocessors
The 74ABT16823A has two 9-bit wide buffered registers with Clock
Enable (nCE) and Master Reset (nMR) which are ideal for parity bus
interfacing in high microprogrammed systems.
• Live insertion/extraction permitted
• Power-up 3-State
• Power-up Reset
• Output capability: +64 mA/–32 mA
• Latch-up protection exceeds 500 mA per Jedec Std 17
• ESD protection exceeds 2000 V per MIL STD 883 Method 3015
The registers are fully edge-triggered. The state of each D input, one
set-up time before the LOW-to-HIGH clock transition is transferred
to the corresponding flip-flop’s Q output.
and 200 V per Machine Model
QUICK REFERENCE DATA
SYMBOL
CONDITIONS
Tamb = 25 °C; GND = 0 V
PARAMETER
TYPICAL
UNIT
2.3
1.9
ns
tPLH
tPHL
Propagation delay
nCP to nQx
CL = 50 pF; VCC = 5 V
CIN
Input capacitance
VI = 0 V or VCC
4
pF
Output capacitance
VO = 0 V or VCC; 3-State
6
pF
500
µA
9
mA
COUT
ICCZ
Outputs disabled; VCC = 5.5 V
Quiescent su
supply
ly current
ICCL
Outputs low; VCC = 5.5 V
ORDERING INFORMATION
Tamb = –40 °C to +85 °C
Package
Type number
Name
Description
Version
74ABT16823ADL
SSOP56
plastic shrink small outline package; 56 leads; body width 7.5 mm
SOT371-1
74ABT16823ADGG
TSSOP56
plastic thin shrink small outline package; 56 leads; body width 6.1 mm
SOT364-1
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
2, 27
1OE, 2OE
Output enable input (active-LOW)
54, 52, 51, 49, 48, 47, 45, 44, 43
42, 41, 40, 38, 37, 36, 34, 33, 31
1D0-1D8
2D0-2D8
Data inputs
3, 5, 6, 8, 9, 10, 12, 13, 14
15, 16, 17, 19, 20, 21, 23, 24, 26
1Q0-1Q8
2Q0-2Q8
Data outputs
56, 29
1CP, 2CP
Clock pulse input (active rising edge)
55, 30
1CE, 2CE
Clock enable input (active-LOW)
1, 28
1MR, 2MR
Master reset input (active-LOW)
4, 11, 18, 25, 32, 39, 46, 53
GND
Ground (0 V)
7, 22, 35, 50
VCC
Positive supply voltage
2004 Feb 02
2
Philips Semiconductors
Product data
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
74ABT16823A
PIN CONFIGURATION
LOGIC SYMBOL (IEEE/IEC)
1MR
1
56
1CP
1OE
2
55
1CE
1Q0
3
54
1D0
GND
4
53
GND
1Q1
5
52
1Q2
6
VCC
7
1Q3
1OE
2
EN1
1MR
1
R2
1CE
55
G3
1CP
56
1D1
2OE
27
EN5
51
1D2
2MR
28
R6
50
VCC
2CE
30
G7
8
49
1D3
2CP
29
1Q4
9
48
1D4
3
10
47
1D5
1D0
54
1Q5
1Q0
1D1
52
5
1Q1
1D2
51
6
1Q2
1D3
49
8
1Q3
1D4
48
9
1Q4
1D5
47
10
1Q5
1D6
45
12
1Q6
1D7
44
13
1Q7
1D8
43
14
1Q8
15
2Q0
GND
1Q6
1Q7
1Q8
2Q0
2Q1
2Q2
GND
11
12
13
14
15
16
17
18
46
45
44
43
42
41
40
39
GND
1D6
1D7
1D8
2D0
2D1
2D2
GND
2D0
2Q3
19
38
2D3
2Q4
20
37
2D4
2Q5
21
36
2D5
VCC
22
35
VCC
2Q6
23
34
2D6
2Q7
24
33
2D7
GND
25
32
GND
2Q8
26
31
2D8
2OE
27
30
2CE
2MR
28
29
2CP
42
3C4
7C8
4D
8D
1, 2 ∇
5, 6 ∇
2D1
41
16
2Q1
2D2
40
17
2Q2
2D3
38
19
2Q3
2D4
37
20
2Q4
2D5
36
21
2Q5
2D6
34
23
2Q6
2D7
33
24
2Q7
2D8
31
25
2Q8
SH00015
SH00014
2004 Feb 02
3
Philips Semiconductors
Product data
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
74ABT16823A
LOGIC DIAGRAM
nCE
nD0
nD1
nD2
nD3
nD4
nD5
nD6
nD7
nD8
nCP
nD
CP
R
nD
CP
R
Q
nD
CP
R
Q
Q
CP
nD
nD
R
R
Q
CP
nD
R
Q
CP
nD
R
Q
CP
nD
R
Q
CP
nD
R
Q
CP
Q
nMR
nOE
nQ0
nQ1
nQ2
nQ3
nQ4
nQ5
nQ6
nQ7
nQ8
n = 1 or 2
SH00016
FUNCTION TABLE
INPUTS
OUTPUTS
nOE
nMR
nCE
nCP
nDx
nQ0 – nQ8
L
L
X
X
X
L
L
H
L
↑
h
H
L
H
L
↑
l
L
L
H
H
↑
X
NC
H =
h =
L =
l =
NC=
X =
Z =
↑ =
↑ =
H
X
X
X
X
Z
High voltage level
High voltage level one set-up time prior to the LOW-to-HIGH clock transition
Low voltage level
Low voltage level one set-up time prior to the LOW-to-HIGH clock transition
No change
Don’t care
High impedance “off” state
LOW-to-HIGH clock transition
Not a LOW-to-HIGH clock transition
2004 Feb 02
4
OPERATING MODE
Clear
Load and read data
Hold
High impedance
Philips Semiconductors
Product data
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
74ABT16823A
ABSOLUTE MAXIMUM RATINGS1, 2
PARAMETER
SYMBOL
VCC
IIK
CONDITIONS
RATING
UNIT
–0.5 to +7.0
V
–18
mA
–1.2 to +7.0
V
VO < 0 V
–50
mA
output in Off or HIGH state
–0.5 to +5.5
V
output in LOW state
128
output in HIGH state
–64
DC supply voltage
DC input diode current
VI < 0 V
voltage3
VI
DC input
IOK
DC output diode current
voltage3
VOUT
DC output
IOUT
O
DC output current
Tstg
Storage temperature range
mA
–65 to 150
°C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
VCC
PARAMETER
UNIT
DC supply voltage
MIN
MAX
4.5
5.5
V
0
VCC
V
VI
Input voltage
VIH
HIGH-level input voltage
2.0
–
V
VIL
LOW-level input voltage
–
0.8
V
IOH
HIGH-level output current
–
–32
mA
IOL
LOW-level output current
–
64
mA
∆t/∆v
Input transition rise or fall rate
0
10
ns/V
Tamb
Operating free-air temperature range
–40
+85
°C
2004 Feb 02
5
Philips Semiconductors
Product data
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
74ABT16823A
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
VIK
VOH
PARAMETER
Input clamp voltage
HIGH-level output voltage
Tamb = –40 °C to
+85 °C
Tamb = +25 °C
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
MAX
–
–0.9
–1.2
–
–1.2
V
VCC = 4.5 V; IOH = –3 mA; VI = VIL or VIH
2.5
2.9
–
2.5
–
V
VCC = 5.0 V; IOH = –3 mA; VI = VIL or VIH
3.0
3.4
–
3.0
–
V
VCC = 4.5 V; IOH = –32 mA; VI = VIL or VIH
2.0
2.4
–
2.0
–
V
VCC = 4.5 V; IIK = –18 mA
VOL
LOW-level output voltage
VCC = 4.5 V; IOL = 64 mA; VI = VIL or VIH
–
0.42
0.55
–
0.55
V
VRST
Power-up output LOW
voltage3
VCC = 5.5 V; IOL = 1 mA; VI = GND or VCC
–
0.13
0.55
–
0.55
V
Input leakage curent
VCC = 5.5 V; VI = VCC or GND
–
±0.01
±1
–
±1
µA
Power-off leakage current
VCC = 0.0 V; VO or VI ≤ 4.5 V
–
±5.0
±100
–
±100
µA
Power-up/down 3-State
output current4
VCC = 2.1 V; VO = 0.5 V; VI = GND or VCC;
VOE = Don’t care
–
±5.0
±50
–
±50
µA
IOZH
3-State output HIGH current
VCC = 5.5 V; VO = 2.7 V; VI = VIL or VIH
–
1.0
10
–
10
µA
IOZL
3-State output LOW current
VCC = 5.5 V; VO = 0.5 V; VI = VIL or VIH
–
–1.0
–10
–
–10
µA
ICEX
Output HIGH leakage
current
VCC = 5.5 V; VO = 5.5 V; VI = GND or VCC
–
50
50
–
50
µA
Output current1
VCC = 5.5 V; VO = 2.5 V
–50
–80
–180
–50
–180
mA
VCC = 5.5 V; Outputs HIGH;
VI = GND or VCC
–
0.5
1
–
1
mA
VCC = 5.5V; Outputs LOW;
VI = GND or VCC
–
9.0
19
–
19
mA
VCC = 5.5V; Outputs 3–State;
VI = GND or VCC
–
0.5
1
–
1
mA
VCC = 5.5V; one input at 3.4 V,
other inputs at VCC or GND
–
0.2
1
–
1
mA
II
IOFF
IPU/PD
IO
ICCH
ICCL
Quiescent supply current
ICCZ
∆ICC
Additional supply current
per input pin2
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any VCC between 0V and 2.1V with a transition time of up to 10msec. From VCC = 2.1V to VCC = 5V ± 10% a
transition time of up to 100µsec is permitted.
2004 Feb 02
6
Philips Semiconductors
Product data
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
74ABT16823A
AC CHARACTERISTICS
GND = 0 V, tR = tF = 2.5 ns, CL = 50 pF, RL = 500 Ω
LIMITS
SYMBOL
PARAMETER
Tamb = +25 °C
VCC = + 5.0 V
WAVEFORM
Tamb = –40 °C to +85 °C
VCC = +5.0 V ± 0.5 V
UNIT
MIN
TYP
MAX
MIN
fMAX
Maximum clock frequency
1
140
190
–
140
MAX
tPLH
tPHL
Propagation delay
nCP to nQx
1
1.4
1.2
2.3
1.9
3.2
2.6
1.4
1.2
3.7
2.9
ns
tPHL
Propagation delay
nMR to nQx
2
2.0
3.3
4.3
2.0
5.0
ns
tPZH
tPZL
Output enable time
to HIGH and LOW level
4
5
1.3
1.2
2.4
2.1
3.2
2.9
1.3
1.2
3.9
3.4
ns
tPHZ
tPLZ
Output disable time
from HIGH and LOW level
4
5
1.7
1.6
2.9
2.3
4.0
3.2
1.7
1.6
4.7
3.4
ns
MHz
AC SET-UP REQUIREMENTS
GND = 0 V, tR = tF = 2.5 ns, CL = 50 pF, RL = 500 Ω
LIMITS
SYMBOL
PARAMETER
Tamb = +25 °C
VCC = + 5.0 V
WAVEFORM
Tamb = –40 °C to +85 °C
VCC = +5.0 V ± 0.5V
MIN
TYP
MIN
UNIT
ts(H)
ts(L)
Set-up time, HIGH or LOW
nDx to nCP
3
2.0
1.5
1.3
0.9
2.0
1.5
ns
th(H)
th(L)
Hold time, HIGH or LOW
nDx to nCP
3
1.5
1.5
–0.9
–1.2
1.5
1.5
ns
tw(H)
tw(L)
nCP pulse width
HIGH or LOW
1
3.3
3.3
1.7
1.7
3.3
3.3
ns
ts(H)
ts(L)
Set-up time, HIGH or LOW
nCE to nCP
3
1.5
2.0
0.9
0.9
1.5
2.0
ns
th(H)
th(L)
Hold time, HIGH or LOW
nCE to nCP
3
1.5
1.5
–0.8
–0.9
1.5
1.5
ns
tw(L)
nMR pulse width, LOW
2
3.0
1.7
3.0
ns
trec
Recovery time
nMR to nCP
2
2.5
1.0
2.5
ns
2004 Feb 02
7
Philips Semiconductors
Product data
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
74ABT16823A
AC WAVEFORMS
For all waveforms, VM = 1.5 V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
1/fMAX
nCP
VM
VM
VM
VM
0V
tPZH
0V
tw
3.0V or VCC
whichever
is less
nOE
3.0V or VCC
whichever
is less
tPLH
tPHZ
VOH
VOH–0.3V
tPHL
VOH
nQn
VM
VM
nQx
VM
0V
0V
SH00020
SH00017
Waveform 4. 3-State Output Enable Time to HIGH Level
and Output Disable Time from HIGH Level
Waveform 1. Propagation Delay, Clock Input to Output,
Clock Pulse Width, and Maximum Clock Frequency
VM
nMR
3.0V or VCC
whichever
is less
3.0V or VCC
whichever
is less
VM
nOE
tREC
tPZL
3.0V or VCC
whichever
is less
VM
nCP
nQx
0V
tPHL
SH00021
Waveform 2. Master Reset Pulse WIdth, Master Reset to
Output Delay and Master Reset to Clock Recovery Time
VM
VM
3.0V or VCC
whichever
is less
VM
0V
nCP
th(H)
VM
ts(L)
th(L)
VM
3.0V or VCC
whichever
is less
0V
SH00019
Waveform 3. Data Set-up and Hold Times
2004 Feb 02
VOL +0.3V
Waveform 5. 3-State Output Enable Time to LOW Level
and Output Disable Time from LOW Level
0V
SH00018
ts(H)
VM
3.0V or VCC
whichever
is less
VOL
VM
VM
tPLZ
VOH
nQn
nDx,
nCE
VM
0V
0V
tw
VM
8
Philips Semiconductors
Product data
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
74ABT16823A
TEST CIRCUIT AND WAVEFORM
VCC
7.0V
VIN
RL
VOUT
PULSE
GENERATOR
90%
VM
CL
AMP (V)
VM
10%
D.U.T.
RT
tW
90%
NEGATIVE
PULSE
10%
tTHL (tf )
tTLH (tr )
tTLH (tr )
tTHL (tf )
0V
RL
AMP (V)
90%
90%
Test Circuit for 3-State Outputs
POSITIVE
PULSE
VM
VM
10%
TEST
tPLZ
tPZL
All other
SWITCH
closed
closed
open
10%
tW
SWITCH POSITION
0V
VM = 1.5V
Input Pulse Definition
DEFINITIONS:
RL = Load resistor; see AC CHARACTERISTICS for value.
CL = Load capacitance includes jig and probe capacitance;
see AC CHARACTERISTICS for value.
RT = Termination resistance should be equal to ZOUT of
pulse generators.
INPUT PULSE REQUIREMENTS
FAMILY
74ABT16
Amplitude
Rep. Rate
tw
tR
tF
3.0V
1MHz
500ns
2.5ns
2.5ns
SH00022
2004 Feb 02
9
Philips Semiconductors
Product data
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
74ABT16823A
SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm
2004 Feb 02
10
SOT371-1
Philips Semiconductors
Product data
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
74ABT16823A
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm
2004 Feb 02
11
SOT364-1
Philips Semiconductors
Product data
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
74ABT16823A
REVISION HISTORY
Rev
Date
Description
_3
20040202
Product data (9397 750 12833); 853-1791 ECN 01-A15432 of 27 January 2004.
Replaces data sheet 74ABT_H16823A_2 of 1998 February 27 (9397 750 03502).
Modifications:
• Delete all references to 74ABTH16823A (product discontinued).
_2
19980227
Product specification (9397 750 03502); ECN 853-1791 19025 of 27 February 1998.
Supersedes data of 1995 Sep 28.
Data sheet status
Level
Data sheet status [1]
Product
status [2] [3]
Definitions
I
Objective data
Development
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL
http://www.semiconductors.philips.com.
[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given
in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no
representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be
expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree
to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described
or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated
via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys
no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent,
copyright, or mask work right infringement, unless otherwise specified.
Koninklijke Philips Electronics N.V. 2004
All rights reserved. Printed in U.S.A.
Contact information
For additional information please visit
http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
Date of release: 02-04
For sales offices addresses send e-mail to:
sales.addresses@www.semiconductors.philips.com.
Document order number:
2004 Feb 02
12
9397 750 12833
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