74ALVT16260DL,512

74ALVT16260 12-bit to 24-bit multiplexed D-type latches; 3-state Rev. 03 — 20 March 2006 Product data sheet 1. General description The 74ALVT16260 is a 12-bit to 24-bit multiplexed D-type latch used in applications where two separate data paths must be multiplexed onto, or demultiplexed from, a single data path. Typical applications include multiplexing or demultiplexing of address and data information in microprocessor or bus-interface applications. This device is also useful in memory-interleaving applications. Three 12-bit I/O ports (A1 to A12, 1B1 to 1B12 and 2B1 to 2B12) are available for address or data transfer. The output enable inputs (OE1B, OE2B, and OEA) control the bus transceiver functions. OE1B and OE2B also allow bank control in the A to B direction. Address or data information can be stored using the internal storage latches. The latch enable inputs (LE1B, LE2B, LEA1B and LEA2B) are used to control data storage. When the latch enable input is HIGH, the latch is transparent. When the latch enable input goes LOW, the data present at the inputs is latched and remains latched until the latch enable input is returned HIGH. To ensure the high-impedance state during power-up or power-down, all output enable inputs should be tied to VCC through a pull-up resistor. The minimum value of the resistor is determined by the current sinking capability of the driver. The 74ALVT16260 is available in a SSOP56 and a TSSOP56 package. 2. Features n n n n n n n n 5 V I/O compatible Bus hold inputs eliminate the need for external pull-up resistors Live insertion and extraction permitted Power-up 3-state Power-up reset Output capability: +64 mA and −32 mA Distributed VCC and GND pin configuration minimizes high-speed switching noise Latch-up protection: u JESD78: exceeds 500 mA n ESD protection: u MIL STD 883C, method 3015: exceeds 2000 V u Machine model: exceeds 200 V 74ALVT16260 Philips Semiconductors 12-bit to 24-bit multiplexed D-type latches; 3-state 3. Quick reference data Table 1. Quick reference data GND = 0 V; Tamb = 25 °C. Symbol Parameter Conditions Min Typ Max Unit - 40 - µA VCC = 2.5 V [1] ICC quiescent supply current VCC = 2.7 V; VI = GND or VCC; IO = 0 A; outputs disabled tPLH LOW-to-HIGH propagation delay An to xBn; xBn to An CL = 50 pF - 2.8 - ns tPHL HIGH-to-LOW propagation delay An to xBn; xBn to An CL = 50 pF - 2.7 - ns Ci input capacitance (control pins) VI = 0 V or VCC 4 - pF Cio input/output capacitance (I/O pins) VI/O = 0 V or 5.0 V 9 - pF - 60 - µA VCC = 3.3 V [1] ICC quiescent supply current VCC = 3.6 V; VI = GND or VCC; IO = 0 A; outputs disabled tPLH LOW-to-HIGH propagation delay An to xBn; xBn to An CL = 50 pF - 2.2 - ns tPHL HIGH-to-LOW propagation delay An to xBn; xBn to An CL = 50 pF - 2.0 - ns Ci input capacitance (control pins) VI = 0 V or VCC 4 - pF Cio input/output capacitance (I/O pins) VI/O = 0 V or 5.0 V 9 - pF [1] ICC is measured with outputs pulled up to VCC or pulled down to ground. 4. Ordering information Table 2. Ordering information Type number 74ALVT16260DL Package Temperature range Name Description Version −40 °C to +85 °C SSOP56 plastic shrink small outline package; 56 leads; body width 7.5 mm SOT371-1 74ALVT16260DGG −40 °C to +85 °C TSSOP56 plastic thin shrink small outline package; 56 leads; body width 6.1 mm 74ALVT16260_3 Product data sheet SOT364-1 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 03 — 20 March 2006 2 of 18 74ALVT16260 Philips Semiconductors 12-bit to 24-bit multiplexed D-type latches; 3-state 5. Functional diagram LE1B LE2B LEA1B LEA2B OE2B OE1B OEA SEL 2 27 30 55 56 29 1 28 C1 G1 A1 8 1D 23 1B1 1 1 C1 1D 6 2B1 C1 1D C1 1D to 11 other channels 001aae373 Fig 1. Logic diagram 74ALVT16260_3 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 03 — 20 March 2006 3 of 18 74ALVT16260 Philips Semiconductors 12-bit to 24-bit multiplexed D-type latches; 3-state 6. Pinning information 6.1 Pinning OEA 1 56 OE2B LE1B 2 55 LEA2B 2B3 3 54 2B4 GND 4 53 GND 2B2 5 52 2B5 2B1 6 51 2B6 VCC 7 A1 8 50 VCC 49 2B7 A2 9 48 2B8 A3 10 47 2B9 GND 11 46 GND A4 12 45 2B10 A5 13 44 2B11 A6 14 A7 15 43 2B12 74ALVT16260 42 1B12 A8 16 41 1B11 A9 17 40 1B10 GND 18 39 GND A10 19 38 1B9 A11 20 37 1B8 A12 21 36 1B7 VCC 22 1B1 23 35 VCC 34 1B6 1B2 24 33 1B5 GND 25 32 GND 1B3 26 31 1B4 LE2B 27 30 LEA1B SEL 28 29 OE1B 001aae369 Fig 2. Pin configuration 6.2 Pin description Table 3. Pin description Symbol Pin Description OEA 1 output A enable input (active LOW) LE1B 2 latch 1B to A enable input 2B3 3 2 data input/output B3 GND 4 ground (0 V) 2B2 5 2 data input/output B2 2B1 6 2 data input/output B1 VCC 7 supply voltage A1 8 data input/output A1 74ALVT16260_3 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 03 — 20 March 2006 4 of 18 74ALVT16260 Philips Semiconductors 12-bit to 24-bit multiplexed D-type latches; 3-state Table 3. Pin description …continued Symbol Pin Description A2 9 data input/output A2 A3 10 data input/output A3 GND 11 ground (0 V) A4 12 data input/output A4 A5 13 data input/output A5 A6 14 data input/output A6 A7 15 data input/output A7 A8 16 data input/output A8 A9 17 data input/output A9 GND 18 ground (0 V) A10 19 data input/output A10 A11 20 data input/output A11 A12 21 data input/output A12 VCC 22 supply voltage 1B1 23 1 data input/output B1 1B2 24 1 data input/output B2 GND 25 ground (0 V) 1B3 26 1 data input/output B3 LE2B 27 latch 2B to A enable input SEL 28 select B1 or B2 input OE1B 29 output 1B enable input (active LOW) LEA1B 30 latch A to 1B enable input 1B4 31 data input/output B4 GND 32 ground (0 V) 1B5 33 1 data input/output B5 1B6 34 1 data input/output B6 VCC 35 supply voltage 1B7 36 1 data input/output B7 1B8 37 1 data input/output B8 1B9 38 1 data input/output B9 GND 39 ground (0 V) 1B10 40 1 data input/output B10 1B11 41 1 data input/output B11 1B12 42 1 data input/output B12 2B12 43 2 data input/output B12 2B11 44 2 data input/output B11 2B10 45 2 data input/output B10 GND 46 ground (0 V) 2B9 47 2 data input/output B9 2B8 48 2 data input/output B8 2B7 49 2 data input/output B7 74ALVT16260_3 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 03 — 20 March 2006 5 of 18 74ALVT16260 Philips Semiconductors 12-bit to 24-bit multiplexed D-type latches; 3-state Table 3. Pin description …continued Symbol Pin Description VCC 50 supply voltage 2B6 51 2 data input/output B6 2B5 52 2 data input/output B5 GND 53 ground (0 V) 2B4 54 2 data input/output B4 LEA2B 55 latch A to 2B enable input OE2B 56 output 2B enable input (active LOW) 7. Functional description 7.1 Function table Table 4. Function table of input B to output A; OE1B = H and OE2B = H [1] Control Input OEA SEL LE1B LE2B 1Bn 2Bn An L H H X H X H L X L L X X X An X H X H H X L L L H [1] X X L X X An X X X X Z H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state; An = HIGH or LOW voltage level one setup time prior to the HIGH-to-LOW LExB transition. Table 5. Function table of input A to output B; OEA = H [1] Control Input Output OE1B OE2B LEA1B LEA2B An 1Bn 2Bn L L H H H H H H H L L L H L L L 2Bn H L H H 2Bn L H H 1Bn H L H L 1Bn L L L X 1Bn 2Bn L X X X active active H X X X active Z L X X X Z active H X X X Z Z L H 74ALVT16260_3 Product data sheet Output © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 03 — 20 March 2006 6 of 18 74ALVT16260 Philips Semiconductors 12-bit to 24-bit multiplexed D-type latches; 3-state [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state; 1Bn = HIGH or LOW voltage level one setup time prior to the HIGH-to-LOW LEA2B transition; 2Bn = HIGH or LOW voltage level one setup time prior to the HIGH-to-LOW LEA1B transition; active = HIGH or LOW voltage level. 8. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Max Unit −0.5 +4.6 V [1] −0.5 +7.0 V [1] −0.5 +7.0 V supply voltage VCC Min VI input voltage VO output voltage output in OFF-state or HIGH-state IIK input clamping current VI < 0 V - −50 mA IOK output clamping current VO < 0 V - −50 mA IO output current output in LOW-state - 128 mA output in HIGH-state - −64 mA −65 +150 °C - 150 °C storage temperature Tstg [2] junction temperature Tj [1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. [2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. 9. Recommended operating conditions Table 7. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit VCC = 2.5 V VCC supply voltage 2.3 - 2.7 V VI input voltage 0 - 5.5 V VIH HIGH-state input voltage 1.7 - - V VIL LOW-state input voltage - - 0.7 V IOH HIGH-state output current - - −8 mA IOL LOW-state output current none - - 8 mA current duty cycle ≤ 50 %; f ≥ 1 kHz - - 24 mA ∆t/∆V input transition rise and fall rate outputs enabled - - 10 ns/V Tamb ambient temperature −40 - +85 °C 3.0 - 3.6 V VCC = 3.3 V VCC supply voltage 74ALVT16260_3 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 03 — 20 March 2006 7 of 18 74ALVT16260 Philips Semiconductors 12-bit to 24-bit multiplexed D-type latches; 3-state Table 7. Recommended operating conditions …continued Symbol Parameter Min Typ Max Unit VI input voltage Conditions 0 - 5.5 V VIH HIGH-state input voltage 2.0 - - V VIL LOW-state input voltage - - 0.8 V IOH HIGH-state output current IOL LOW-state output current - - −32 mA none - - 32 mA current duty cycle ≤ 50 %; f ≥ 1 kHz - - 64 mA ∆t/∆V input transition rise and fall rate outputs enabled - - 10 ns/V Tamb ambient temperature −40 - +85 °C in free air 10. Static characteristics Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Tamb = −40 °C to +85 °C . Symbol Parameter Conditions Min Typ Max −0.85 −1.2 Unit VCC = 2.5 V ± 0.2 V[1] VIK input clamping voltage VCC = 2.3 V; IIK = −18 mA - VOH HIGH-state output voltage VCC = 2.3 V to 3.6 V; IOH = −100 µA VCC − 0.2 VCC - V VCC = 2.3 V; IOH = −8 mA 1.8 2.1 - V VOL LOW-state output voltage VCC = 2.3 V; IOL = 100 µA - 0.07 0.2 V - 0.3 0.5 V - - 0.55 V - 0.1 ±1 µA µA VCC = 2.3 V; IOL = 24 mA VRST power-up LOW-state output voltage ILI input leakage current control pins VCC = 2.7 V; IO = 1 mA; VI = VCC or GND [2] VCC = 2.7 V; VI = VCC or GND VCC = 0 V or 2.7 V; VI = 5.5 V I/O data pins - 0.1 10 VCC = 2.7 V; VI = VCC [3] - 0.1 1 µA VCC = 2.7 V; VI = 0 V [3] - +0.1 −5 µA - 0.1 20 µA ±100 µA VCC = 0 V or 2.7 V; VI = 5.5 V IOFF IHOLD power-off leakage current bus hold current data input VCC = 0 V; VI or VO = 0 V to 4.5 V - 0.1 VCC = 2.3 V; VI = 0.7 V [4] - 90 - µA VCC = 2.3 V; VI = 1.7 V [4] - −10 - µA - 10 125 µA - 1 100 µA - 0.04 0.1 mA - 2.7 4.5 mA - 0.04 0.1 mA IEX external current into output output in HIGH-state when VO > VCC; VO = 5.5 V; VCC = 2.3 V IO(pu/pd) power-up/power-down output current VCC ≤ 1.2 V; VO = 0.5 V to VCC; VI = GND or VCC; OEx = don’t care ICC quiescent supply current VCC = 2.7 V; VI = GND or VCC; IO = 0 A [5] outputs HIGH-state outputs LOW-state outputs disabled 74ALVT16260_3 Product data sheet V [6] © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 03 — 20 March 2006 8 of 18 74ALVT16260 Philips Semiconductors 12-bit to 24-bit multiplexed D-type latches; 3-state Table 8. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Tamb = −40 °C to +85 °C . Symbol Parameter Conditions Min Typ Max Unit - 0.04 0.4 mA ∆ICC additional quiescent supply current per input pin; VCC = 2.3 V to 2.7 V; one input at VCC − 0.6 V, other inputs at VCC or GND Ci input capacitance (control pins) VI = 0 V or VCC - 4 - pF Cio input/output capacitance (I/O pins) VI/O = 0 V or 5.0 V - 9 - pF −0.85 −1.2 [7] VCC = 3.3 V ± 0.3 V[8] VIK input clamping voltage VCC = 3.0 V; IIK = −18 mA - VOH HIGH-state output voltage VCC = 3.0 V to 3.6 V; IOH = −100 µA VCC − 0.2 VCC 2.0 2.3 - V VOL LOW-state output voltage VCC = 3.0 V; IOL = 100 µA [3] - 0.07 0.2 V VCC = 3.0 V; IOL = 16 mA [3] - 0.25 0.4 V VCC = 3.0 V; IOL = 32 mA [3] - 0.3 0.5 V VCC = 3.0 V; IOL = 64 mA [3] - 0.4 0.55 V VCC = 3.6 V; IO = 1 mA; VI = VCC or GND [2] - - 0.55 V VCC = 3.6 V; VI = VCC or GND - 0.1 ±1 µA VCC = 0 V or 3.6 V; VI = 5.5 V - 0.1 10 µA VCC = 3.6 V; VI = VCC [3] - 0.1 1 µA VCC = 3.6 V; VI = 0 V [3] - +0.1 −5 µA VCC = 3.0 V; IOH = −32 mA VRST power-up LOW-state output voltage ILI input leakage current control pins I/O data pins - V V VCC = 0 V or 3.6 V; VI = 5.5 V - 0.1 20 µA IOFF power-off leakage current VCC = 0 V; VI or VO = 0 V to 4.5 V - 0.1 ±100 µA IHOLD bus hold current data input VCC = 3 V; VI = 0.8 V [4] 75 130 - µA VCC = 3 V; VI = 2.0 V [4] −75 −140 - µA VCC = 3.6 V; VI = 0 V to 3.6 V [4] IEX external current into output output in HIGH-state when VO > VCC; VO = 5.5 V; VCC = 3.0 V IO(pu/pd) power-up/power-down output current VCC ≤ 1.2 V; VO = 0.5 V to VCC; VI = GND or VCC; OEx = don’t care ICC quiescent supply current VCC = 3.6 V; VI = GND or VCC; IO = 0 A [9] outputs HIGH-state outputs LOW-state outputs disabled ±500 - - µA - 10 125 µA - 1 ±100 µA - 0.04 0.1 mA - 3.7 6 mA [6] - 0.06 0.1 mA [7] - 0.04 0.4 mA ∆ICC additional quiescent supply current Ci input capacitance (control pins) VI = 0 V or VCC - 4 - pF Cio input/output capacitance (I/O pins) VI/O = 0 V or 5.0 V - 9 - pF per input pin; VCC = 3 V to 3.6 V; one input at VCC − 0.6 V, other inputs at VCC or GND [1] Typical values are measured at VCC = 2.5 V and Tamb = 25 °C. [2] For valid test results, data must not be loaded into the flip-flops (or latches) after applying power. 74ALVT16260_3 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 03 — 20 March 2006 9 of 18 74ALVT16260 Philips Semiconductors 12-bit to 24-bit multiplexed D-type latches; 3-state [3] Unused pins at VCC or GND. [4] This is the bus hold overdrive current required to force the input to the opposite logic state. [5] This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 2.5 V ± 0.2 V a transition time of 100 µs is permitted. This parameter is valid for Tamb = 25 °C only. [6] ICC is measured with outputs pulled up to VCC or pulled down to ground. [7] This is the increase in supply current for each input at the specified voltage level other than VCC or GND. [8] All typical values are measured at VCC = 3.3 V and Tamb = 25 °C. [9] This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 3.3 V ± 0.3 V a transition time of 100 µs is permitted. This parameter is valid for Tamb = 25 °C only. 11. Dynamic characteristics Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 6; Tamb = −40 °C to +85 °C Symbol Parameter Conditions Min Typ Max Unit An to xBn; xBn to An 0.8 2.8 5.2 ns LExB to An; LEAxB to xBn 1.1 3.1 5.6 ns SEL(1Bn) to An 1.2 2.9 4.8 ns 1.6 3.1 5.2 ns An to xBn; xBn to An 1.1 2.7 4.9 ns LExB to An; LEAxB to xBn 0.9 2.8 5.3 ns SEL(1Bn) to An 1.1 2.4 4.5 ns SEL(2Bn) to An 1.2 2.7 4.6 ns 1.8 3.5 5.5 ns 1.3 2.8 4.6 ns 1.8 2.8 4.6 ns 1.0 2.2 3.4 ns 1.0 - - ns 1.0 - - ns 3.3 - - ns VCC = 2.5 V ± 0.2 V tPLH LOW-to-HIGH propagation delay see Figure 3 SEL(2Bn) to An tPHL tPZH HIGH-to-LOW propagation delay see Figure 3 output enable time to HIGH-state see Figure 4 OEA to An; OE1B to 1Bn; OE2B to 2Bn tPZL output enable time to LOW-state see Figure 4 OEA to An; OE1B to 1Bn; OE2B to 2Bn tPHZ output disable time from HIGH-state see Figure 4 OEA to An; OE1B to 1Bn; OE2B to 2Bn tPLZ output disable time from LOW-state see Figure 4 OEA to An; OE1B to 1Bn; OE2B to 2Bn tsu setup time see Figure 5 An to LEAxB; xBn to LExB th hold time see Figure 5 LEAxB to An; LExB to xBn tW pulse width see Figure 5 LExB HIGH; LEAxB HIGH 74ALVT16260_3 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 03 — 20 March 2006 10 of 18 74ALVT16260 Philips Semiconductors 12-bit to 24-bit multiplexed D-type latches; 3-state Table 9. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 6; Tamb = −40 °C to +85 °C Symbol Parameter Conditions Min Typ Max Unit An to xBn; xBn to An 0.7 2.2 3.6 ns LExB to An; LEAxB to xBn 1.0 2.4 4.1 ns SEL(1Bn) to An 1.0 2.2 3.4 ns 0.9 2.3 3.8 ns An to xBn; xBn to An 0.7 2.0 3.4 ns LExB to An; LEAxB to xBn 1.1 2.3 3.9 ns SEL(1Bn) to An 1.0 2.0 3.3 ns SEL(2Bn) to An 1.6 2.1 3.4 ns 1.1 2.7 4.1 ns 1.1 2.1 3.2 ns 2.4 3.4 4.8 ns 2.0 3.0 4.0 ns 1 - - ns 1 - - ns 3.3 - - ns VCC = 3.3 V ± 0.3 V tPLH LOW-to-HIGH propagation delay see Figure 3 SEL(2Bn) to An tPHL tPZH HIGH-to-LOW propagation delay see Figure 3 output enable time to HIGH-state see Figure 4 OEA to An; OE1B to 1Bn; OE2B to 2Bn tPZL output enable time to LOW-state see Figure 4 OEA to An; OE1B to 1Bn; OE2B to 2Bn tPHZ output disable time from HIGH-state see Figure 4 OEA to An; OE1B to 1Bn; OE2B to 2Bn tPLZ output disable time from LOW-state see Figure 4 OEA to An; OE1B to 1Bn; OE2B to 2Bn tsu setup time see Figure 5 An to LEAxB; xBn to LExB th hold time see Figure 5 LEAxB to An; LExB to xBn tW pulse width see Figure 5 LExB HIGH; LEAxB HIGH 74ALVT16260_3 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 03 — 20 March 2006 11 of 18 74ALVT16260 Philips Semiconductors 12-bit to 24-bit multiplexed D-type latches; 3-state 12. Waveforms input VI An, xBn or LExB, LEAxB or 0 V SEL xBn VM VM tPLH tPHL VOH output An, 1Bn or 2Bn VM VM VOL tPLH tPHL VOH output An, 1Bn or 2Bn VM VM 001aae370 VOL Measurement points are given in Table 10. VOL and VOH are typical voltage output drop that occur with the output load. Fig 3. Propagation delay input (An; xBn) to output (xBn; An) or (LExB; LEAxB) to output (An; xBn) or (SELxBn) to output (An) VI input VM OEA, OE1B or OE2B VM tPZL tPLZ 3.5 V output An, 1Bn or 2Bn VM VX VOL tPHZ tPZH VOH output An, 1Bn or 2Bn VY VM 0V disabled enabled disabled 001aae372 Measurement points are given in Table 10. VOL and VOH are typical voltage output drop that occur with the output load. Fig 4. 3-state output disable and enable time Table 10. Measurement points Input Output VM VM VX VY 1.5 V 1.5 V VOL + 0.3 V VOH − 0.3 V 74ALVT16260_3 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 03 — 20 March 2006 12 of 18 74ALVT16260 Philips Semiconductors 12-bit to 24-bit multiplexed D-type latches; 3-state input LE1B, LE2B LEA1B or LEA2B VI VM VM 0V tw tsu th VI input An, 1Bn or 2Bn VM VM 0V 001aae371 Measurement points are given in Table 10. Fig 5. Data setup and hold times VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VEXT VCC VI PULSE GENERATOR RL VO DUT RT CL RL 001aae235 Test data is given in Table 11. Definitions test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = Test voltage for switching times. Fig 6. Load circuitry for switching times Table 11. Test data Input Load VI fi tr, tf CL RL tPLZ, tPZL tPLH, tPHL tPHZ, tPZH 3.0 V ≤ 10 MHz ≤ 2.5 ns 50 pF 500 Ω 7V open GND 74ALVT16260_3 Product data sheet VEXT © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 03 — 20 March 2006 13 of 18 74ALVT16260 Philips Semiconductors 12-bit to 24-bit multiplexed D-type latches; 3-state 13. Package outline SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm SOT371-1 D E A X c y HE v M A Z 29 56 Q A2 A1 A (A 3) θ pin 1 index Lp L 28 1 bp e 0 detail X w M 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2.8 0.4 0.2 2.35 2.20 0.25 0.3 0.2 0.22 0.13 18.55 18.30 7.6 7.4 0.635 10.4 10.1 1.4 1.0 0.6 1.2 1.0 0.25 0.18 0.1 0.85 0.40 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT371-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-118 Fig 7. Package outline SOT371-1 (SSOP56) 74ALVT16260_3 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 03 — 20 March 2006 14 of 18 74ALVT16260 Philips Semiconductors 12-bit to 24-bit multiplexed D-type latches; 3-state TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1 E D A X c HE y v M A Z 56 29 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 detail X 28 w M bp e 2.5 0 5 mm scale DIMENSIONS (mm are the original dimensions). UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z θ mm 1.2 0.15 0.05 1.05 0.85 0.25 0.28 0.17 0.2 0.1 14.1 13.9 6.2 6.0 0.5 8.3 7.9 1 0.8 0.4 0.50 0.35 0.25 0.08 0.1 0.5 0.1 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT364-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Fig 8. Package outline SOT364-1 (TSSOP56) 74ALVT16260_3 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 03 — 20 March 2006 15 of 18 74ALVT16260 Philips Semiconductors 12-bit to 24-bit multiplexed D-type latches; 3-state 14. Abbreviations Table 12. Abbreviations Acronym Description ESD ElectroStatic Discharge DUT Device Under Test 15. Revision history Table 13. Revision history Document ID Release date Data sheet status Change notice Supersedes 74ALVT16260_3 20060320 Product data sheet - 74ALVT16260_2 (9397 750 03337) Modifications: • The format of this data sheet has been redesigned to comply with the new presentation and information standard of Philips Semiconductors. • • Section 2 “Features”: modified ‘JEDEC Std JESD-17’ into ‘JESD78’. Table 9 “Dynamic characteristics”: changed various values. 74ALVT16260_2 (9397 750 03337) 19980130 Product specification - 74ALVT16260_1 74ALVT16260_1 - - - - 74ALVT16260_3 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 03 — 20 March 2006 16 of 18 74ALVT16260 Philips Semiconductors 12-bit to 24-bit multiplexed D-type latches; 3-state 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.semiconductors.philips.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Philips Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Philips Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, Philips Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — Philips Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — Philips Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a Philips Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Philips Semiconductors accepts no liability for inclusion and/or use of Philips Semiconductors products in such equipment or applications and therefore such inclusion and/or use is for the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — Philips Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.semiconductors.philips.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by Philips Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com 74ALVT16260_3 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 03 — 20 March 2006 17 of 18 Philips Semiconductors 74ALVT16260 12-bit to 24-bit multiplexed D-type latches; 3-state 18. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 6 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7 Recommended operating conditions. . . . . . . . 7 Static characteristics. . . . . . . . . . . . . . . . . . . . . 8 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information. . . . . . . . . . . . . . . . . . . . . 17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. For more information, please visit: http://www.semiconductors.philips.com. For sales office addresses, email to: sales.addresses@www.semiconductors.philips.com. Date of release: 20 March 2006 Document identifier: 74ALVT16260_3