74HC164D

74HC164; 74HCT164 8-bit serial-in, parallel-out shift register Rev. 04 — 2 February 2010 Product data sheet 1. General description The 74HC164; 74HCT164 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC164; 74HCT164 are 8-bit edge-triggered shift registers with serial data entry and an output from each of the eight stages. Data is entered serially through one of two inputs (DSA or DSB); either input can be used as an active HIGH enable for data entry through the other input. Both inputs must be connected together or an unused input must be tied HIGH. Data shifts one place to the right on each LOW-to-HIGH transition of the clock (CP) input and enters into Q0, which is the logical AND of the two data inputs (DSA and DSB) that existed one set-up time prior to the rising clock edge. A LOW level on the master reset (MR) input overrides all other inputs and clears the register asynchronously, forcing all outputs LOW. 2. Features Input levels: For 74HC164: CMOS level For 74HCT164: TTL level Gated serial data inputs Asynchronous master reset Complies with JEDEC standard no. 7A ESD protection: HBM JESD22-A114F exceeds 2 000 V MM JESD22-A115-A exceeds 200 V. Multiple package options Specified from −40 °C to +85 °C and −40 °C to +125 °C. NXP Semiconductors 74HC164; 74HCT164 8-bit serial-in, parallel-out shift register 3. Ordering information Table 1. Ordering information Package Temperature range 74HC164N 74HCT164N 74HC164D 74HCT164D 74HC164DB 74HCT164DB 74HC164PW 74HCT164PW 74HC164BQ 74HCT164BQ −40 °C to +125 °C DHVQFN14 −40 °C to +125 °C TSSOP14 −40 °C to +125 °C SSOP14 −40 °C to +125 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm plastic shrink small outline package; 14 leads; body width 5.3 mm plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT108-1 SOT337-1 SOT402-1 −40 °C to +125 °C Name DIP14 Description plastic dual in-line package; 14 leads (300 mil) Version SOT27-1 Type number plastic dual in-line compatible thermal enhanced very SOT762-1 thin quad flat package; no leads; 14 terminals; body 2.5 × 3 × 0.85 mm 4. Functional diagram SRG8 8 9 1 2 C1/ R 3 4 & 1D DSA DSB 3 1 2 4 5 6 10 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 001aac424 5 6 10 11 12 13 CP MR 8 9 11 12 13 001aac423 Fig 1. Logic symbol Fig 2. IEC logic symbol DSA DSB CP MR 1 2 8 9 3 4 5 6 10 11 12 13 8-BIT SERIAL−IN/PARALLEL−OUT SHIFT REGISTER Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 001aac425 Fig 3. 74HC_HCT164_4 Logic diagram © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 2 February 2010 2 of 20 NXP Semiconductors 74HC164; 74HCT164 8-bit serial-in, parallel-out shift register DSA D DSB Q D Q D Q D Q D Q D Q D Q D Q CP FF1 RD CP FF2 RD CP FF3 RD CP FF4 RD CP FF5 RD CP FF6 RD CP FF7 RD CP FF8 RD CP MR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 001aac616 Fig 4. Functional diagram 5. Pinning information 5.1 Pinning 74HC164 74HCT164 DSA 2 3 4 5 6 7 GND CP 8 GND(1) 1 terminal 1 index area DSB 14 VCC 13 Q7 12 Q6 11 Q5 10 Q4 9 8 001aal390 74HC164 74HCT164 DSA DSB Q0 Q1 Q2 Q3 GND 1 2 3 4 5 6 7 14 VCC 13 Q7 12 Q6 11 Q5 10 Q4 9 MR Q0 Q1 Q2 Q3 MR CP 001aal391 Transparent top view (1) The substrate is attached to this pad using conductive die attach material. It can not be used as supply pin or input. It is recommended that no connection is made at all. Fig 5. Pin configuration DIP14, SO14, (T)SSOP14 Fig 6. Pin configuration DHVQFN14 74HC_HCT164_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 2 February 2010 3 of 20 NXP Semiconductors 74HC164; 74HCT164 8-bit serial-in, parallel-out shift register 5.2 Pin description Table 2. Symbol DSA DSB Q0 to Q7 GND CP MR VCC Pin description Pin 1 2 3, 4, 5, 6, 10, 11, 12, 13 7 8 9 14 Description data input data input output ground (0 V) clock input (LOW-to-HIGH, edge-triggered) master reset input (active LOW) positive supply voltage 6. Functional description Table 3. Operating modes Reset (clear) Shift Function table[1] Input MR L H H H H [1] H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition L = LOW voltage level I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition q = lower case letters indicate the state of the referenced input one set-up time prior to the LOW-to-HIGH clock transition ↑ = LOW-to-HIGH clock transition Output CP X ↑ ↑ ↑ ↑ DSA X l l h h DSB X l h l h Q0 L L L L H Q1 to Q7 L to L q0 to q6 q0 to q6 q0 to q6 q0 to q6 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK IOK IO ICC IGND Tstg Parameter supply voltage input clamping current output clamping current output current supply current ground current storage temperature VI < −0.5 V or VI > VCC + 0.5 V VO < −0.5 V or VO > VCC + 0.5 V −0.5 V < VO < VCC + 0.5 V [1] [1] Conditions Min −0.5 −50 −65 Max +7 ±20 ±20 ±25 50 +150 Unit V mA mA mA mA mA °C 74HC_HCT164_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 2 February 2010 4 of 20 NXP Semiconductors 74HC164; 74HCT164 8-bit serial-in, parallel-out shift register Table 4. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Ptot Parameter total power dissipation DIP14 package SO14, (T)SSOP14 and DHVQFN14 packages [1] [2] Conditions [2] Min - Max 750 500 Unit mW mW The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For DIP14 package: Ptot derates linearly with 12 mW/K above 70 °C. For SO14 package: Ptot derates linearly with 8 mW/K above 70 °C. For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 °C. For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 °C. 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter VCC VI VO Tamb Δt/ΔV supply voltage input voltage output voltage ambient temperature input transition rise and fall rate VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Conditions 74HC164 Min 2.0 0 0 −40 Typ 5.0 +25 1.67 Max 6.0 VCC VCC +125 625 139 83 74HCT164 Min 4.5 0 0 −40 Typ 5.0 +25 1.67 Max 5.5 VCC VCC +125 139 V V V °C ns/V ns/V ns/V Unit 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 74HC164 VIH HIGH-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VIL LOW-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V 1.5 3.15 4.2 1.2 2.4 3.2 0.8 2.1 2.8 0.5 1.35 1.8 1.5 3.15 4.2 0.5 1.35 1.8 1.5 3.15 4.2 0.5 1.35 1.8 V V V V V V Conditions Min 25 °C Typ Max −40 °C to +85 °C −40 °C to +125 °C Unit Min Max Min Max 74HC_HCT164_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 2 February 2010 5 of 20 NXP Semiconductors 74HC164; 74HCT164 8-bit serial-in, parallel-out shift register Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VOH HIGH-level output voltage Conditions Min VI = VIH or VIL IO = −20 μA; VCC = 2.0 V IO = −20 μA; VCC = 4.5 V IO = −20 μA; VCC = 6.0 V IO = −4.0 mA; VCC = 4.5 V IO = −5.2 mA; VCC = 6.0 V VOL LOW-level output voltage VI = VIH or VIL IO = 20 μA; VCC = 2.0 V IO = 20 μA; VCC = 4.5 V IO = 20 μA; VCC = 6.0 V IO = 4.0 mA; VCC = 4.5 V IO = 5.2 mA; VCC = 6.0 V II ICC CI input leakage current supply current input capacitance HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V VI = VIH or VIL; VCC = 4.5 V IO = −20 μA IO = −4.0 mA VOL LOW-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 μA; VCC = 4.5 V IO = 5.2 mA; VCC = 6.0 V II ICC ΔICC input leakage current supply current additional supply current VI = VCC or GND; VCC = 6.0 V VI = VCC or GND; IO = 0 A; VCC = 6.0 V per input pin; VI = VCC − 2.1 V; IO = 0 A; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V 0 0.15 100 0.1 0.26 ±0.1 8 360 0.1 0.33 ±1 80 450 0.1 0.4 ±1 160 490 V V μA μA μA 4.4 3.98 4.5 4.32 4.4 3.84 4.4 3.7 V V VI = VCC or GND; VCC = 6.0 V VI = VCC or GND; IO = 0 A; VCC = 6.0 V 0 0 0 0.15 0.16 3.5 0.1 0.1 0.1 0.26 0.26 ±0.1 8.0 0.1 0.1 0.1 0.33 0.33 ±1 80 0.1 0.1 0.1 0.4 0.4 ±1 160 V V V V V μA μA pF 1.9 4.4 5.9 3.98 5.48 2.0 4.5 6.0 4.32 5.81 1.9 4.4 5.9 3.84 5.34 1.9 4.4 5.9 3.7 5.2 V V V V V 25 °C Typ Max −40 °C to +85 °C −40 °C to +125 °C Unit Min Max Min Max 74HCT164 VIH VIL VOH 2.0 1.6 1.2 0.8 2.0 0.8 2.0 0.8 V V CI input capacitance - 3.5 - - - - - pF 74HC_HCT164_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 2 February 2010 6 of 20 NXP Semiconductors 74HC164; 74HCT164 8-bit serial-in, parallel-out shift register 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; tr = tf = 6 ns; CL = 50 pF; test circuit see Figure 10; unless otherwise specified Symbol Parameter 74HC164 tpd propagation delay CP to Qn; see Figure 7 VCC = 2.0 V VCC = 4.5 V VCC = 5.0 V; CL = 15 pF VCC = 6.0 V tPHL HIGH to LOW propagation delay MR to Qn; see Figure 8 VCC = 2.0 V VCC = 4.5 V VCC = 5.0 V; CL = 15 pF VCC = 6.0 V tt transition time see Figure 7 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tW pulse width CP HIGH or LOW; see Figure 7 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V MR LOW; see Figure 8 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V trec recovery time MR to CP; see Figure 8 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tsu set-up time DSA, and DSB to CP; see Figure 9 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V th hold time DSA, and DSB to CP; see Figure 9 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V 74HC_HCT164_4 Conditions Min [1] 25 °C Typ Max −40 °C to +85 °C Min Max −40 °C to +125 °C Unit Min Max [2] 41 15 12 12 39 14 11 11 19 7 6 170 34 29 140 28 24 75 15 13 - 215 43 37 175 35 30 95 19 16 - 255 51 43 210 42 36 110 22 19 ns ns ns ns ns ns ns ns ns ns ns - 80 16 14 60 12 10 60 12 10 14 5 4 17 6 5 17 6 5 - 100 20 17 75 15 13 75 15 13 - 120 24 20 90 18 15 90 18 15 - ns ns ns ns ns ns ns ns ns 60 12 10 8 3 2 - 75 15 13 - 90 18 15 - ns ns ns +4 +4 +4 −6 −2 −2 - 4 4 4 - 4 4 4 - ns ns ns © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 2 February 2010 7 of 20 NXP Semiconductors 74HC164; 74HCT164 8-bit serial-in, parallel-out shift register Table 7. Dynamic characteristics GND = 0 V; tr = tf = 6 ns; CL = 50 pF; test circuit see Figure 10; unless otherwise specified Symbol Parameter fmax maximum frequency Conditions Min for Cp, see Figure 7 VCC = 2.0 V VCC = 4.5 V VCC = 5.0 V; CL = 15 pF VCC = 6.0 V CPD power dissipation capacitance propagation delay per package; VI = GND to VCC [3] 25 °C Typ Max 23 71 78 85 40 - −40 °C to +85 °C Min 5 24 28 Max - −40 °C to +125 °C Unit Min 4 20 24 Max MHz MHz MHz MHz pF 6 30 35 - 74HCT164 tpd CP to Qn; see Figure 7 VCC = 4.5 V VCC = 5.0 V; CL = 15 pF tPHL HIGH to LOW propagation delay transition time pulse width MR to Qn; see Figure 8 VCC = 4.5 V VCC = 5.0 V; CL = 15 pF see Figure 7 VCC = 4.5 V tW CP HIGH or LOW; see Figure 7 VCC = 4.5 V MR LOW; see Figure 8 VCC = 4.5 V trec tsu recovery time set-up time MR to CP; see Figure 8 VCC = 4.5 V DSA, and DSB to CP; see Figure 9 VCC = 4.5 V th hold time DSA, and DSB to CP; see Figure 9 VCC = 4.5 V fmax maximum frequency for Cp, see Figure 7 VCC = 4.5 V VCC = 5.0 V; CL = 15 pF 27 55 61 22 18 MHz MHz +4 −2 4 4 ns 12 6 15 18 ns 16 7 20 24 ns 18 10 23 27 ns 18 7 23 27 ns [2] [1] - 17 14 19 16 7 36 38 15 - 45 48 19 - 54 57 22 ns ns ns ns ns tt 74HC_HCT164_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 2 February 2010 8 of 20 NXP Semiconductors 74HC164; 74HCT164 8-bit serial-in, parallel-out shift register Table 7. Dynamic characteristics GND = 0 V; tr = tf = 6 ns; CL = 50 pF; test circuit see Figure 10; unless otherwise specified Symbol Parameter CPD power dissipation capacitance Conditions Min per package; VI = GND to VCC − 1.5 V [3] 25 °C Typ Max 40 - −40 °C to +85 °C Min Max - −40 °C to +125 °C Unit Min Max pF [1] [2] [3] tpd is the same as tPHL and tPLH. tt is the same as tTHL and tTLH. CPD is used to determine the dynamic power dissipation (PD in μW): PD = CPD × VCC2 × fi × N + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; ∑ (CL × VCC2 × fo) = sum of outputs. 1/fmax VI CP input GND VM tW tPHL VOH Qn output VOL VY VM VX tPLH tTHL tTLH 001aal392 (1) Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, the output transition times and the maximum clock frequency Measurement points Input VM 0.5VCC 1.3 V Output VM 0.5VCC 1.3 V VX 0.1VCC 0.1VCC VY 0.9VCC 0.9VCC Table 8. Type 74HC164 74HCT164 74HC_HCT164_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 2 February 2010 9 of 20 NXP Semiconductors 74HC164; 74HCT164 8-bit serial-in, parallel-out shift register VI MR input GND tW VI CP input GND tPHL VOH Qn output VOL VM 001aac427 VM frec VM (1) Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 8. Waveforms showing the master reset (MR) pulse width, the master reset to output (Qn) propagation delays and the master reset to clock (CP) removal time VI CP input GND t su th VI Dn input GND VM t su th VM VOH Qn output VOL 001aac428 VM (1) Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. The shaded areas indicate when the input is permitted to change for predictable output performance. Fig 9. Waveforms showing the data set-up and hold times for Dn inputs 74HC_HCT164_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 2 February 2010 10 of 20 NXP Semiconductors 74HC164; 74HCT164 8-bit serial-in, parallel-out shift register VI negative pulse GND tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VCC G VI VO VM VI positive pulse GND VM DUT RT CL 001aah768 Test data is given in Table 9. Definitions test circuit: RT = termination resistance should be equal to output impedance Zo of the pulse generator. CL = load capacitance including jig and probe capacitance. Fig 10. Test circuit for measuring switching times Table 9. Type 74HC164 74HCT164 Test data Input VI VCC 3.0 V tr, tf 6.0 ns 6.0 ns Load CL 15 pF, 50 pF 15 pF, 50 pF tPLH, tPHL tPLH, tPHL Test 74HC_HCT164_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 2 February 2010 11 of 20 NXP Semiconductors 74HC164; 74HCT164 8-bit serial-in, parallel-out shift register 11. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 D seating plane ME A2 A L A1 c Z e b1 b 14 8 MH wM (e 1) pin 1 index E 1 7 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.02 A2 max. 3.2 0.13 b 1.73 1.13 0.068 0.044 b1 0.53 0.38 0.021 0.015 c 0.36 0.23 0.014 0.009 D (1) 19.50 18.55 0.77 0.73 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.1 e1 7.62 0.3 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 2.2 0.087 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT27-1 REFERENCES IEC 050G04 JEDEC MO-001 JEITA SC-501-14 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-13 Fig 11. Package outline SOT27-1 (DIP14) 74HC_HCT164_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 2 February 2010 12 of 20 NXP Semiconductors 74HC164; 74HCT164 8-bit serial-in, parallel-out shift register SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE vMA Z 14 8 Q A2 A1 pin 1 index (A 3) θ Lp L A 1 7 e bp wM detail X 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 8.75 8.55 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 0.028 0.024 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3 θ o 0.010 0.057 inches 0.069 0.004 0.049 0.019 0.0100 0.35 0.014 0.0075 0.34 0.244 0.039 0.041 0.228 0.016 0.028 0.004 0.012 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT108-1 REFERENCES IEC 076E06 JEDEC MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 12. Package outline SOT108-1 (SO14) 74HC_HCT164_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 2 February 2010 13 of 20 NXP Semiconductors 74HC164; 74HCT164 8-bit serial-in, parallel-out shift register SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 D E A X c y HE vM A Z 14 8 Q A2 A1 pin 1 index θ Lp L 1 7 (A 3) A detail X wM e bp 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT337-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 6.4 6.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.4 0.9 θ 8 o 0 o ISSUE DATE 99-12-27 03-02-19 Fig 13. Package outline SOT337-1 (SSOP14) 74HC_HCT164_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 2 February 2010 14 of 20 NXP Semiconductors 74HC164; 74HCT164 8-bit serial-in, parallel-out shift register TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 D E A X c y HE vMA Z 14 8 Q A2 pin 1 index A1 θ Lp L (A 3) A 1 e bp 7 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.72 0.38 θ 8 o 0 o Fig 14. Package outline SOT402-1 (TSSOP14) 74HC_HCT164_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 2 February 2010 15 of 20 NXP Semiconductors 74HC164; 74HCT164 8-bit serial-in, parallel-out shift register DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm D B A A A1 E c terminal 1 index area detail X terminal 1 index area e 2 L e1 b 6 vMCAB wM C y1 C C y 1 Eh 14 7 e 8 13 Dh 0 9 X 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 3.1 2.9 Dh 1.65 1.35 E (1) 2.6 2.4 Eh 1.15 0.85 e 0.5 e1 2 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT762-1 REFERENCES IEC --JEDEC MO-241 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 15. Package outline SOT762-1 (DHVQFN14) 74HC_HCT164_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 2 February 2010 16 of 20 NXP Semiconductors 74HC164; 74HCT164 8-bit serial-in, parallel-out shift register 12. Abbreviations Table 10. Acronym CMOS DUT ESD HBM LSTTL MM TTL Abbreviations Description Complementary Metal-Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Low-power Schottky Transistor-Transistor Logic Machine Model Transistor-Transistor Logic 13. Revision history Table 11. Revision history Release date 20100202 Data sheet status Product data sheet Change notice Supersedes 74HC_HCT164_3 Document ID 74HC_HCT164_4 Modifications: • • • • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Added type number 74HC164BQ (DHVQFN14 / SOT762-1 package). For type numbers 74HC164D and 74HCT164D: sot number SOT108-2 changed to SOT108-1. Product data sheet Product specification 74HC_HCT164_ CNV_2 - 74HC_HCT164_3 74HC_HCT164_CNV_2 20050404 19901201 74HC_HCT164_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 2 February 2010 17 of 20 NXP Semiconductors 74HC164; 74HCT164 8-bit serial-in, parallel-out shift register 14. Legal information 14.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 14.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Non-automotive qualified products — Unless the data sheet of an NXP Semiconductors product expressly states that the product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. 14.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 14.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 74HC_HCT164_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 2 February 2010 18 of 20 NXP Semiconductors 74HC164; 74HCT164 8-bit serial-in, parallel-out shift register 15. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74HC_HCT164_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 2 February 2010 19 of 20 NXP Semiconductors 74HC164; 74HCT164 8-bit serial-in, parallel-out shift register 16. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 14.1 14.2 14.3 14.4 15 16 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contact information. . . . . . . . . . . . . . . . . . . . . 19 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 2 February 2010 Document identifier: 74HC_HCT164_4