HEF4027BT

HEF4027B Dual JK flip-flop Rev. 05 — 10 November 2008 Product data sheet 1. General description The HEF4027B is a edge-triggered dual JK flip-flop which features independent set-direct (SD), clear-direct (CD), clock (CP) inputs and outputs (Q, Q). Data is accepted when CP is LOW, and transferred to the output on the positive-going edge of the clock. The active HIGH asynchronous clear-direct (CD) and set-direct (SD) inputs are independent and override the J, K, and CP inputs. The outputs are buffered for best system performance. Schmitt trigger action makes the clock input highly tolerant of slower rise and fall times. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. It is also suitable for use over the full industrial (−40 °C to +85 °C) temperature range. 2. Features I I I I I I Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Operates across the full industrial temperature range −40 °C to +85 °C Complies with JEDEC standard JESD 13-B ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V 3. Applications I Registers I Counters I Control circuits 4. Ordering information Table 1. Ordering information Tamb from −40 °C to +85 °C. Type number HEF4027BP HEF4027BT Package Name DIP16 SO16 Description plastic dual in-line package; 16-leads (300 mil) plastic small outline package; 16 leads; body width 3.9 mm Version SOT38-4 SOT109-1 NXP Semiconductors HEF4027B Dual JK flip-flop 5. Functional diagram 9 FF 1 1SD 10 13 11 1J 1CP 1K 1CD 1Q 1Q 15 14 12 7 FF 2 2SD 6 3 5 2J 2CP 2K 2CD 4 001aae593 2Q 2Q 1 2 Fig 1. Functional diagram CP C C C C Q J C C C C Q K CD SD 001aae595 C C Fig 2. Logic diagram of one flip-flop HEF4027B_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 10 November 2008 2 of 13 NXP Semiconductors HEF4027B Dual JK flip-flop 6. Pinning information 6.1 Pinning HEF4027B 2Q 2Q 2CP 2CD 2K 2J 2SD VSS 1 2 3 4 5 6 7 8 001aae594 16 VDD 15 1Q 14 1Q 13 1CP 12 1CD 11 1K 10 1J 9 1SD Fig 3. Pin configuration 6.2 Pin description Table 2. Symbol VSS 1SD, 2SD 1J, 2J 1K, 2K 1CD, 2CD 1CP, 2CP 1Q, 2Q 1Q, 2Q VDD Pin description Pin 8 9, 7 10, 6 11, 5 12, 4 13, 3 14, 2 15, 1 16 Description ground supply voltage asynchronous set-direct input (active HIGH) synchronous input synchronous input asynchronous clear-direct input (active HIGH) clock input (LOW-to-HIGH edge-triggered) complement output true output supply voltage 7. Functional description Table 3. Inputs nSD H L H nCD L H H nCP X X X nJ X X X nK X X X Function table[1] Outputs nQ H L H nQ L H H HEF4027B_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 10 November 2008 3 of 13 NXP Semiconductors HEF4027B Dual JK flip-flop Table 3. Inputs nSD L L L L [1] Function table[1] …continued Outputs nCD L L L L nCP ↑ ↑ ↑ ↑ nJ L H L H nK L L H H nQ no change H L nQ nQ no change L H nQ H = HIGH voltage level; L = LOW voltage level; X = don’t care.; ↑ = positive-going transition. 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD IIK VI IOK II/O IDD Tstg Tamb Ptot Parameter supply voltage input clamping current input voltage output clamping current input/output current supply current storage temperature ambient temperature total power dissipation in free air Tamb −40 °C to +125 °C DIP16 package SO16 package P [1] [2] [1] [2] Conditions VI < 0.5 V or VI > VDD + 0.5 V VO < 0.5 V or VO > VDD + 0.5 V Min −0.5 −0.5 −65 −40 - Max +18 ±10 VDD + 0.5 ±10 ±10 50 +150 +85 750 500 100 Unit V mA V mA mA mA °C °C mW mW mW power dissipation per output For DIP16 package: Ptot derates linearly with 12 mW/K above 70 °C. For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C. 9. Recommended operating conditions Table 5. Symbol VDD VI Tamb ∆t/∆V Recommended operating conditions Parameter supply voltage input voltage ambient temperature input transition rise and fall rate in free air VDD = 5 V VDD = 10 V VDD = 15 V Conditions Min 3 0 −40 Max 15 VDD +85 3.75 0.5 0.08 Unit V V °C ns/V ns/V ns/V HEF4027B_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 10 November 2008 4 of 13 NXP Semiconductors HEF4027B Dual JK flip-flop 10. Static characteristics Table 6. Static characteristics VSS = 0 V; VI = VSS or VDD; unless otherwise specified. Symbol VIH Parameter HIGH-level input voltage Conditions |IO| < 1 µA VDD 5V 10 V 15 V VIL LOW-level input voltage |IO| < 1 µA 5V 10 V 15 V VOH HIGH-level output voltage |IO| < 1 µA 5V 10 V 15 V VOL LOW-level output voltage |IO| < 1 µA 5V 10 V 15 V IOH HIGH-level output current VO = 2.5 V VO = 4.6 V VO = 9.5 V VO = 13.5 V IOL LOW-level output current VO = 0.4 V VO = 0.5 V VO = 1.5 V II IDD input leakage current supply current IO = 0 A 5V 5V 10 V 15 V 5V 10 V 15 V 15 V 5V 10 V 15 V CI input capacitance Tamb = −40 °C Min 3.5 7.0 11.0 4.95 9.95 14.95 −1.7 −0.52 −1.3 −3.6 0.52 1.3 3.6 Max 1.5 3.0 4.0 0.05 0.05 0.05 ±0.3 4.0 8.0 16.0 Tamb = 25 °C Min 3.5 7.0 11.0 4.95 9.95 14.95 −1.4 −0.44 −1.1 −3.0 0.44 1.1 3.0 Max 1.5 3.0 4.0 0.05 0.05 0.05 ±0.3 4.0 8.0 16.0 7.5 Tamb = 85 °C Unit Min 3.5 7.0 11.0 4.95 9.95 14.95 −1.1 −0.36 −0.9 −2.4 0.36 0.9 2.4 Max 1.5 3.0 4.0 0.05 0.05 0.05 ±1.0 30 60 120 V V V V V V V V V V V V mA mA mA mA mA mA mA µA µA µA µA pF HEF4027B_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 10 November 2008 5 of 13 NXP Semiconductors HEF4027B Dual JK flip-flop 11. Dynamic characteristics Table 7. Dynamic characteristics VSS = 0 V; Tamb = 25 °C; for test circuit see Figure 7; unless otherwise specified. Symbol Parameter tPHL HIGH to LOW propagation delay Conditions CP → Q, Q; see Figure 4 VDD 5V 10 V 15 V CD → Q; see Figure 4 5V 10 V 15 V SD → Q; see Figure 4 5V 10 V 15 V tPLH LOW to HIGH propagation delay CP → Q, Q; see Figure 4 5V 10 V 15 V CD → Q; see Figure 4 5V 10 V 15 V SD → Q; see Figure 4 5V 10 V 15 V tt transition time see Figure 4 5V 10 V 15 V tsu set-up time J, K → CP; see Figure 5 5V 10 V 15 V th hold time J, K → CP; see Figure 5 5V 10 V 15 V tW pulse width CP LOW; minimum width see Figure 5 SD, CD HIGH; minimum width see Figure 6 trec recovery time SD, CD inputs; see Figure 6 5V 10 V 15 V 5V 10 V 15 V 5V 10 V 15 V [2] Extrapolation formula[1] 78 ns + (0.55 ns/pF)CL 29 ns + (0.23 ns/pF)CL 22 ns + (0.16 ns/pF)CL 93 ns + (0.55 ns/pF)CL 33 ns + (0.23 ns/pF)CL 27 ns + (0.16 ns/pF)CL 113 ns + (0.55 ns/pF)CL 44 ns + (0.23 ns/pF)CL 32 ns + (0.16 ns/pF)CL 58 ns + (0.55 ns/pF)CL 27 ns + (0.23 ns/pF)CL 22 ns + (0.16 ns/pF)CL 48 ns + (0.55 ns/pF)CL 24 ns + (0.23 ns/pF)CL 17 ns + (0.16 ns/pF)CL 43 ns + (0.55 ns/pF)CL 19 ns + (0.23 ns/pF)CL 17 ns + (0.16 ns/pF)CL 10 ns + (1.00 ns/pF)CL 9 ns + (0.42 ns/pF)CL 6 ns + (0.28 ns/pF)CL Min 50 30 20 25 20 15 80 30 24 90 40 30 +20 +15 +10 Typ 105 40 30 120 45 35 140 55 40 85 35 30 75 35 25 70 30 25 60 30 20 25 10 5 0 0 5 40 15 12 45 20 15 −15 −10 −5 Max 210 80 60 240 90 70 280 110 80 170 70 60 150 70 50 140 60 50 120 60 40 - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns HEF4027B_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 10 November 2008 6 of 13 NXP Semiconductors HEF4027B Dual JK flip-flop Table 7. Dynamic characteristics …continued VSS = 0 V; Tamb = 25 °C; for test circuit see Figure 7; unless otherwise specified. Symbol Parameter fmax maximum frequency Conditions CP input; J = K = HIGH; see Figure 5 VDD 5V 10 V 15 V Extrapolation formula[1] Min 4 12 15 Typ 8 25 30 Max Unit MHz MHz MHz [1] [2] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF). tt is the same as tTLH and tTHL. Table 8. Dynamic power dissipation PD PD can be calculated from the formulas shown. VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C. Symbol PD Parameter dynamic power dissipation VDD 5V 10 V 15 V Typical formula for PD (µW) PD = 900 × fi + Σ(fo × CL) × VDD 2 Where: fi = input frequency in MHz; fo = output frequency in MHz; 2 PD = 4500 × fi + Σ(fo × CL) × VDD2 PD = 13200 × fi + Σ(fo × CL) × VDD CL = output load capacitance in pF; VDD = supply voltage in V; Σ(CL × fo) = sum of the outputs. 12. Waveforms tr VI SD, CD or CP INPUT 0V 90 % VM 10 % tPLH VOH Q or Q OUTPUT VOL VM 10 % tTLH tTHL 001aah863 90 % tPHL tf VOH and VOL are typical output voltages levels that occur with the output load. Measurement points are given in Table 9. Fig 4. Waveforms showing rise, fall and transition times and propagation delays 1/fmax tW CP INPUT VM th J,K INPUT VM tsu 001aae596 Measurement points are given in Table 9. Fig 5. HEF4027B_5 Waveforms showing set-up and hold times and minimum clock pulse width © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 10 November 2008 7 of 13 NXP Semiconductors HEF4027B Dual JK flip-flop VI SD INPUT 0V VM tW VI CD INPUT 0V trec VI CP INPUT 0V VM VM tW trec VOH Q OUTPUT VOL 001aae597 VOH and VOL are typical output voltages levels that occur with the output load. Measurement points are given in Table 9. Fig 6. Table 9. VDD Waveforms showing pulse widths and recovery times Measurement points Input VM 0.5VDD Output VM 0.5VDD Supply voltage 5 V to 15 V VDD VI G RT VO DUT CL 001aag182 Test data is given in Table 10. Definitions for test circuit: DUT = Device Under Test. CL = load capacitance including jig and probe capacitance. RT = termination resistance should be equal to the output impedance Zo of the pulse generator. Fig 7. Table 10. VDD Test circuit Test data Input VI VSS or VDD tr, tf ≤ 20 ns Load CL 50 pF Supply voltage 5 V to 15 V HEF4027B_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 10 November 2008 8 of 13 NXP Semiconductors HEF4027B Dual JK flip-flop 13. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 D seating plane ME A2 A L A1 c Z e b1 b 16 9 b2 MH wM (e 1) pin 1 index E 1 8 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.02 A2 max. 3.2 0.13 b 1.73 1.30 0.068 0.051 b1 0.53 0.38 0.021 0.015 b2 1.25 0.85 0.049 0.033 c 0.36 0.23 0.014 0.009 D (1) 19.50 18.55 0.77 0.73 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.1 e1 7.62 0.3 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 0.76 0.03 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT38-4 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 95-01-14 03-02-13 Fig 8. HEF4027B_5 Package outline SOT38-4 (DIP16) © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 10 November 2008 9 of 13 NXP Semiconductors HEF4027B Dual JK flip-flop SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE vMA Z 16 9 Q A2 pin 1 index θ Lp 1 e bp 8 wM L detail X A1 (A 3) A 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3 θ 0.010 0.057 0.069 0.004 0.049 0.019 0.0100 0.39 0.014 0.0075 0.38 0.244 0.041 0.228 0.028 0.004 0.012 8 o 0 o Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07 JEDEC MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 9. HEF4027B_5 Package outline SOT109-1 (SO16) © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 10 November 2008 10 of 13 NXP Semiconductors HEF4027B Dual JK flip-flop 14. Abbreviations Table 11. Acronym DUT ESD HBM MM Abbreviations Description Device Under Test ElectroStatic Discharge Human Body Model Machine Model 15. Revision history Table 12. Revision history Release date 20081110 Data sheet status Product data sheet Change notice Supersedes HEF4027B_4 Document ID HEF4027B_5 Modifications: • • • Maximum Tamb changed to 85 °C and Tamb = 125 °C parameter data removed throughout. Section 1 “General description” temperature range statement modified. Section 10 “Static characteristics” IDD, IOL, IOH and II values revised. Product specification Product specification Product specification HEF4027B_CNV_3 HEF4027B_CNV_2 - HEF4027B_4 HEF4027B_CNV_3 HEF4027B_CNV_2 20080703 19950101 19950101 HEF4027B_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 10 November 2008 11 of 13 NXP Semiconductors HEF4027B Dual JK flip-flop 16. Legal information 16.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com HEF4027B_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 10 November 2008 12 of 13 NXP Semiconductors HEF4027B Dual JK flip-flop 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Contact information. . . . . . . . . . . . . . . . . . . . . 12 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 10 November 2008 Document identifier: HEF4027B_5