HEF4030BT-Q100J

HEF4030B-Q100 Quad 2-input EXCLUSIVE-OR gate Rev. 2 — 7 December 2021 Product data sheet 1. General description The HEF4030B-Q100 is a quad 2-input EXCLUSIVE-OR gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VDD. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits • • • • • • • • • Automotive product qualification in accordance with AEC-Q100 (Grade 1) • Specified from -40 °C to +85 °C and from -40 °C to +125 °C Wide supply voltage range from 3.0 V to 15.0 V CMOS low power dissipation High noise immunity Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics ESD protection: • MIL-STD-833, method 3015 exceeds 2000 V • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω) Complies with JEDEC standard JESD 13-B 3. Ordering information Table 1. Ordering information Type number Package HEF4030BT-Q100 Temperature range Name Description Version -40 °C to +125 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 HEF4030B-Q100 Nexperia Quad 2-input EXCLUSIVE-OR gate 4. Functional diagram 1 1A 2 1B 1Y 3 5 2A 6 2B 2Y 4 8 3A 9 3B 3Y 10 12 4A 13 4B 4Y 11 A Y B aaa-009541 Fig. 1. Functional diagram Fig. 2. mna788 Logic diagram (one gate) 5. Pinning information 5.1. Pinning HEF4030B 1A 1 14 VDD 1B 2 13 4B 1Y 3 12 4A 2Y 4 11 4Y 2A 5 10 3Y 2B 6 9 3B VSS 7 8 3A aaa-009542 Fig. 3. Pin configuration SOT108-1( SO14) 5.2. Pin description Table 2. Pin description Symbol Pin Description 1A, 2A, 3A, 4A 1, 5, 8, 12 data input 1B, 2B, 3B, 4B 2, 6, 9, 13 data input 1Y, 2Y, 3Y, 4Y 3, 4, 10, 11 data output VSS 7 ground (0 V) VDD 14 supply voltage HEF4030B_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 7 December 2021 © Nexperia B.V. 2021. All rights reserved 2 / 10 HEF4030B-Q100 Nexperia Quad 2-input EXCLUSIVE-OR gate 6. Functional description Table 3. Functional table H = HIGH voltage level; L = LOW voltage level Output Input nA nB nY L L L L H H H L H H H L 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground). Symbol Parameter VDD supply voltage IIK input clamping current VI input voltage IOK output clamping current II/O IDD Tstg Conditions VI < -0.5 V or VI > VDD + 0.5 V Min Max Unit -0.5 +18 V - ±10 mA -0.5 - ±10 mA input/output current - ±10 mA supply current - 50 mA storage temperature -65 +150 °C Tamb ambient temperature -40 +125 °C Ptot total power dissipation Tamb = -40 °C to + 125 °C - 500 mW P power dissipation per output - 100 mW [1] VO < -0.5 V or VO > VDD + 0.5 V VDD + 0.5 V [1] For SOT108-1 (SO14) package: Ptot derates linearly with 10.1 mW/K above 100 °C. 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions Min Typ Max VDD supply voltage 3 - 15 V VI input voltage 0 - VDD V Tamb ambient temperature in free air -40 - +125 °C Δt/ΔV input transition rise and fall rate VDD = 5 V - - 3.75 μs/V VDD = 10 V - - 0.5 μs/V VDD = 15 V - - 0.08 μs/V HEF4030B_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 7 December 2021 © Unit Nexperia B.V. 2021. All rights reserved 3 / 10 HEF4030B-Q100 Nexperia Quad 2-input EXCLUSIVE-OR gate 9. Static characteristics Table 6. Static characteristics VSS = 0 V; VI = VSS or VDD unless otherwise specified. Symbol Parameter VIH VIL VOH VOL IOH IOL HIGH-level input voltage |IO| < 1 μA LOW-level input |IO| < 1 μA voltage HIGH-level output voltage |IO| < 1 μA VDD Tamb = -40 °C Tamb = +25 °C Tamb = +85 °C Tamb = +125 °C Unit Min Max Min Max Min Max Min Max 3.5 - 3.5 - 3.5 - 3.5 - V 10 V 7.0 - 7.0 - 7.0 - 7.0 - V 15 V 11.0 - 11.0 - 11.0 - 11.0 - V 5V - 1.5 - 1.5 - 1.5 - 1.5 V 10 V - 3.0 - 3.0 - 3.0 - 3.0 V 15 V - 4.0 - 4.0 - 4.0 - 4.0 V 5V 4.95 - 4.95 - 4.95 - 4.95 - V 10 V 9.95 - 9.95 - 9.95 - 9.95 - V 15 V 14.95 - 14.95 - 14.95 - 14.95 - V 5V - 0.05 - 0.05 - 0.05 - 0.05 V 10 V - 0.05 - 0.05 - 0.05 - 0.05 V 5V LOW-level output voltage |IO| < 1 μA 15 V - 0.05 - 0.05 - 0.05 - 0.05 V HIGH-level output current VO = 2.5 V 5V - -1.7 - -1.4 - -1.1 - -1.1 mA VO = 4.6 V 5V - -0.64 - -0.5 - -0.36 - -0.36 mA VO = 9.5 V 10 V - -1.6 - -1.3 - -0.9 - -0.9 mA VO = 13.5 V 15 V - -4.2 - -3.4 - -2.4 - -2.4 mA VO = 0.4 V 5V 0.64 - 0.5 - 0.36 - 0.36 - mA VO = 0.5 V 10 V 1.6 - 1.3 - 0.9 - 0.9 - mA VO = 1.5 V 15 V 4.2 - 3.4 - 2.4 - 2.4 - mA 15 V - ±0.1 - ±0.1 - ±1.0 - ±1.0 μA all valid input 5 V combinations; 10 V IO = 0 A 15 V - 0.25 - 0.25 - 7.5 - 7.5 μA - 0.5 - 0.5 - 15.0 - 15.0 μA - 1.0 - 1.0 - 30.0 - 30.0 μA - - - 7.5 - - - - pF LOW-level output current II input leakage current IDD supply current CI Conditions input capacitance HEF4030B_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 7 December 2021 © Nexperia B.V. 2021. All rights reserved 4 / 10 HEF4030B-Q100 Nexperia Quad 2-input EXCLUSIVE-OR gate 10. Dynamic characteristics Table 7. Dynamic characteristics Tamb = 25 °C unless otherwise specified. For waveforms see Fig. 4; for test circuit, see Fig. 5. Symbol Parameter VDD Extrapolation formula [1] tPHL 5V HIGH to LOW propagation delay tPLH LOW to HIGH propagation delay Typ Max Unit 57 + 0.55 × CL - 85 175 ns 10 V 24 + 0.23 × CL - 35 75 ns 15 V 22 + 0.16 × CL - 30 55 ns 5V 47 + 0.55 × CL - 75 150 ns 10 V 19 + 0.23 × CL - 30 65 ns 15 V 17 + 0.16 × CL - 25 50 ns 10 + 1.00 × CL - 60 120 ns 10 V 9 + 0.42 × CL - 30 60 ns 15 V 6 + 0.28 × CL - 20 40 ns 10 + 1.00 × CL - 60 120 ns 10 V 9 + 0.42 × CL - 30 60 ns 15 V 6 + 0.28 × CL - 20 40 ns HIGH to LOW output transition time 5 V tTHL LOW to HIGH output transition time 5 V tTLH [1] Min The typical value of the propagation delay and output transition time can be calculated with the extrapolation formula (CL in pF). Table 8. Dynamic power dissipation VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C. Symbol Parameter PD VDD dynamic power dissipation Typical formula Where 2 5V PD = 1100 × fi + Σ(fo × CL) × VDD (μW) fi = input frequency in MHz; 2 10 V PD = 4900 × fi + Σ(fo × CL) × VDD (μW) fo = output frequency in MHz; CL = output load capacitance in pF; 2 15 V PD = 14400 × fi + Σ(fo × CL) × VDD Σ(fo × CL) = sum of the outputs; (μW) VDD = supply voltage in V. 10.1. Waveforms and test circuit tr VI tf 90 % VM nA, nB input 0V 10 % tPHL VOH tPLH 90 % VM nY output VOL 10 % tTHL tTLH aaa-009502 Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig. 4. Input to output propagation delays and output transition times HEF4030B_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 7 December 2021 © Nexperia B.V. 2021. All rights reserved 5 / 10 HEF4030B-Q100 Nexperia Quad 2-input EXCLUSIVE-OR gate Table 9. Measurement points Supply voltage Input Output VDD VM VM 5 V to 15 V 0.5VDD 0.5VDD VDD G VI VO DUT CL RT 001aag182 Test data is given in Table 10. Definitions for test circuit: CL = load capacitance including jig and probe capacitance. RT = termination resistance should be equal to the output impedance Zo of the pulse generator. Fig. 5. Test circuit for measuring switching times Table 10. Test data Supply voltage Input VDD VI tr, tf CL 5 V to 15 V VSS or VDD ≤ 20 ns 50 pF HEF4030B_Q100 Product data sheet Load All information provided in this document is subject to legal disclaimers. Rev. 2 — 7 December 2021 © Nexperia B.V. 2021. All rights reserved 6 / 10 HEF4030B-Q100 Nexperia Quad 2-input EXCLUSIVE-OR gate 11. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 A2 Q A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 inches 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.05 0.01 0.01 0.004 0.028 0.012 0.244 0.039 0.028 0.041 0.228 0.016 0.024 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. Fig. 6. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Package outline SOT108-1 (SO14) HEF4030B_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 7 December 2021 © Nexperia B.V. 2021. All rights reserved 7 / 10 HEF4030B-Q100 Nexperia Quad 2-input EXCLUSIVE-OR gate 12. Abbreviations Table 11. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MIL Military MM Machine Model 13. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes HEF4030B_Q100 v.2 20211207 Product data sheet - HEF4030B_Q100 v.1 Modification • • • • HEF4030B_Q100 v.1 HEF4030B_Q100 Product data sheet The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Section 1 and Section 2 updated. Table 4: Derating values for Ptot total power dissipation updated. 20131113 Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 2 — 7 December 2021 - © Nexperia B.V. 2021. All rights reserved 8 / 10 HEF4030B-Q100 Nexperia Quad 2-input EXCLUSIVE-OR gate equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. 14. Legal information Data sheet status Document status [1][2] Product status [3] Definition Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Objective [short] data sheet Development This document contains data from the objective specification for product development. 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This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This Nexperia product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or HEF4030B_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 7 December 2021 © Nexperia B.V. 2021. All rights reserved 9 / 10 HEF4030B-Q100 Nexperia Quad 2-input EXCLUSIVE-OR gate Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................1 4. Functional diagram.......................................................2 5. Pinning information......................................................2 5.1. Pinning.........................................................................2 5.2. Pin description............................................................. 2 6. Functional description................................................. 3 7. Limiting values............................................................. 3 8. Recommended operating conditions..........................3 9. Static characteristics....................................................4 10. Dynamic characteristics............................................ 5 10.1. Waveforms and test circuit........................................ 5 11. Package outline.......................................................... 7 12. Abbreviations.............................................................. 8 13. Revision history..........................................................8 14. Legal information........................................................9 © Nexperia B.V. 2021. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 7 December 2021 HEF4030B_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 7 December 2021 © Nexperia B.V. 2021. All rights reserved 10 / 10