HEF4072BT,653

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4072B gates Dual 4-input OR gate Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification HEF4072B gates Dual 4-input OR gate DESCRIPTION The HEF4072B provides the positive dual 4-input OR function. The outputs are fully buffered for highest noise immunity and pattern insensitivity of output impedance. Fig.2 Pinning diagram. HEF4072BP(N): 14-lead DIL; plastic (SOT27-1) HEF4072BD(F): 14-lead DIL; ceramic (cerdip) (SOT73) HEF4072BT(D): 14-lead SO; plastic (SOT108-1) Fig.1 Functional diagram. ( ): Package Designator North America Fig.3 Logic diagram (one gate). FAMILY DATA, IDD LIMITS category GATES See Family Specifications January 1995 2 Philips Semiconductors Product specification HEF4072B gates Dual 4-input OR gate AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V SYMBOL TYP. TYPICAL EXTRAPOLATION FORMULA MAX. Propagation delays In → On HIGH to LOW 5 10 tPHL 15 5 LOW to HIGH 10 tPLH 15 Output transition times HIGH to LOW 5 10 tTHL 15 5 LOW to HIGH 10 tTLH 15 VDD V Dynamic power dissipation per package (P) 5 80 155 ns 53 ns + (0,55 ns/pF) CL 35 70 ns 24 ns + (0,23 ns/pF) CL 25 55 ns 17 ns + (0,16 ns/pF) CL 75 145 ns 48 ns + (0,55 ns/pF) CL 35 70 ns 24 ns + (0,23 ns/pF) CL 25 55 ns 17 ns + (0,16 ns/pF) CL 10 ns + (1,0 ns/pF) CL 60 120 ns 30 60 ns 9 ns + (0,42 ns/pF) CL 20 40 ns 6 ns + (0,28 ns/pF) CL 60 120 ns 30 60 ns 9 ns + (0,42 ns/pF) CL 20 40 ns 6 ns + (0,28 ns/pF) CL 10 ns + (1,0 ns/pF) CL TYPICAL FORMULA FOR P (µW) 950 fi + ∑ (foCL) × VDD2 10 4500 fi + ∑ (foCL) × VDD 2 15 13 700 fi + ∑ (foCL) × VDD 2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) ∑ (foCL) = sum of outputs VDD = supply voltage (V) January 1995 3