HEF4104BT

HEF4104B Quad low-to-high voltage translator with 3-state outputs Rev. 07 — 16 December 2009 Product data sheet 1. General description The HEF4104B is a quad low voltage-to-high voltage translator with 3-state outputs. It provides the capability of interfacing low voltage circuits to high voltage circuits. For example low voltage Local Oxidation Complementary MOS (LOCMOS) and Transistor Transistor Logic (TTL) to high voltage LOCMOS. It has four data inputs (A0 to A3), an active HIGH output enable input (OE), four data outputs (B0 to B3) and their complements (B0 to B3). With OE = HIGH, the outputs B0 to B3 and B0 to B3 are in the low impedance ON-state, either HIGH or LOW as determined by the inputs A0 to A3. With OE = LOW, the outputs B0 to B3 and B0 to B3 are in the high-impedance OFF-state. It uses a common negative supply (VSS) and separate positive supplies for the inputs (VDD(A)) and the outputs (VDD(B)). VDD(A) must always be less than or equal to VDD(B), even during power turn-on and turn-off. For the permissible operating range of VDD(A) and VDD(B) see Figure 4. Each input protection circuit is terminated between VDD(B) and VSS. This allows the input signals to be driven from any potential between VDD(B) and VSS, without regard to current limiting. When driving from potentials greater than VDD(B) or less than VSS, the current at each input must be limited to 10 mA. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. It is also suitable for use over the full industrial (−40 °C to +85 °C) temperature range. 2. Features Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Inputs and outputs are protected against electrostatic effects Operates across the full industrial temperature range from −40 °C to +85 °C Complies with JEDEC standard JESD 13-B 3. Applications Industrial NXP Semiconductors HEF4104B Quad low-to-high voltage translator with 3-state outputs 4. Ordering information Table 1. Ordering information All types operate from −40 °C to +85 °C. Type number HEF4104BP HEF4104BT Package Name DIP16 SO16 Description plastic dual in-line package; 16 leads (300 mil) plastic small outline package; 16 leads; body width 3.9 mm Version SOT38-4 SOT109-1 5. Functional diagram VDD(A) 16 4 2 VDD(B) 1 3 A0 B0 B0 LEVEL CONVERTER A1 5 6 A0 B1 B0 B0 7 11 LEVEL CONVERTER B1 A1 A2 10 B2 LEVEL CONVERTER LEVEL CONVERTER B1 B1 9 A3 12 A2 B2 B2 B2 13 B3 A3 14 B3 LEVEL CONVERTER VDD(A) VDD(B) 001aag264 LEVEL CONVERTER B3 OE 15 B3 OE 8 VSS 001aag262 Fig 1. Logic symbol Fig 2. Logic diagram HEF4104B_7 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 07 — 16 December 2009 2 of 14 NXP Semiconductors HEF4104B Quad low-to-high voltage translator with 3-state outputs 6. Pinning information 6.1 Pinning HEF4104B VDD(B) B0 B0 A0 A1 B1 B1 VSS 1 2 3 4 5 6 7 8 001aag263 16 VDD(A) 15 OE 14 B3 13 B3 12 A3 11 A2 10 B2 9 B2 Fig 3. Pin configuration 6.2 Pin description Table 2. Symbol VDD(B) B0 to B3 B0 to B3 A0 to A3 VSS OE VDD(A) Pin description Pin 1 2, 7, 9, 14 3, 6, 10, 13 4, 5, 11, 12 8 15 16 Description supply voltage port B complementary data output data output data input common negative supply voltage (0 V) output enable input supply voltage port A 7. Functional description Table 3. Control OE H L [1] Function table[1] Output Bn An Z Bn An Z H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state. HEF4104B_7 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 07 — 16 December 2009 3 of 14 NXP Semiconductors HEF4104B Quad low-to-high voltage translator with 3-state outputs 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground). Symbol VDD(A) VDD(B) IIK VI IOK II/O IDD Tstg Tamb Ptot Parameter supply voltage A supply voltage B input clamping current input voltage output clamping current input/output current supply current storage temperature ambient temperature total power dissipation Tamb = −40 °C to +85 °C DIP16 SO16 P [1] [2] [3] [2] [3] [1] Conditions port A; VDD(A) ≤ VDD(B) port B; VDD(B) ≥ VDD(A) VI < −0.5 V or VI > VDD(A) + 0.5 V VO < −0.5 V or VO > VDD(B) + 0.5 V Min −0.5 −0.5 −0.5 −65 −40 - Max +18 +18 ±10 ±10 ±10 50 +150 +85 750 500 100 Unit V V mA mA mA mA °C °C mW mW mW VDD(A) + 0.5 V power dissipation IDD is the combined current of IDD(A) and IDD(B). per output For DIP16 packages: above Tamb = 70 °C, Ptot derates linearly at 12 mW/K. For SO16 packages: above Tamb = 70 °C, Ptot derates linearly at 8 mW/K. 9. Recommended operating conditions Table 5. Symbol VDD(A) VDD(B) VI Tamb Δt/ΔV Recommended operating conditions Parameter supply voltage A supply voltage B input voltage ambient temperature input transition rise and fall rate in free air VDD(A) = 5 V VDD(A) = 10 V VDD(A) = 15 V Conditions Min 3 ≥ VDD(A) 0 −40 Typ Max ≤ VDD(B) 15 VDD(A) +85 3.75 0.5 0.08 Unit V V V °C μs/V μs/V μs/V HEF4104B_7 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 07 — 16 December 2009 4 of 14 NXP Semiconductors HEF4104B Quad low-to-high voltage translator with 3-state outputs 10. Static characteristics Table 6. Static characteristics VDD(A) = VDD(B); VSS = 0 V; VI = VSS or VDD(A); unless otherwise specified. Symbol Parameter VIH HIGH-level input voltage Conditions |IO| < 1 μA VDD[1] 5V 10 V 15 V VIL LOW-level input voltage |IO| < 1 μA 5V 10 V 15 V VOH HIGH-level output voltage |IO| < 1 μA 5V 10 V 15 V VOL LOW-level output voltage |IO| < 1 μA 5V 10 V 15 V IOH HIGH-level output current VO = 2.5 V VO = 4.6 V VO = 9.5 V VO = 13.5 V IOL LOW-level output current VO = 0.4 V VO = 0.5 V VO = 1.5 V II IDD input leakage current supply current all valid input combinations; IO = 0 A HIGH level; VO = VDD(B) LOW level; VO = VSS CI [1] [2] Tamb = −40 °C Tamb = +25 °C Tamb = +85 °C Unit Min 3.5 7.0 11.0 4.95 9.95 14.95 −1.7 −0.52 −1.3 −3.6 0.52 1.3 3.6 [2] Max 1.5 3.0 4.0 0.05 0.05 0.05 ±0.3 20 40 80 1.6 −1.6 - Min 3.5 7.0 11.0 4.95 9.95 14.95 −1.4 −0.44 −1.1 −3.0 0.44 1.1 3.0 - Max 1.5 3.0 4.0 0.05 0.05 0.05 ±0.3 20 40 80 1.6 −1.6 7.5 Min 3.5 7.0 11.0 4.95 9.95 14.95 −1.1 −0.36 −0.9 −2.4 0.36 0.9 2.4 - Max 1.5 3.0 4.0 0.05 0.05 0.05 ±1.0 150 300 600 12.0 V V V V V V V V V V V V mA mA mA mA mA mA mA μA μA μA μA μA 5V 5V 10 V 15 V 5V 10 V 15 V 15 V 5V 10 V 15 V 15 V 15 V - - IOZ OFF-state output current −12.0 μA pF input capacitance digital inputs VDD is the same as VDD(A) and VDD(B). IDD is the combined current of IDD(A) and IDD(B). HEF4104B_7 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 07 — 16 December 2009 5 of 14 NXP Semiconductors HEF4104B Quad low-to-high voltage translator with 3-state outputs 15 VDD(B) (V) 10 001aag265 operating area 5 0 0 5 10 VDD(A) (V) 15 The shaded area shows the permissible operating range. Fig 4. VDD(B) as a function of VDD(A) 11. Dynamic characteristics Table 7. Dynamic characteristics Tamb = 25 °C; for test circuit see Figure 7; unless otherwise specified. Symbol Parameter tPHL HIGH to LOW propagation delay Conditions An to Bn, Bn; see Figure 5 VDD(A) = VDD(B) = 5 V VDD(A) = VDD(B) = 10 V VDD(A) = VDD(B) = 15 V tPLH LOW to HIGH propagation delay An to Bn, Bn; see Figure 5 VDD(A) = VDD(B) = 5 V VDD(A) = VDD(B) = 10 V VDD(A) = VDD(B) = 15 V tTHL HIGH to LOW output Bn or Bn; see Figure 6 transition time VDD(A) = VDD(B) = 5 V VDD(A) = VDD(B) = 10 V VDD(A) = VDD(B) = 15 V tTLH LOW to HIGH output Bn or Bn; see Figure 6 transition time VDD(A) = VDD(B) = 5 V VDD(A) = VDD(B) = 10 V VDD(A) = VDD(B) = 15 V tPHZ HIGH to OFF-state propagation delay OE to Bn, Bn; see Figure 6 VDD(A) = VDD(B) = 5 V VDD(A) = VDD(B) = 10 V VDD(A) = VDD(B) = 15 V 70 55 60 135 110 120 ns ns ns 143 ns + (0.55 ns/pF)CL 69 ns + (0.23 ns/pF)CL 62 ns + (0.16 ns/pF)CL 10 ns + (1.00 ns/pF)CL 9 ns + (0.42 ns/pF)CL 6 ns + (0.28 ns/pF)CL 10 ns + (1.00 ns/pF)CL 9 ns + (0.42 ns/pF)CL 6 ns + (0.28 ns/pF)CL 170 80 70 60 30 20 60 30 20 340 160 140 120 60 40 120 60 40 ns ns ns ns ns ns ns ns ns 143 ns + (0.55 ns/pF)CL 69 ns + (0.23 ns/pF)CL 57 ns + (0.16 ns/pF)CL 170 80 65 340 160 135 ns ns ns Extrapolation formula[1] Min Typ Max Unit HEF4104B_7 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 07 — 16 December 2009 6 of 14 NXP Semiconductors HEF4104B Quad low-to-high voltage translator with 3-state outputs Table 7. Dynamic characteristics …continued Tamb = 25 °C; for test circuit see Figure 7; unless otherwise specified. Symbol Parameter tPLZ LOW to OFF-state propagation delay Conditions OE to Bn, Bn; see Figure 6 VDD(A) = VDD(B) = 5 V VDD(A) = VDD(B) = 10 V VDD(A) = VDD(B) = 15 V tPZH OFF-state to HIGH propagation delay OE to Bn, Bn; see Figure 6 VDD(A) = VDD(B) = 5 V VDD(A) = VDD(B) = 10 V VDD(A) = VDD(B) = 15 V tPZL OFF-state to LOW propagation delay OE to Bn, Bn; see Figure 6 VDD(A) = VDD(B) = 5 V VDD(A) = VDD(B) = 10 V VDD(A) = VDD(B) = 15 V [1] Extrapolation formula[1] Min - Typ 70 55 55 195 95 80 195 95 80 Max 135 105 110 395 195 165 395 190 160 Unit ns ns ns ns ns ns ns ns ns Typical value of the propagation delay and output transition time can be calculated with the extrapolation formula (CL in pF). Table 8. Dynamic power dissipation VDD(A) = VDD(B); VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C. Symbol Parameter PD dynamic power dissipation VDD[1] Typical formula (μW) 5V 10 V 15 V PD = 3000 × fi + Σ(fo × CL) × VDD 2 where fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; Σ(fo × CL) = sum of the outputs; VDD = supply voltage in V. PD = 12200 × fi + Σ(fo × CL) × VDD2 PD = 31000 × fi + Σ(fo × CL) × VDD2 [1] VDD is the same as VDD(A) and VDD(B). HEF4104B_7 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 07 — 16 December 2009 7 of 14 NXP Semiconductors HEF4104B Quad low-to-high voltage translator with 3-state outputs 12. Waveforms VI An input 0V VM tPHL VOH Bn output VOL tPLH VY VM VX tTHL tPLH tTLH tPHL VOH Bn output VOL VY VX tTLH tTHL 001aaj783 Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 5. Data input (An) to data output (Bn, Bn) propagation delays and output transition times VI OE input VSS tPLZ output LOW-to-OFF OFF-to-LOW VOH tPZL VY VM VOL tPHZ VOH VX tPZH VY VX outputs on outputs off outputs on 001aaj782 output HIGH-to-OFF OFF-to-HIGH VOL Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 6. Table 9. Input VI Enable and disable times Measurement points Output VM 0.5VDD(A) VM 0.5VDD(B) VX 0.1VDD(B) VY 0.9VDD(B) © NXP B.V. 2009. All rights reserved. VSS or VDD(A) HEF4104B_7 Product data sheet Rev. 07 — 16 December 2009 8 of 14 NXP Semiconductors HEF4104B Quad low-to-high voltage translator with 3-state outputs VI negative pulse 0V tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW 001aaj781 VM VI positive pulse 0V VM a. Input waveforms VEXT VDD VI VO RL G RT DUT CL 001aaj915 b. Test circuit Test data given in Table 10. Definitions for test circuit: DUT = Device Under Test. CL = load capacitance including jig and probe capacitance. RL = load resistance. RT = termination resistance should be equal to the output impedance Zo of the pulse generator. Fig 7. Table 10. Supplies Test circuit for measuring switching times Test data Input tr, tf ≤ 20 ns Load RL 1 kΩ CL 50 pF VEXT tPHL, tPLH open tPZL, tPLZ VDD(B) tPZH, tPHZ VSS VDD(A) = VDD(B) 5 V to 15 V HEF4104B_7 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 07 — 16 December 2009 9 of 14 NXP Semiconductors HEF4104B Quad low-to-high voltage translator with 3-state outputs 13. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 D seating plane ME A2 A L A1 c Z e b1 b 16 9 b2 MH wM (e 1) pin 1 index E 1 8 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.02 A2 max. 3.2 0.13 b 1.73 1.30 0.068 0.051 b1 0.53 0.38 0.021 0.015 b2 1.25 0.85 0.049 0.033 c 0.36 0.23 0.014 0.009 D (1) 19.50 18.55 0.77 0.73 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.1 e1 7.62 0.3 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 0.76 0.03 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT38-4 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 95-01-14 03-02-13 Fig 8. HEF4104B_7 Package outline SOT38-4 (DIP16) © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 07 — 16 December 2009 10 of 14 NXP Semiconductors HEF4104B Quad low-to-high voltage translator with 3-state outputs SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE vMA Z 16 9 Q A2 pin 1 index θ Lp 1 8 A1 (A 3) A L wM detail X e bp 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3 θ o 0.010 0.057 0.069 0.004 0.049 0.019 0.0100 0.39 0.014 0.0075 0.38 0.244 0.041 0.228 0.028 0.004 0.012 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07 JEDEC MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 9. HEF4104B_7 Package outline SOT109-1 (SO16) © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 07 — 16 December 2009 11 of 14 NXP Semiconductors HEF4104B Quad low-to-high voltage translator with 3-state outputs 14. Revision history Table 11. Revision history Release date 20091216 Data sheet status Product data sheet Product data sheet Product data sheet Product data sheet Product specification Product specification Change notice Supersedes HEF4104B_6 HEF4104B_5 HEF4104B_4 HEF4104B_CNV_3 HEF4104B_CNV_2 Document ID HEF4104B_7 Modifications: HEF4104B_6 HEF4104B_5 HEF4104B_4 HEF4104B_CNV_3 HEF4104B_CNV_2 • Section 12 “Waveforms” Figure 7 “Test circuit for measuring switching times” updated. 20091102 20090728 20090305 19950101 19950101 HEF4104B_7 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 07 — 16 December 2009 12 of 14 NXP Semiconductors HEF4104B Quad low-to-high voltage translator with 3-state outputs 15. Legal information 15.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com HEF4104B_7 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 07 — 16 December 2009 13 of 14 NXP Semiconductors HEF4104B Quad low-to-high voltage translator with 3-state outputs 17. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12 Legal information. . . . . . . . . . . . . . . . . . . . . . . 13 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Contact information. . . . . . . . . . . . . . . . . . . . . 13 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 16 December 2009 Document identifier: HEF4104B_7