Freescale Semiconductor
Addendum
Document Number: QFN_Addendum
Rev. 0, 07/2014
Addendum for New QFN
Package Migration
This addendum provides the changes to the 98A case outline numbers for products covered in this book.
Case outlines were changed because of the migration from gold wire to copper wire in some packages. See
the table below for the old (gold wire) package versus the new (copper wire) package.
To view the new drawing, go to Freescale.com and search on the new 98A package number for your
device.
For more information about QFN package use, see EB806: Electrical Connection Recommendations for
the Exposed Pad on QFN and DFN Packages.
© Freescale Semiconductor, Inc., 2014. All rights reserved.
Part Number
MC68HC908JW32
Package Description
Original (gold wire)
Current (copper wire)
package document number package document number
48 QFN
98ARH99048A
98ASA00466D
MC9RS08LA8
48 QFN
98ARL10606D
98ASA00466D
MC9S08GT16A
32 QFN
98ARH99035A
98ASA00473D
MC9S908QE32
32 QFN
98ARE10566D
98ASA00473D
MC9S908QE8
32 QFN
98ASA00071D
98ASA00736D
MC9S08JS16
24 QFN
98ARL10608D
98ASA00734D
MC9S08QG8
24 QFN
98ARL10605D
98ASA00474D
MC9S08SH8
24 QFN
98ARE10714D
98ASA00474D
MC9RS08KB12
24 QFN
98ASA00087D
98ASA00602D
MC9S08QG8
16 QFN
98ARE10614D
98ASA00671D
MC9RS08KB12
8 DFN
98ARL10557D
98ASA00672D
6 DFN
98ARL10602D
98ASA00735D
MC9S08AC16
MC9S908AC60
MC9S08AC128
MC9S08AW60
MC9S08GB60A
MC9S08GT16A
MC9S08JM16
MC9S08JM60
MC9S08LL16
MC9S08QE128
MC9S08QE32
MC9S08RG60
MCF51CN128
MC9S08QB8
MC9S08QG8
MC9RS08KA2
Addendum for New QFN Package Migration, Rev. 0
2
Freescale Semiconductor
Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MCF51CN128
Rev. 4, 5/2009
MCF51CN128
MCF51CN128 ColdFire
Microcontroller
Cover: MCF51CN128
The MCF51CN128 device is a low-cost, low-power,
high-performance 32-bit ColdFire V1 microcontroller (MCU)
featuring 10/100 BASE-T/TX fast ethernet controller (FEC),
media independent interface (MII) to connect an external
physical transceiver (PHY), and multi-function external bus
interface.
MCF51CN128 also has multiple communication interfaces
for various ethernet gateway applications. MCF51CN128 is
the first ColdFire V1 device to incorporate ethernet and
external bus interface along with new features to minimize
power consumption and increase functionality in low-power
modes.
The MCF51CN128 features the following functional units:
• 32-bit ColdFire V1 Central Processing Unit (CPU)
– Up to 50.33 MHz ColdFire CPU from 3.6 V to 3.0 V, up
to 40 MHz CPU from 3.0 V to 2.1 V, and up to 20 MHz
CPU from 2.1 V to 1.8 V across temperature range of
–40 °C to 85 °C
– Provides 0.94 Dhrystone 2.1 MIPS per MHz
performance when running from internal RAM
(0.76 DMIPS/MHz from flash)
– ColdFire Instruction Set Revision C (ISA_C)
– Support for up to 45 peripheral interrupt requests and 7
software interrupts
• On-Chip Memory
– 128 KB Flash, 24 KB RAM
– Flash read/program/erase over full operating voltage
and temperature
– On-chip memory aliased to create a contiguous memory
space with off-chip memory
– Security circuitry to prevent unauthorized access to
Peripherals, RAM, and flash contents
• Ethernet
– FEC—10/100 BASE-T/TX, bus-mastering fast ethernet
controller with direct memory access (DMA); supports
half or full duplex; operation is limited to 3.0 V to 3.6 V
80 LQFP
14 mm × 14 mm
48 QFN
7 mm × 7 mm
– MII—media independent interface to connect ethernet
controller to external PHY; includes output clock for
external PHY
• External Bus
– Mini-FlexBus—Multi-function external bus interface;
supports up to 1 MB memories, gate-array logic, simple
slave device or glueless interfaces to standard
chip-selected asynchronous memories
– Programmable options: access time per chip select, burst
and burst-inhibited transfers per chip select, transfer
direction, and address setup and hold times
• Power-Saving Modes
– Two low-power stop modes, one of which allows limited
use of some peripherals (ADC, KBI, RTC)
– Reduced-power wait mode shuts off CPU and allows
full use of all peripherals; FEC can remain active and
conduct DMA transfers to RAM and assert an interrupt
to wake up the CPU upon completion
– Low-power run and wait modes allow peripherals to run
while the voltage regulator is in standby
– Peripheral clock enable register can disable clocks to
unused modules, thereby reducing currents
– Low-power external oscillator that can be used in stop3
mode to provide accurate clock source to active
peripherals
– Low-power real-time counter for use in run, wait, and
stop modes with internal and external clock sources
– 6 μs typical wake-up time from stop3 mode
– Pins and clocks to peripherals not available in smaller
packages are automatically disabled for reduced current
consumption; no user interaction is needed
• Clock Source Options
– Oscillator (XOSC) — Loop-control pierce oscillator;
crystal or ceramic resonator range of 31.25 kHz to
38.4 kHz or 1 MHz to 25 MHz
– Multi-Purpose Clock Generator (MCG) — Flexible
clock source module with either frequency-locked-loop
(FLL) or phase-lock loop (PLL) clock options. FLL can
be controlled by internal or external reference and
Freescale reserves the right to change the detail specifications as may be required to permit
improvements in the design of its products.
© Freescale Semiconductor, Inc., 2009. All rights reserved.
64 LQFP
10 mm × 10 mm
•
•
•
•
includes precision trimming of internal reference, allowing 0.2% resolution and 2% deviation over temperature and
voltage. PLL derives a higher accuracy clock source derived by an external reference
System Protection
– Watchdog computer operating properly (COP) reset with option to run from dedicated 1-kHz internal clock source or bus
clock
– Low-voltage detection with reset or interrupt; selectable trip points
– Illegal opcode and illegal address detection with programmable reset or exception response
– Flash block protection
Development Support
– Single-wire background debug module (BDM) interface; supports same electrical interface used by the S08, 9S12, and
9S12x families debug modules
– 4 PC plus 2 address (optional data) breakpoint registers with programmable 1- or 2-level trigger response
– 64-entry processor status and debug data trace buffer with programmable start/stop conditions
Peripherals
– ADC—Up to 12 channel, 12-bit resolution; 2.5 μs conversion time; automatic compare function; 1.7 mV/°C temperature
sensor; internal bandgap reference channel; operation in stop3; fully functional from 3.6 V to 1.8 V
– SCI—Three modules with optional 13-bit break
– SPI—Two interfaces with full-duplex or single-wire bi-directional; double-buffered transmit and receive; master or slave
mode; MSB-first or LSB-first shifting
– IIC—Two IICs with up to 100 kbps with maxmimum bus loading; multi-master operation; programmable slave address;
interrupt-driven byte-by-byte data transfer; supports broadcast mode and 11-bit addressing
– TPM—Two 3-channel, 16-bit resolution modules; selectable input capture, output compare, or buffered edge- or
center-aligned PWM on each channel
– RTC—8-bit modulus counter with binary- or decimal-based prescaler; external clock source for precise time base,
time-of-day, calendar- or task-scheduling functions; free-running on-chip low-power oscillator (1 kHz) for cyclic wake-up
without external components; runs in all MCU modes
– MTIM—Two 8-bit resolution modulo timers with 8-bit prescaler
Input/Output
– Up to 70 general-purpose input/output (GPIO) pins, all with pin mux controls to select alternate functions
– 16 keyboard interrupt (KBI) pins with selectable polarity
– Hysteresis and configurable pull-up device or input filtering on all input pins; configurable slew rate and drive strength on
all output pins
– 16 Rapid GPIO pins connected to the CPU’s high-speed local bus with set, clear, and toggle functionality (PTD and PTF)
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
2
Freescale Semiconductor
Table of Contents
1
2
3
4
5
6
7
MCF51CN128 Series Comparison . . . . . . . . . . . . . . . . . . . . . .4
1.1 Device Comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.2 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.2 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . .12
3.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .12
3.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .13
3.5 ESD Protection and Latch-Up Immunity . . . . . . . . . . . .14
3.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.7 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .18
3.8 External Oscillator (XOSC) Characteristics . . . . . . . . .20
3.9 Multipurpose Clock Generator (MCG) Specifications . .21
3.10 Mini-FlexBus Timing Specifications . . . . . . . . . . . . . . .23
3.11 Fast Ethernet Timing Specifications . . . . . . . . . . . . . . .24
3.11.1 Receive Signal Timing Specifications . . . . . . . .24
3.11.2 Transmit Signal Timing Specifications . . . . . . . .25
3.11.3 Asynchronous Input Signal Timing Specifications25
3.11.4 MII Serial Management Timing Specifications .26
3.12 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
3.12.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . .26
3.12.2 TPM Module Timing . . . . . . . . . . . . . . . . . . . . .28
3.12.3 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
3.12.4 ADC Characteristics . . . . . . . . . . . . . . . . . . . . .32
3.12.5 Flash Specifications. . . . . . . . . . . . . . . . . . . . . .35
3.13 EMC Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
3.13.1 Radiated Emissions . . . . . . . . . . . . . . . . . . . . . .36
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Mechanical Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . .36
6.1 80-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
6.2 64-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
6.3 48-pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
List of Tables
Table 1.. MCF51CN128 Series Device Comparison . . . . . . . . . . .4
Table 2.. Package Pin Assignments . . . . . . . . . . . . . . . . . . . . . . .8
Table 3.. Parameter Classifications . . . . . . . . . . . . . . . . . . . . . . .12
Table 4.. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .12
Table 5.. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .13
Table 6.. ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . .14
Table 7.. ESD and Latch-Up Protection Characteristics . . . . . . .14
Table 8.. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 9.. Supply Current Characteristics . . . . . . . . . . . . . . . . . . .18
Table 10..XOSC and ICS Specifications (Temperature Range = –40
to 85 °C Ambient) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Table 11..MCG Frequency Specifications (Temperature Range = –40
to 125 °C Ambient) . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 12..Mini-FlexBus AC Timing Specifications . . . . . . . . . . . .23
Table 13..Receive Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 14..Transmit Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 15..MII Transmit Signal Timing . . . . . . . . . . . . . . . . . . . . . 25
Table 16..MII Serial Management Channel Signal Timing . . . . . 26
Table 17..Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 18..TPM Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 19..SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 20..12-bit ADC Operating Conditions . . . . . . . . . . . . . . . . 32
Table 21..12-bit ADC Characteristics (VREFH = VDDAD, VREFL =
VSSAD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 22..Flash Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 23..Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 24..Package Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 25..Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
List of Figures
Figure 1..MCF51CN128 Series Block Diagram . . . . . . . . . . . . . . 5
Figure 2..Pin Assignments in 80-Pin LQFP Package. . . . . . . . . . 6
Figure 3..Pin Assignments in 64-Pin LQFP Package. . . . . . . . . . 7
Figure 4..Pin Assignments in 48-Pin QFN Package. . . . . . . . . . . 8
Figure 5..Pull-up and Pull-down Typical Resistor Values . . . . . . 16
Figure 6..Typical Low-Side Driver (Sink) Characteristics — Low Drive
(PTxDSn = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 7..Typical Low-Side Driver (Sink) Characteristics — High
Drive (PTxDSn = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 8..Typical High-Side (Source) Characteristics — Low Drive
(PTxDSn = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 9..Typical High-Side (Source) Characteristics — High Drive
(PTxDSn = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 10..Typical Run IDD for FBE and FEI, IDD vs. VDD
(ADC off, All Other Modules Enabled) . . . . . . . . . . . . . 19
Figure 11..Typical Crystal or Resonator Circuit: High Range and Low
Range/High Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 12..Typical Crystal or Resonator Circuit: Low Range/Low
Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 13..Mini-FlexBus Read Timing . . . . . . . . . . . . . . . . . . . . 23
Figure 14..Mini-FlexBus Write Timing . . . . . . . . . . . . . . . . . . . . 24
Figure 15..MII Receive Signal Timing Diagram . . . . . . . . . . . . . 25
Figure 16..MII Transmit Signal Timing Diagram . . . . . . . . . . . . . 25
Figure 17..MII Async Inputs Timing Diagram . . . . . . . . . . . . . . . 25
Figure 18..MII Serial Management Channel TIming Diagram . . 26
Figure 19..Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 20..IRQ/KBIPx Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 21..Timer External Clock. . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 22..Timer Input Capture Pulse . . . . . . . . . . . . . . . . . . . . 28
Figure 23..SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . . 30
Figure 24..SPI Master Timing (CPHA =1) . . . . . . . . . . . . . . . . . 30
Figure 25..SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . 31
Figure 26..SPI Slave Timing (CPHA = 1) . . . . . . . . . . . . . . . . . . 31
Figure 27..ADC Input Impedance Equivalency Diagram . . . . . . 33
MCF51CN128 ColdFire Microcontroller Advance Information Data Sheet, Rev. 4
3
Freescale Semiconductor
MCF51CN128 Series Comparison
1
MCF51CN128 Series Comparison
1.1
Device Comparison
The following table compares the various device derivatives available within the MCF51CN128 series.
Table 1. MCF51CN128 Series Device Comparison
MCF51CN128
Feature
80-pin
64-pin
Flash memory size (KB)
128
RAM size (KB)
24
V1 ColdFire core equiped with BDM (background debug
module) and 2X3 Crossbar switch
Yes
ADC (analog-to-digital converter) channels (12-bit)
12
FEC (Fast Ethernet Controller with MII Interface)
Yes
COP (computer operating properly)
Yes
IIC1 (inter-integrated circuit)
Yes
IIC2
Yes
IRQ (interrupt request input)
Yes
KBI (keyboard interrupts)
16
12
LVD (low-voltage detector)
Yes
MCG (multipurpose clock generator)
Yes
Port I/O
1
RGPIO (rapid general-purpose I/O)
48-pin
6
70
54
38
16
16
8
RTC (real-time counter)
Yes
SCI1, SCI2 & SCI3 (serial communications interface)
Yes
SPI1 & SPI2 (serial peripheral interface)
Yes
TPM1 (Timer/PWM Module) channels
3
3
3
TPM2 channels
3
3
3
Yes2
MTIM1 & MTIM2
External Timer Clocks
Mini-FlexBus
XOSC (crystal oscillator)
1
2
2
1
1
Yes
0
0
Yes
All GPIO are muxed with other functions
TMRCLK2 is not available on the 48 pin package, although MTIM2 can be used as an
internal timebase using on-chip clock sources.
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
4
Freescale Semiconductor
MCF51CN128 Series Comparison
1.2
Block Diagram
ColdFire V1 core
KBI
Port F/H:
TPM2CH2
TPM2CH1
TPM2CH0
Port B, F or H* : TPM2CLK
RESET/PTC3
TPM2
SIM
COP
Port F:
RGPIO15
RGPIO14
RGPIO13
RGPIO12
RGPIO11
RGPIO10
RGPIO9
RGPIO8
LVD
FLASH
128 KB
RAM
24 KB
MII
Port A:
MII_TX_CLK
MII_RX_CLK
MII_TX_EN
MII_TXD0
MII_TXD1
MII_TXD2
MII_TXD3
Port B:
MII_TX_ER
MII_RX_DV
MII_RXD0
MII_RXD1
MII_RXD2
MII_RXD3
MII_RX_ER
MII_CRS
Port C:
MII_COL
MII_MDC
MII_MDIO
FEC
VDD1
VSS1
VDD2
VSS2
VDD3
VSS3
VDD4
VSS4
RGPIO
Port D:
RGPIO7
RGPIO6
RGPIO5
RGPIO4
RGPIO3
RGPIO2
RGPIO1
RGPIO0
Port F:
FB_D7-FB_D0
Port H:
FB_A19-FB_A16
FB_A11-FB_A8
Port G:
FB_CS1
FB_CS0
OE
Mini-FlexBus
FB_RW
FB_A5-FB_A2
Port I:
FB_A15-FB_A12
FB_A7-FB_A6
Port E:
FB_A1-FB_A0
VREG
Port C:
External Interrupt IRQ
Port D:
MCG
Port B
Port E:
TPM1CH2
TPM1CH1
TPM1CH0
Port B, F or H* : TPM1CLK
TPM1
XOSC EXTAL
XTAL
Port A:
CLKOUT
Port E
BKGD/MS/PTD6/RGPIO6
Port E:
KBI2P7
KBI2P6
KBI2P5
KBI2P4
KBI2P3
KBI2P2
KBI2P1
KBI2P0
Port G/I:
KBI1P7
KBI1P6
KBI1P5
KBI1P4
KBI1P3
KBI1P2
KBI1P1
KBI1P0
Port C
INTC
Port C/G:
SDA2
SCL2
Port D
IIC2
RTC
MTIM1
Port B, F or H* :
MTIM1CLK
MTIM2
Port B, F or H* :
MTIM2CLK
SCI1
Port D:
RXD1
TXD1
SCI2
Port D:
RXD2
TXD2
SCI3
Port E:
RXD3
TXD3
SPI1
Port C:
SS1
SPSCK1
MOSI1
MISO1
Port D/E:
SS2
SPI2 SPSCK2
MOSI2
MISO2
Port F
BDM
Port D:
BKGD/MS
Port C/G:
SDA1
IIC1
SCL1
Port G
ADC
DBG
Port C:
ADP3ADP0
Port D:
ADP8ADP4
Port E:
ADP11ADP9
PTA7/MII_RX_DV/MOSI2
PTA6/MII_RXD0/MISO2
PTA5/MII_RXD1/SPSCK2
PTA4/MII_RXD2/RXD3
PTA3/MII_RXD3/TXD3
PTA2/MII_MDC/SCL2
PTA1/MII_MDIO/SDA2
PTA0/PHYCLK
PTB7/MII_TXD2/TPM2CH1
PTB6/MII_TXD1/TPM2CH0
PTB5/MII_TXD0/SPSCK1
PTB4/MII_TX_EN/MISO1
PTB3/MII_TX_CLK/MOSI1
PTB2/MII_TX_ER/SS1
PTB1/MII_RX_ER/TMRCLK1
PTB0/MII_RX_CLK/SS2
PTC7/SDA2/SPSCK1/ADP8
PTC6/SCL2/MISO1/ADP9
PTC5/MOSI1/ADP10
PTC4/IRQ/SS1/ADP11
PTC2/MII_CRS/SDA1
PTC1/MII_COL/SCL1
PTC0/MII_TXD3/TPM2CH2
PTD7/RGPIO7/SPSCK2/ADP3
BKGD/MS/PTD6/RGPIO6
PTD5/RGPIO5/XTAL
PTD4/RGPIO4/EXTAL
PTD3/RGPIO3/RXD2/ADP4
PTD2/RGPIO2/TXD2/ADP5
PTD1/RGPIO1/RXD1/ADP6
PTD0/RGPIO0/TXD1/ADP7
PTE7/KBI2P7/FB_CS0/RXD3
PTE6/KBI2P6/FB_D0/TXD3
PTE5/KBI2P5/IRQ/TPM1CH2
PTE4/KBI2P4/CLKOUT/TPM1CH1
PTE3/KBI2P3/TPM1CH0
PTE2/KBI2P2/SS2/ADP0
PTE1/KBI2P1/MOSI2/ADP1
PTE0/KBI2P0/MISO2/ADP2
PTF7/RGPIO15/FB_A13/FB_AD13/TPM2CH2
PTF6/RGPIO14/FB_A14/FB_AD14/TPM2CH1
PTF5/RGPIO13/FB_D4/TPM2CH0
PTF4/RGPIO12/FB_D5/TMRCLK2
PTF3/RGPIO11/FB_A16/FB_AD16
PTF2/RGPIO10/FB_A17/FB_AD17
PTF1/RGPIO9/FB_A18/FB_AD18
PTF0/RGPIO8/FB_A19/FB_AD19
PTG7/KBI1P7/FB_D1
PTG6/KBI1P6/FB_D2
PTG5/KBI1P5/FB_D3
PTG4/KBI1P4/FB_RW
PTG3/KBI1P3/FB_A5/FB_AD5/SDA1
PTG2/KBI1P2/FB_A6/FB_AD6/SCL1
PTG1/KBI1P1/FB_A7/FB_AD7/SDA2
PTG0/KBI1P0/FB_A8/FB_AD8/SCL2
Port H
VDDA
VREFH
VSSA
VREFL
PTH7/FB_A9/FB_AD9/TPM2CH2
PTH6/FB_A10/FB_AD10/TPM2CH1
PTH5/FB_A11/FB_AD11
PTH4/FB_A12/FB_AD12
PTH3/FB_D6/TPM2CH0
PTH2/FB_D7/TMRCLK1
PTH1/FB_OE
PTH0/FB_A15/FB_AD15
Port J
VDDA/
VREFH
VSSA/
VREFL
Port A
The following figure shows the connections between the MCF51CN128 series pins and modules.
PTJ5/FB_A0/FB_AD0
PTJ4/FB_A1/FB_AD1
PTJ3/FB_A2/FB_AD2
PTJ2/FB_A3/FB_AD3
PTJ1/FB_A4/FB_AD4
PTJ0/FB_ALE/FB_CS1
* TPMx and MTIMx external clocks each have the choice of being assigned to either TMRCLK1 or TMRCLK2.
Figure 1. MCF51CN128 Series Block Diagram
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
5
Pin Assignments
2
Pin Assignments
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
80-Pin LQFP
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
PTG7/KBI1P7/FB_D1
PTG6/KBI1P6/FB_D2
PTG5/KBI1P5/FB_D3
PTG4/KBI1P4/FB_RW
PTG3/KBI1P3/FB_A5/FB_AD5/SDA1
PTG2/KBI1P2/FB_A6/FB_AD6/SCL1
PTG1/KBI1P1/FB_A7/FB_AD7/SDA2
PTG0/KBI1P0/FB_A8/FB_AD8/SCL2
PTD3/RGPIO3/RXD2/ADP4
PTD2/RGPIO2/TXD2/ADP5
PTD1/RGPIO1/RXD1/ADP6
PTD0/RGPIO0/TXD1/ADP7
PTC7/SDA2/SPSCK1/ADP8
PTC6/SCL2/MISO1/ADP9
PTC5/MOSI1/ADP10
PTC4/IRQ/SS1/ADP11
VSSA
VDDA
VSS3
VDD3
VDD2
VSS2
PTB2/MII_TX_ER/SS1
PTB3/MII_TX_CLK/MOSI1
PTB4/MII_TX_EN/MISO1
PTB5/MII_TXD0/SPSCK1
PTB6/MII_TXD1/TPM2CH0
PTB7/MII_TXD2/TPM2CH1
PTC0/MII_TXD3/TPM2CH2
PTC1/MII_COL/SCL1
PTC2/MII_CRS/SDA1
RESET/PTC3
PTF4/RGPIO12/FB_D5/TMRCLK2
PTF5/RGPIO13/FB_D4/TPM2CH0
PTF6/RGPIO14/FB_A14/FB_AD14/TPM2CH1
PTF7/RGPIO15/FB_A13/FB_AD13/TPM2CH2
PTH4/FB_A12/FB_AD12
PTH5/FB_A11/FB_AD11
PTH6/FB_A10/FB_AD10/TPM2CH1
PTH7/FB_A9/FB_AD9/TPM2CH2
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
VDD1
VSS1
PTA0/PHYCLK
PTA1/MII_MDIO/SDA2
PTA2/MII_MDC/SCL2
PTA3/MII_RXD3/TXD3
PTA4/MII_RXD2/RXD3
PTA5/MII_RXD1/SPSCK2
PTA6/MII_RXD0/MISO2
PTA7/MII_RX_DV/MOSI2
PTB0/MII_RX_CLK/SS2
PTB1/MII_RX_ER/TMRCLK1
PTF0/RGPIO8/FB_A19/FB_AD19
PTF1/RGPIO9/FB_A18/FB_AD18
PTF2/RGPIO10/FB_A17/FB_AD17
PTF3/RGPIO11/FB_A16/FB_AD16
PTH0/FB_A15/FB_AD15
PTH1/FB_OE
PTH2/FB_D7/TMRCLK1
PTH3/FB_D6/TPM2CH0
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
PTJ5/FB_A0/FB_AD0
PTJ4/FB_A1/FB_AD1
PTJ3/FB_A2/FB_AD2
PTJ2/FB_A3/FB_AD3
PTJ1/FB_A4/FB_AD4
PTJ0/FB_ALE/FB_CS1
PTE7/KBI2P7/FB_CS0/RXD3
PTE6/KBI2P6/FB_D0/TXD3
PTE5/KBI2P5/IRQ/TPM1CH2
PTE4/KBI2P4/CLKOUT/TPM1CH1
PTE3/KBI2P3/TPM1CH0
PTE2/KBI2P2/SS2/ADP0
PTE1/KBI2P1/MOSI2/ADP1
PTE0/KBI2P0/MISO2/ADP2
PTD7/RGPIO7/SPSCK2/ADP3
BKGD/MS/PTD6/RGPIO6
PTD5/RGPIO5/XTAL
PTD4/RGPIO4/EXTAL
VSS4
VDD4
This section describes the pin assignments for the available packages. See for pin availability by package pin-count.
Figure 2. Pin Assignments in 80-Pin LQFP Package
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
6
Freescale Semiconductor
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
64-Pin LQFP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PTG3/KBI1P3/FB_A5/FB_AD5/SDA1
PTG2/KBI1P2/FB_A6/FB_AD6/SCL1
PTG1/KBI1P1/FB_A7/FB_AD7/SDA2
PTG0/KBI1P0/FB_A8/FB_AD8/SCL2
PTD3/RGPIO3/RXD2/ADP4
PTD2/RGPIO2/TXD2/ADP5
PTD1/RGPIO1/RXD1/ADP6
PTD0/RGPIO0/TXD1/ADP7
PTC7/SDA2/SPSCK1/ADP8
PTC6/SCL2/MISO1/ADP9
PTC5/MOSI1/ADP10
PTC4/IRQ/SS1/ADP11
VSSA
VDDA
VSS3
VDD3
VDD2
VSS2
PTB2/MII_TX_ER/SS1
PTB3/MII_TX_CLK/MOSI1
PTB4/MII_TX_EN/MISO1
PTB5/MII_TXD0/SPSCK1
PTB6/MII_TXD1/TPM2CH0
PTB7/MII_TXD2/TPM2CH1
PTC0/MII_TXD3/TPM2CH2
PTC1/MII_COL/SCL1
PTC2/MII_CRS/SDA1
RESET/PTC3
PTF4/RGPIO12/FB_D5/TMRCLK2
PTF5/RGPIO13/FB_D4/TPM2CH0
PTF6/RGPIO14/FB_A14/FB_AD14/TPM2CH1
PTF7/RGPIO15/FB_A13/FB_AD13/TPM2CH2
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VDD1
VSS1
PTA0/PHYCLK
PTA1/MII_MDIO/SDA2
PTA2/MII_MDC/SCL2
PTA3/MII_RXD3/TXD3
PTA4/MII_RXD2/RXD3
PTA5/MII_RXD1/SPSCK2
PTA6/MII_RXD0/MISO2
PTA7/MII_RX_DV/MOSI2
PTB0/MII_RX_CLK/SS2
PTB1/MII_RX_ER/TMRCLK1
PTF0/RGPIO8/FB_A19/FB_AD19
PTF1/RGPIO9/FB_A18/FB_AD18
PTF2/RGPIO10/FB_A17/FB_AD17
PTF3/RGPIO11/FB_A16/FB_AD16
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
PTJ1/FB_A4/FB_AD4
PTJ0/FB_ALE/FB_CS1
PTE7/KBI2P7/FB_CS0/RXD3
PTE6/KBI2P6/FB_D0/TXD3
PTE5/KBI2P5/IRQ/TPM1CH2
PTE4/KBI2P4/CLKOUT/TPM1CH1
PTE3/KBI2P3/TPM1CH0
PTE2/KBI2P2/SS2/ADP0
PTE1/KBI2P1/MOSI2/ADP1
PTE0/KBI2P0/MISO2/ADP2
PTD7/RGPIO7/SPSCK2/ADP3
BKGD/MS/PTD6/RGPIO6
PTD5/RGPIO5/XTAL
PTD4/RGPIO4/EXTAL
VSS4
VDD4
Pin Assignments
Figure 3. Pin Assignments in 64-Pin LQFP Package
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
7
PTE0/KBI2P0/MISO2/ADP2
PTD7/RGPIO7/SPSCK2/ADP3
BKGD/MS/PTD6/RGPIO6
PTD5/RGPIO5/XTAL
PTD4/RGPIO4/EXTAL
VSS4
VDD4
43
42
41
40
39
38
37
44 PTE1/KBI2P1/MOSI2/ADP1
45 PTE2/KBI2P2/SS2/ADP0
46 PTE3/KBI2P3/TPM1CH0
47 PTE4/KBI2P4/CLKOUT/TPM1CH1
48 PTE5/KBI2P5/IRQ/TPM1CH2
Pin Assignments
VDD1 1
36 PTD3/RGPIO3/RXD2/ADP4
VSS1
2
35 PTD2/RGPIO2/TXD2/ADP5
PTA0/PHYCLK
3
34 PTD1/RGPIO1/RXD1/ADP6
PTA1/MII_MDIO/SDA2
4
33 PTD0/RGPIO0/TXD1/ADP7
PTA2/MII_MDC/SCL2
5
32 PTC7/SDA2/SPSCK1/ADP8
PTA3/MII_RXD3/TXD3
6
PTA4/MII_RXD2/RXD3
7
30 PTC5/MOSI1/ADP10
PTA5/MII_RXD1/SPSCK2
8
29 PTC4/IRQ/SS1/ADP11
PTA6/MII_RXD0/MISO2
9
28 VSSA
PTA7/MII_RX_DV/MOSI2
10
27 VDDA
PTB0/MII_RX_CLK/SS2
11
26 VSS3
PTB1/MII_RX_ER/TMRCLK1
12
25 VDD3
31 PTC6/SCL2/MISO1/ADP9
RESET/PTC3 24
PTC2/MII_CRS/SDA1 23
PTC1/MII_COL/SCL1 22
PTC0/MII_TXD3/TPM2CH2 21
PTB7/MII_TXD2/TPM2CH1 20
PTB6/MII_TXD1/TPM2CH0 19
PTB5/MII_TXD0/SPSCK1 18
PTB3/MII_TX_CLK/MOSI1 17
PTB3/MII_TX_CLK/MOSI1 16
PTB2/MII_TX_ER/SS1 15
VSS2 14
VDD2 13
48-Pin QFN
Figure 4. Pin Assignments in 48-Pin QFN Package
NOTE
There is no electrical connection to the flag for 48-pin QFN packages.
Table 2. Package Pin Assignments
80-Pin
64-Pin
48-Pin
Default Function
Alt 1
Alt 2
Alt 3
Comment
1
1
1
VDD1
—
—
—
—
2
2
2
VSS1
—
—
—
—
3
3
3
PTA0
PHYCLK
—
—
—
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
8
Freescale Semiconductor
Pin Assignments
Table 2. Package Pin Assignments (continued)
80-Pin
64-Pin
48-Pin
Default Function
Alt 1
Alt 2
Alt 3
Comment
4
4
4
PTA1
MII_MDIO
—
SDA2
—
5
5
5
PTA2
MII_MDC
—
SCL2
—
6
6
6
PTA3
MII_RXD3
TXD3
—
—
7
7
7
PTA4
MII_RXD2
RXD3
—
—
8
8
8
PTA5
MII_RXD1
SPSCK2
—
—
9
9
9
PTA6
MII_RXD0
MISO2
—
—
10
10
10
PTA7
MII_RX_DV
MOSI2
—
—
11
11
11
PTB0
MII_RX_CLK
SS2
—
—
12
12
12
PTB1
MII_RX_ER
—
TMRCLK1
—
13
13
—
PTF0/RGPIO8
—
FB_A19/FB_AD19
—
14
14
—
PTF1/RGPIO9
—
FB_A18/FB_AD18
—
RGPIO_ENB selects
between standard GPIO
and RGPIO
15
15
—
PTF2/RGPIO10
—
FB_A17/FB_AD17
—
16
16
—
PTF3/RGPIO11
—
FB_A16/FB_AD16
—
17
—
—
PTH0
—
FB_A15/FB_AD15
—
—
18
—
—
PTH1
—
FB_OE
—
—
19
—
—
PTH2
—
FB_D7
TMRCLK1
—
20
—
—
PTH3
—
FB_D6
TPM2CH0
—
21
17
13
VDD2
—
—
—
—
22
18
14
VSS2
—
—
—
—
23
19
15
PTB2
MII_TX_ER
SS1
—
—
24
20
16
PTB3
MII_TX_CLK
MOSI1
—
—
25
21
17
PTB4
MII_TX_EN
MISO1
—
—
26
22
18
PTB5
MII_TXD0
SPSCK1
—
—
27
23
19
PTB6
MII_TXD1
—
TPM2CH0
—
28
24
20
PTB7
MII_TXD2
—
TPM2CH1
—
29
25
21
PTC0
MII_TXD3
—
TPM2CH2
—
30
26
22
PTC1
MII_COL
—
SCL1
—
31
27
23
PTC2
MII_CRS
—
SDA1
—
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
9
Pin Assignments
Table 2. Package Pin Assignments (continued)
80-Pin
64-Pin
48-Pin
Default Function
Alt 1
Alt 2
Alt 3
Comment
32
28
24
RESET
PTC3
—
—
This pin is a
bi-directional open drain
pin and has an internal
pullup. There is no
clamp diode to VDD.
DSE and SRE port
controls for this bit have
no effect.
33
29
—
PTF4/RGPIO12
—
FB_D5
TMRCLK2
34
30
—
PTF5/RGPIO13
—
FB_D4
TPM2CH0
RGPIO_ENB selects
between standard GPIO
and RGPIO
35
31
—
PTF6/RGPIO14
—
FB_A14/FB_AD14
TPM2CH1
36
32
—
PTF7/RGPIO15
—
FB_A13/FB_AD13
TPM2CH2
37
—
—
PTH4
—
FB_A12/FB_AD12
—
—
38
—
—
PTH5
—
FB_A11/FB_AD11
—
—
39
—
—
PTH6
—
FB_A10/FB_AD10
TPM2CH1
—
40
—
—
PTH7
—
FB_A9/FB_AD9
TPM2CH2
—
41
33
25
VDD3
—
—
—
—
42
34
26
VSS3
—
—
—
—
43
35
27
VDDA
—
—
—
—
44
36
28
VSSA
—
—
—
—
45
37
29
PTC4
IRQ
SS1
ADP11
—
46
38
30
PTC5
—
MOSI1
ADP10
—
47
39
31
PTC6
SCL2
MISO1
ADP9
—
48
40
32
PTC7
SDA2
SPSCK1
ADP8
—
49
41
33
PTD0/RGPIO0
—
TXD1
ADP7
50
42
34
PTD1/RGPIO1
—
RXD1
ADP6
RGPIO_ENB selects
between standard GPIO
and RGPIO
51
43
35
PTD2/RGPIO2
—
TXD2
ADP5
52
44
36
PTD3/RGPIO3
—
RXD2
ADP4
53
45
—
PTG0
KBI1P0
FB_A8/FB_AD8
SCL2
—
54
46
—
PTG1
KBI1P1
FB_A7/FB_AD7
SDA2
—
55
47
—
PTG2
KBI1P2
FB_A6/FB_AD6
SCL1
—
56
48
—
PTG3
KBI1P3
FB_A5/FB_AD5
SDA1
—
57
—
—
PTG4
KBI1P4
FB_RW
—
—
58
—
—
PTG5
KBI1P5
FB_D3
—
—
59
—
—
PTG6
KBI1P6
FB_D2
—
—
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
10
Freescale Semiconductor
Electrical Characteristics
Table 2. Package Pin Assignments (continued)
1
80-Pin
64-Pin
48-Pin
Default Function
Alt 1
Alt 2
Alt 3
Comment
60
—
—
PTG7
KBI1P7
FB_D1
—
—
61
49
37
VDD4
—
—
—
—
62
50
38
VSS4
—
—
—
—
63
51
39
PTD4/RGPIO4
—
—
EXTAL
64
52
40
PTD5/RGPIO5
—
—
XTAL
RGPIO_ENB selects
between standard GPIO
and RGPIO
65
53
41
BKGD/MS
PTD6/RGPIO6
—
—
This pin has an internal
pullup. PTD6/RGPIO6
can only be
programmed as an
output.1
66
54
42
PTD7RGPIO7
—
SPSCK2
ADP3
RGPIO_ENB selects
between standard GPIO
and RGPIO
67
55
43
PTE0
KBI2P0
MISO2
ADP2
—
68
56
44
PTE1
KBI2P1
MOSI2
ADP1
—
69
57
45
PTE2
KBI2P2
SS2
ADP0
—
70
58
46
PTE3
KBI2P3
—
TPM1CH0
—
71
59
47
PTE4
KBI2P4
CLKOUT
TPM1CH1
—
72
60
48
PTE5
KBI2P5
IRQ
TPM1CH2
—
73
61
—
PTE6
KBI2P6
FB_D0
TXD3
—
74
62
—
PTE7
KBI2P7
FB_CS0
RXD3
—
75
63
—
PTJ0
FB_ALE
FB_CS1
—
—
76
64
—
PTJ1
—
FB_A4/FB_AD4
—
—
77
—
—
PTJ2
—
FB_A3/FB_AD3
—
—
78
—
—
PTJ3
—
FB_A2/FB_AD2
—
—
79
—
—
PTJ4
—
FB_A1/FB_AD1
—
—
80
—
—
PTJ5
—
FB_A0/FB_AD0
—
—
RGPIO_ENB selects between standard GPIO and RGPIO. When PTD6 is set as RGPIO output, and "1" is driven to PTD6 via
RGPIO function, a read of register RGPIODATA6 always returns a "0" because V1 RGPIO design looks for IO enable when the
return value of RGPIO function reads data. As PTD6 is set to RGPIO output only, it returns "0" always to RGPIODATA6, athough
PTD6 pin is driven to high.
3
Electrical Characteristics
3.1
Introduction
This section contains electrical and timing specifications for the MCF51CN128 series of microcontrollers available at the time
of publication.
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
11
Electrical Characteristics
3.2
Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better
understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate:
Table 3. Parameter Classifications
P
These parameters are guaranteed during production testing on each individual device.
C
These parameters are achieved by the design characterization by measuring a statistically relevant sample
size across process variations.
T
These parameters are achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted. All values shown in the typical column are within this
category.
D
These parameters are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the parameter tables where
appropriate.
3.3
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the
limits specified in Table 4 may affect device reliability or cause permanent damage to the device. For functional operating
conditions, refer to the remaining tables in this section.
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised
that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this
high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for
instance, either VSS or VDD) or the programmable pull-up resistor associated with the pin is enabled.
Table 4. Absolute Maximum Ratings
Rating
Symbol
Value
Unit
Supply voltage
VDD
–0.3 to +3.8
V
Maximum current into VDD
IDD
120
mA
Digital input voltage
VIn
–0.3 to VDD + 0.3
V
Instantaneous maximum current
Single pin limit (applies to all port pins)1, 2, 3
ID
± 25
mA
Tstg
–55 to 150
°C
Storage temperature range
1
Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp
voltages, then use the larger of the two resistance values.
2 All functional non-supply pins are internally clamped to V
SS and VDD.
3 Power supply must maintain regulation within operating V
DD range during instantaneous and
operating maximum current conditions. If positive injection current (VIn > VDD) is greater than
IDD, the injection current may flow out of VDD and could result in external power supply going
out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if
no system clock is present, or if the clock rate is very low (which would reduce overall power
consumption).
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
12
Freescale Semiconductor
Electrical Characteristics
3.4
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power
dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and
it is user-determined rather than being controlled by the MCU design. To take PI/O into account in power calculations, determine
the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of
unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small.
Table 5. Thermal Characteristics
Rating
Operating temperature range
(packaged)
Maximum junction temperature
Symbol
Value
Unit
TA
TL to TH
(–40 to 85 or 0 to 70)1
°C
TJM
95
°C
Thermal resistance
Single-layer board
48-pin QFN
81
θJA
64-pin LQFP
80-pin LQFP
69
°C/W
60
Thermal resistance
Four-layer board
48-pin QFN
26
θJA
64-pin LQFP
80-pin LQFP
1
50
°C/W
47
Depending on device.
The average chip-junction temperature (TJ) in °C can be obtained from:
TJ = TA + (PD × θJA)
Eqn. 1
where:
TA = Ambient temperature, °C
θJA = Package thermal resistance, junction-to-ambient, °C/W
PD = Pint + PI/O
Pint = IDD × VDD, Watts — chip internal power
PI/O = Power dissipation on input and output pins — user determined
For most applications, PI/O 2.7 V
0.70 x VDD
—
—
VDD > 1.8 V
0.85 x VDD
—
—
VDD > 2.7 V
—
—
0.35 x VDD
VDD >1.8 V
—
—
0.30 x VDD
All I/O pins,
low-drive strength
P
All I/O pins,
high-drive strength
T
VOH
C
3
4
D
Output high
current
C
Output low
voltage
Max total IOH for all
ports
IOHT
All I/O pins,
low-drive strength
P
All I/O pins,
high-drive strength
T
VOL
C
Max total IOL for all
ports
Output low
current
5
D
P Input high
voltage
C
all digital inputs
6
P Input low voltage
all digital inputs
IOLT
VIH
7
VIL
C
8
C Input hysteresis
9
P
Input leakage
current
10
P
Hi-Z (off-state)
leakage current
11
P
Pull resistors
all digital inputs, when
enabled
Single pin limit
12
DC injection
4, 5, 6
D current
V
mA
V
mA
V
all digital inputs
Vhys
—
0.06 x VDD
—
—
mV
all input only pins
(Per pin)
|IIn|
VIn = VDD or VSS
—
0.1
1
μA
all input/output
(per pin)
|IOZ|
VIn = VDD or VSS
—
0.1
1
μA
RP
—
17.5
—
52.5
kΩ
–0.2
—
0.2
mA
–5
—
5
mA
CIn
—
—
8
pF
Total MCU limit, includes
sum of all stressed pins
IIC
VIN < VSS, VIN > VDD
13
C Input Capacitance, all pins
14
C POR re-arm voltage7
VPOR
0.9
1.4
1.79
V
15
D POR re-arm time
tPOR
10
—
—
μs
16
P
2.15
2.24
2.32
2.39
2.45
2.49
V
Low-voltage detection threshold —
high range8
VLVDH9
VDD falling
VDD rising
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
15
Electrical Characteristics
Table 8. DC Characteristics (continued)
Num C
Characteristic
Symbol
Condition
Min
Typ1
Max
Unit
17
P
Low-voltage detection threshold —
low range8
VLVDL
VDD falling
VDD rising
1.70
1.80
1.83
1.89
1.95
2.00
V
18
P
Low-voltage warning threshold —
high range8
VLVWH
VDD falling
VDD rising
2.50
2.50
2.62
2.62
2.70
2.70
V
19
P
Low-voltage warning threshold —
low range8
VLVWL
VDD falling
VDD rising
2.25
2.29
2.32
2.39
2.45
2.49
V
20
P Bandgap Voltage Reference10
VBG
—
1.15
1.17
1.18
V
Typical values are measured at 25 °C. Characterized, not tested
As an exception, the Fast Ethernet Controller (FEC) is only operational above the operating voltage of 3 V.
3
As the supply voltage rises, the LVD circuit will hold the MCU in reset until the supply has risen above VLVDL.
4
All functional non-supply pins are internally clamped to VSS and VDD.
5 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values for positive and negative clamp voltages, then use the larger of the two values.
6 Power supply must maintain regulation within operating V
DD range during instantaneous and operating maximum current
conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result
in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if
clock rate is very low (which would reduce overall power consumption).
7 Maximum is highest voltage that POR is guaranteed.
8 Low voltage detection and warning limits measured at 1 MHz bus frequency.
9 Run at 1 MHz bus frequency
10 Factory trimmed at V
DD = 3.3 V, Temp = 25 °C
1
PULL-UP RESISTOR TYPICALS
85°C
25°C
–40°C
PULL-UP RESISTOR (kΩ)
40
35
30
25
20
1.8
2
2.2
2.4
2.6 2.8
VDD (V)
3
3.2
3.4
3.6
PULL-DOWN RESISTANCE (kΩ)
2
40
35
PULL-DOWN RESISTOR TYPICALS
85°C
25°C
–40°C
30
25
20
1.8
2.3
2.8
VDD (V)
3.3
3.6
Figure 5. Pull-up and Pull-down Typical Resistor Values
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
16
Freescale Semiconductor
Electrical Characteristics
TYPICAL VOL VS IOL AT VDD = 3.3 V
1.2
85°C
25°C
–40°C
1
0.15
VOL (V)
0.8
VOL (V)
TYPICAL VOL VS VDD
0.2
0.6
0.4
0.2
0.1
85°C, IOL = 2 mA
25°C, IOL = 2 mA
–40°C, IOL = 2 mA
0.05
0
0
0
5
10
IOL (mA)
15
1
20
2
3
VDD (V)
4
Figure 6. Typical Low-Side Driver (Sink) Characteristics — Low Drive (PTxDSn = 0)
0.4
85°C
25°C
–40°C
0.8
0.4
0.2
0.2
0.1
0
0
0
85°C
25°C
–40°C
0.3
0.6
VOL (V)
VOL (V)
TYPICAL VOL VS VDD
TYPICAL VOL VS IOL AT VDD = 3.3 V
1
10
20
30
IOL = 10 mA
IOL = 6 mA
IOL = 3 mA
1
2
3
4
VDD (V)
IOL (mA)
Figure 7. Typical Low-Side Driver (Sink) Characteristics — High Drive (PTxDSn = 1)
TYPICAL VDD – VOH VS IOH AT VDD = 3.3 V
0.25
85°C
25°C
–40°C
1
VDD – VOH (V)
VDD – VOH (V)
1.2
0.8
0.6
0.4
TYPICAL VDD – VOH VS VDD AT SPEC IOH
85°C, IOH = 2 mA
25°C, IOH = 2 mA
–40°C, IOH = 2 mA
0.2
0.15
0.1
0.05
0.2
0
0
0
–5
–10
IOH (mA))
–15
–20
1
2
VDD (V)
3
4
Figure 8. Typical High-Side (Source) Characteristics — Low Drive (PTxDSn = 0)
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
17
Electrical Characteristics
TYPICAL VDD – VOH VS VDD AT SPEC IOH
TYPICAL VDD – VOH VS IOH AT VDD = 3.3 V
0.8
85°C
25°C
–40°C
0.6
0.4
0.2
0
0
–5
–10
–15
–20
IOH (mA)
–25
85°C
25°C
–40°C
0.3
VDD – VOH (V)
VDD – VOH (V)
0.4
0.2
IOH = –10 mA
IOH = –6 mA
0.1
IOH = –3 mA
0
–30
1
2
3
4
VDD (V)
Figure 9. Typical High-Side (Source) Characteristics — High Drive (PTxDSn = 1)
3.7
Supply Current Characteristics
This section includes information about power supply current in various operating modes.
Table 9. Supply Current Characteristics
Num
C
P
T
Parameter
Symbol
T
C
T
Run supply current
FEI mode, all modules off
2
T
T
Run supply current
LPRS=0, all modules off
3
RIDD
T
C
T
Run supply current
LPRS=1, all modules off, running from
Flash
RIDD
T
C
49
—
8 MHz
21
—
1 MHz
4.6
—
25 MHz
44
47
36
—
8 MHz
15.5
—
1 MHz
3.9
—
203
—
3.3
3.3
3.3
16 kHz
FBELP
154
—
50
—
11
13.7
4.57
—
8 MHz
2
—
1 MHz
0.73
—
16 kHz
FBELP
3.3
20 MHz
WIDD
T
75
25 MHz
Wait mode supply current
FEI mode, all modules off
5
60
16 kHz
FBILP
T
4
Max
20 MHz
RIDD
T
Typ1
20 MHz
RIDD
T
VDD
(V)
25 MHz
Run supply current
FEI mode, all modules on
1
Bus
Freq
3.3
mA
–40 to 85 °C
mA
–40 to 85 °C
μA
–40 to 85 °C
μA
–40 to 85 °C
μA
–-40 to 85 °C
0 to 70 °C
0.35
P
C
Temp
(°C)
11
Stop2 mode supply current
3.3
6
Unit
45
S2IDD
μA
n/a
1.8
12
0 to 70 °C
16.2
–40 to 85 °C
0.35
C
–40 to 85 °C
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
18
Freescale Semiconductor
Electrical Characteristics
Table 9. Supply Current Characteristics (continued)
Num
C
C
P
Parameter
Symbol
Bus
Freq
3.3
0.52
n/a
1.8
Unit
Temp
(°C)
0 to 70 °C
μA
–40 to 85 °C
15
0 to 70 °C
32.4
–40 to 85 °C
0.52
C
1
Max
55
S3IDD
C
Typ1
14
Stop3 mode supply current
No clocks active
7
VDD
(V)
8
T
EREFSTEN=1
32 kHz
500
—
nA
–40 to 85 °C
9
T
IREFSTEN=1
32 kHz
70
—
μA
–40 to 85 °C
10
T
TPM PWM
100 Hz
12
—
μA
–40 to 85 °C
11
T
15
—
μA
–40 to 85 °C
12
T
13
14
Low power
mode adders:
SCI, SPI, or IIC
—
300 bps
3.3
RTC using LPO
1 kHz
200
—
nA
–40 to 85 °C
T
RTC using
ICSERCLK
32 kHz
1
—
μA
–40 to 85 °C
T
LVD
n/a
100
—
μA
–40 to 85 °C
Data in Typical column was characterized at 3.3 V, 25 °C or is typical recommended value.
Figure 10. Typical Run IDD for FBE and FEI, IDD vs. VDD
(ADC off, All Other Modules Enabled)
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
19
Electrical Characteristics
3.8
External Oscillator (XOSC) Characteristics
Reference Figure 11 and Figure 12 for crystal or resonator circuits.
Table 10. XOSC and ICS Specifications (Temperature Range = –40 to 85 °C Ambient)
Num
C
Characteristic
1
Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1)
Low range (RANGE = 0)
C
High range (RANGE = 1), high gain (HGO = 1)
High range (RANGE = 1), low power (HGO = 0)
2
D
3
Feedback resistor
Low range, low power (RANGE=0, HGO=0)2
D
Low range, High Gain (RANGE=0, HGO=1)
High range (RANGE=1, HGO=X)
4
Series resistor —
Low range, low power (RANGE = 0, HGO = 0)2
Low range, high gain (RANGE = 0, HGO = 1)
High range, low power (RANGE = 1, HGO = 0)
D
High range, high gain (RANGE = 1, HGO = 1)
≥ 8 MHz
4 MHz
1 MHz
5
6
Load capacitors
Low range (RANGE=0), low power (HGO=0)
Other oscillator settings
Crystal start-up time 4
Low range, low power
Low range, high power
C
High range, low power
High range, high power
D
Square wave input clock frequency (EREFS = 0, ERCLKEN = 1)
External with FLL / PLL enabled (FEE / PEE)
External with bypass (FBE.FBELP,PBE, PBELP)
Symbol
Min
Typ1
Max
Unit
flo
fhi
fhi
32
1
1
—
—
—
38.4
25
8
kHz
MHz
MHz
See Note2
See Note3
C1,C2
RF
RS
t
CSTL
t
CSTH
fextal
—
—
—
—
10
1
—
—
—
—
—
—
—
0
100
—
—
—
Ω
—
—
—
0
0
0
0
10
20
ΚΩ
—
—
—
—
200
400
5
15
—
—
—
—
ms
0.03125
0
—
—
50.33
50.33
MHz
MHz
MΩ
Data in Typical column was characterized at 3.3 V, 25 °C or is typical recommended value.
Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE=HGO=0.
3
See crystal or resonator manufacturer’s recommendation.
4 Proper PC board layout procedures must be followed to achieve specifications.
1
2
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
20
Freescale Semiconductor
Electrical Characteristics
XOSC
EXTAL
XTAL
RS
RF
C1
Crystal or Resonator
C2
Figure 11. Typical Crystal or Resonator Circuit: High Range and Low Range/High Gain
XOSC
EXTAL
XTAL
Crystal or Resonator
Figure 12. Typical Crystal or Resonator Circuit: Low Range/Low Gain
3.9
Multipurpose Clock Generator (MCG) Specifications
Table 11. MCG Frequency Specifications (Temperature Range = –40 to 125 °C Ambient)
Num C
Rating
Symbol
Min
Typical
Max
Unit
fint_ft
—
32.768
—
kHz
1
Internal reference frequency - factory
P trimmed at VDD = and
temperature = 25 °C
2
P
Average internal reference frequency untrimmed 1
fint_ut
25
—
41.66
kHz
3
P
Average internal reference frequency user trimmed
fint_t
31.25
—
39.06
kHz
4
D Internal reference startup time
tirefst
—
60
100
us
5
DCO output frequency range untrimmed 1
—
value provided for reference:
fdco_ut = 1024 X fint_ut
fdco_ut
25.6
33.48
42.66
MHz
6
P DCO output frequency range - trimmed
fdco_t
32
—
40
MHz
7
Resolution of trimmed DCO output
C frequency at fixed voltage and
temperature (using FTRIM)
Δfdco_res_t
—
± 0.1
± 0.2
%fdco
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
21
Electrical Characteristics
Table 11. MCG Frequency Specifications (continued)(Temperature Range = –40 to 125 °C Ambient)
Num C
Rating
Symbol
Min
Typical
Max
Unit
Δfdco_res_t
—
± 0.2
± 0.4
%fdco
8
Resolution of trimmed DCO output
C frequency at fixed voltage and
temperature (not using FTRIM)
9
Total deviation of trimmed DCO output
P frequency over voltage and
temperature
Δfdco_t
—
+ 0.5
-1.0
±2
%fdco
10
Total deviation of trimmed DCO output
C frequency over fixed voltage and
temperature range of 0 - 70 °C
Δfdco_t
—
± 0.5
±1
%fdco
11
C FLL acquisition time 2
tfll_acquire
—
—
1
ms
12
D PLL acquisition time 3
tpll_acquire
—
—
1
ms
13
C
CJitter
—
0.02
0.2
%fdco
14
D VCO operating frequency
fvco
7.0
—
55.0
MHz
15
D Lock entry frequency tolerance5
Dlock
± 1.49
—
± 2.98
%
16
D Lock exit frequency tolerance6
Dunl
± 4.47
—
± 5.97
%
17
D Lock time - FLL
tfll_lock
—
—
tfll_acquire+
1075(1/fint_t
s
Long term Jitter of DCO output clock
(averaged over 2ms interval) 4
)
18
tpll_lock
D Lock time - PLL
—
—
tpll_acquire+
1075(1/fpll_r
s
ef)
19
Loss of external clock minimum
D frequency - RANGE = 0
floc_low
(3/5) x fint
—
—
kHz
1
TRIM register at default value (0x80) and FTRIM control bit at default value (0x0).
This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing
from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference,
this specification assumes it is already running.
3 This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is
already running.
4
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBUS.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a
given interval.
5 Below D
lock minimum, the MCG is guaranteed to enter lock. Above Dlock maximum, the MCG does not enter lock. But if the
MCG is already in lock, then the MCG may stay in lock.
2
6
Below Dunl minimum, the MCG does not exit lock if already in lock. Above Dunl maximum, the MCG is guaranteed to exit lock.
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
22
Freescale Semiconductor
Electrical Characteristics
3.10
Mini-FlexBus Timing Specifications
A multi-function external bus interface called Mini-FlexBus is provided with basic functionality to interface to slave-only
devices up to a maximum bus frequency of 25.1666 MHz. It can be directly connected to asynchronous or synchronous devices
such as external boot ROMs, flash memories, gate-array logic, or other simple target (slave) devices with little or no additional
circuitry. For asynchronous devices a simple chip-select based interface can be used.
All processor bus timings are synchronous; that is, input setup/hold and output delay are given in respect to the rising edge of
a reference clock, MB_CLK. The MB_CLK frequency is half the internal system bus frequency.
The following timing numbers indicate when data is latched or driven onto the external bus, relative to the Mini-FlexBus output
clock (MB_CLK). All other timing relationships can be derived from these values.
Table 12. Mini-FlexBus AC Timing Specifications
1
2
Num
C
Characteristic
Min
Max
Unit
Notes
—
—
Frequency of Operation
—
25.1666
MHz
—
MB1
D
Clock Period
39.73
—
ns
—
MB2
P
Output Valid
—
20
ns
1
MB3
D
Output Hold
1.0
—
ns
1
MB4
P
Input Setup
22
—
ns
2
MB5
D
Input Hold
10
—
ns
2
Specification is valid for all MB_A[19:0], MB_D[7:0], MB_CS[1:0], MB_OE, MB_R/W, and MB_ALE.
Specification is valid for all MB_D[7:0].
S0
S1
S2
S3
S0
FB_CLK
MB1
FB_A[19:16]
MB3
ADDR[19:0]
MB2
8-bit Non-Mux’d Bus
FB_D[7:0]
ADDR[31:24]
MB5
DATA[7:0]
MB4
FB_AD[19:16]
ADDR[19:16]
16-bit Mux’d Bus
FB_AD[15:0]
ADDR[15:0]
DATA[15:0]
FB_R/W
FB_ALE
FB_CSn, FB_OE
Figure 13. Mini-FlexBus Read Timing
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
23
Electrical Characteristics
S0
S1
S2
S3
S0
FB_CLK
MB1
MB3
ADDR[19:8]
FB_AD[19:8]
MB2
8-bit Non-Mux’d Bus
FB_AD[7:0]
ADDR[7:0]
FB_AD[19:16]
DATA[7:0]
ADDR[19:16]
16-bit Mux’d Bus
FB_AD[15:0]
ADDR[15:0]
DATA[15:0]
FB_R/W
FB_ALE
FB_CSn
FB_OE
Figure 14. Mini-FlexBus Write Timing
3.11
Fast Ethernet Timing Specifications
The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing
specs/constraints for the physical interface.
3.11.1
Receive Signal Timing Specifications
The following timing specs meet the requirements for MII and 7-Wire style interfaces for a range of transceiver devices.
Table 13. Receive Signal Timing
MII Mode
Num
C
Characteristic
Unit
Min
Max
—
—
RXCLK frequency
—
25
MHz
E1
P
RXD[3:0], RXDV, RXER to RXCLK setup
5
—
ns
E2
D
RXCLK to RXD[3:0], RXDV, RXER hold
5
—
ns
E3
D
RXCLK pulse width high
35%
65%
RXCLK period
E4
D
RXCLK pulse width low
35%
65%
RXCLK period
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
24
Freescale Semiconductor
Electrical Characteristics
E4
RXCLK (Input)
E3
E1
RXD[n:0]
RXDV,
RXER
E2
Valid Data
Figure 15. MII Receive Signal Timing Diagram
3.11.2
Transmit Signal Timing Specifications
Table 14. Transmit Signal Timing
MII Mode
Num
C
Characteristic
Unit
Min
Max
—
—
TXCLK frequency
—
25
MHz
E5
D
TXCLK to TXD[3:0], TXEN, TXER invalid
5
—
ns
E6
P
TXCLK to TXD[3:0], TXEN, TXER valid
—
25
ns
E7
D
TXCLK pulse width high
35%
65%
tTXCLK
E8
D
TXCLK pulse width low
35%
65%
tTXCLK
E8
TXCLK (Input)
E7
E6
E5
TXD[n:0]
TXEN,
TXER
Valid Data
Figure 16. MII Transmit Signal Timing Diagram
3.11.3
Asynchronous Input Signal Timing Specifications
Table 15. MII Transmit Signal Timing
Num
C
E9
D
Characteristic
CRS, COL minimum pulse width
Min
Max
Unit
1.5
—
TXCLK period
CRS, COL
E9
Figure 17. MII Async Inputs Timing Diagram
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
25
Electrical Characteristics
3.11.4
MII Serial Management Timing Specifications
Table 16. MII Serial Management Channel Signal Timing
Num
C
E10
D
E11
Characteristic
Symbol
Min
Max
Unit
MDC cycle time
tMDC
400
—
ns
D
MDC pulse width
—
40
60
% tMDC
E12
D
MDC to MDIO output valid
—
—
375
ns
E13
D
MDC to MDIO output invalid
—
30
—
ns
E14
D
MDIO input to MDC setup
—
5
—
ns
E15
D
MDIO input to MDC hold
—
15
—
ns
E10
E11
MDC (Output)
E11
E13
E12
Valid Data
MDIO (Output)
E14
MDIO (Input)
E15
Valid Data
Figure 18. MII Serial Management Channel TIming Diagram
3.12
AC Characteristics
This section describes timing characteristics for each peripheral system.
3.12.1
Control Timing
Table 17. Control Timing
Num
C
Rating
1
D
Bus frequency (tcyc = 1/fBus)
VDD > 2.7 V
2.7 V > VDD > 2.1 V
2.1 V > VDD > 1.8 V
2
D
Internal low power oscillator period
width2
Symbol
Min
Typ1
Max
dc
dc
dc
—
—
—
50.33
40
20
Unit
fBus
tLPO
700
—
1300
μs
textrst
100
—
—
ns
MHz
3
D
External reset pulse
4
D
Reset low drive
trstdrv
34 x tcyc
—
—
ns
5
D
BKGD/MS setup time after issuing background debug
force reset to enter user or BDM modes
tMSSU
500
—
—
ns
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
26
Freescale Semiconductor
Electrical Characteristics
Table 17. Control Timing (continued)
Symbol
Min
Typ1
Max
Unit
tMSH
100
—
—
μs
IRQ pulse width
Asynchronous path2
Synchronous path4
tILIH, tIHIL
100
2 x tcyc
—
—
—
—
ns
Keyboard interrupt pulse width
Asynchronous path2
Synchronous path4
tILIH, tIHIL
100
2 x tcyc
—
—
—
—
ns
Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)5
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
tRise, tFall
—
—
16
23
—
—
Port rise and fall time —
High output drive (PTxDS = 1) (load = 50 pF)
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
tRise, tFall
—
—
5
9
—
—
Stop3 recovery time, from interrupt event to vector fetch
tSTPREC
—
6
10
Num
C
6
D
BKGD/MS hold time after issuing background debug
force reset to enter user or BDM modes 3
7
D
8
D
9
10
Rating
ns
C
C
ns
μs
Typical values are based on characterization data at VDD = 3.3 V, 25 °C unless otherwise stated.
This is the shortest pulse that is guaranteed to be recognized as a reset or interrupt pin request. Shorter pulses are not
guaranteed to override reset requests from internal sources.
3 To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of t
MSH after VDD
rises above VLVD.
4 This is the minimum assertion time in which the interrupt may be recognized. The correct protocol is to assert the interrupt
request until it is explicitly negated by the interrupt service routine.
5 Timing is shown with respect to 20% V
DD and 80% VDD levels. Temperature range –40 °C to 85 °C.
1
2
textrst
RESET PIN
Figure 19. Reset Timing
tIHIL
KBIPx
IRQ/KBIPx
tILIH
Figure 20. IRQ/KBIPx Timing
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
27
Electrical Characteristics
3.12.2
TPM Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the
optional external source to the timer counter. These synchronizers operate from the current bus rate clock.
Table 18. TPM Input Timing
No.
C
Function
Symbol
Min
Max
Unit
1
D
External clock frequency
fTCLK
0
fBus/4
Hz
2
D
External clock period
tTCLK
4
—
tcyc
3
D
External clock high time
tclkh
1.5
—
tcyc
4
D
External clock low time
tclkl
1.5
—
tcyc
5
D
Input capture pulse width
tICPW
1.5
—
tcyc
tTCLK
tclkh
TCLK
tclkl
Figure 21. Timer External Clock
tICPW
TPMCHn
TPMCHn
tICPW
Figure 22. Timer Input Capture Pulse
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
28
Freescale Semiconductor
Electrical Characteristics
3.12.3
SPI Timing
Table 19 and Figure 23 through Figure 26 describe the timing requirements for the SPI system.
Table 19. SPI Timing
No.
C
Function
Symbol
Min
Max
Unit
—
D
Operating frequency
Master
Slave
fBus/2048
0
fBus/2
fBus/4
Hz
Hz
1
D
SPSCK period
Master
Slave
2
4
2048
—
tcyc
tcyc
D
Enable lead time
Master
Slave
tLead
2
1/2
1
—
—
tSPSCK
tcyc
D
Enable lag time
Master
Slave
tLag
3
1/2
1
—
—
tSPSCK
tcyc
4
D
Clock (SPSCK) high or low time
Master
Slave
tcyc – 30
tcyc – 30
1024 tcyc
—
ns
ns
D
Data setup time (inputs)
Master
Slave
tSU
5
15
15
—
—
ns
ns
D
Data hold time (inputs)
Master
Slave
tHI
6
0
25
—
—
ns
ns
7
D
Slave access time
ta
—
1
tcyc
8
D
Slave MISO disable time
tdis
—
1
tcyc
9
D
Data valid (after SPSCK edge)
Master
Slave
—
—
25
25
ns
ns
10
D
Data hold time (outputs)
Master
Slave
0
0
—
—
ns
ns
11
D
Rise time
Input
Output
tRI
tRO
—
—
tcyc – 25
25
ns
ns
12
D
Fall time
Input
Output
tFI
tFO
—
—
tcyc – 25
25
ns
ns
fop
tSPSCK
tWSPSCK
tv
tHO
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
29
Electrical Characteristics
SS1
(OUTPUT)
2
1
SPSCK
(CPOL = 0)
(OUTPUT)
3
11
4
4
12
SPSCK
(CPOL = 1)
(OUTPUT)
5
MISO
(INPUT)
6
MSB IN2
BIT 6 . . . 1
9
9
MOSI
(OUTPUT)
LSB IN
MSB OUT2
10
BIT 6 . . . 1
LSB OUT
NOTES:
1. SS output mode (DDS7 = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 23. SPI Master Timing (CPHA = 0)
SS(1)
(OUTPUT)
1
2
12
11
11
12
3
SPSCK
(CPOL = 0)
(OUTPUT)
4
4
SPSCK
(CPOL = 1)
(OUTPUT)
5
MISO
(INPUT)
6
MSB IN(2)
9
MOSI
(OUTPUT) PORT DATA
BIT 6 . . . 1
LSB IN
10
MASTER MSB OUT(2)
BIT 6 . . . 1
MASTER LSB OUT
PORT DATA
NOTES:
1. SS output mode (DDS7 = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 24. SPI Master Timing (CPHA =1)
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
30
Freescale Semiconductor
Electrical Characteristics
SS
(INPUT)
1
12
11
11
12
3
SPSCK
(CPOL = 0)
(INPUT)
2
4
4
SPSCK
(CPOL = 1)
(INPUT)
8
7
MISO
(OUTPUT)
MSB OUT
SLAVE
BIT 6 . . . 1
SLAVE LSB OUT
SEE
NOTE
6
5
MOSI
(INPUT)
10
10
9
BIT 6 . . . 1
MSB IN
LSB IN
NOTE:
1. Not defined but normally MSB of character just received
Figure 25. SPI Slave Timing (CPHA = 0)
SS
(INPUT)
1
3
2
12
11
11
12
SPSCK
(CPOL = 0)
(INPUT)
4
4
SPSCK
(CPOL = 1)
(INPUT)
9
MISO
(OUTPUT)
SEE
NOTE
7
MOSI
(INPUT)
SLAVE
10
MSB OUT
5
BIT 6 . . . 1
8
SLAVE LSB OUT
6
MSB IN
BIT 6 . . . 1
LSB IN
NOTE:
1. Not defined but normally LSB of character just received
Figure 26. SPI Slave Timing (CPHA = 1)
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
31
Electrical Characteristics
3.12.4
ADC Characteristics
Table 20. 12-bit ADC Operating Conditions
C
Characteristic
Supply voltage
Conditions
Absolute
D
2
Delta to VDD (VDD-VDDAD)
Delta to VSS (VSS-VSSAD)2
Symb
Min
Typ1
Max
Unit
VDDAD
1.8
—
3.6
V
ΔVDDAD
-100
0
+100
mV
ΔVSSAD
-100
0
+100
mV
D
Ground voltage
D
Ref Voltage High
VREFH
1.8
VDDAD
VDDAD
V
D
Ref Voltage Low
VREFL
VSSAD
VSSAD
VSSAD
V
D
Input Voltage
VADIN
VREFL
—
VREFH
V
C
Input
Capacitance
CADIN
—
4.5
5.5
C
Input Resistance
RADIN
—
5
7
—
—
—
—
2
5
10 bit mode
fADCK > 4MHz
fADCK < 4MHz
—
—
—
—
5
10
8 bit mode (all valid fADCK)
—
—
10
0.4
—
8.0
0.4
—
4.0
Analog Source
Resistance
C
D
12 bit mode
fADCK > 4MHz
fADCK < 4MHz
ADC Conversion High Speed (ADLPC=0)
Clock Freq.
Low Power (ADLPC=1)
Comment
pF
kΩ
RAS
External to MCU
kΩ
fADCK
MHz
Typical values assume VDDAD = 3.3 V, Temp = 25 °C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
2
DC potential difference.
1
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
32
Freescale Semiconductor
Electrical Characteristics
SIMPLIFIED
INPUT PIN EQUIVALENT
ZADIN
CIRCUIT
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
due to
input
protection
ZAS
RAS
RADIN
ADC SAR
ENGINE
+
VADIN
VAS
CAS
+
–
–
RADIN
INPUT PIN
RADIN
INPUT PIN
RADIN
INPUT PIN
CADIN
Figure 27. ADC Input Impedance Equivalency Diagram
Table 21. 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD)
C
Symb
Min
Typ1
Max
Supply Current
ADLPC=1
ADLSMP=1
ADCO=1
T
IDDAD
—
120
—
Supply Current
ADLPC=1
ADLSMP=0
ADCO=1
T
Supply Current
ADLPC=0
ADLSMP=1
ADCO=1
T
Supply Current
ADLPC=0
ADLSMP=0
ADCO=1
T
Characteristic
Conditions
Unit
Comment
μA
IDDAD
—
202
—
μA
IDDAD
—
288
—
μA
IDDAD
—
0.532
1
mA
Supply Current
Stop, Reset, Module Off
D
IDDAD
—
0.007
0.8
ADC
Asynchronous
Clock Source
High Speed (ADLPC=0)
P
fADACK
2
3.3
5
Low Power (ADLPC=1)
C
1.25
2
3.3
μA
tADACK = 1/fADACK
MHz
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
33
Electrical Characteristics
Table 21. 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) (continued)
C
Symb
Min
Typ1
Max
Unit
Comment
P
tADC
—
20
—
—
40
—
ADCK
cycles
—
3.5
—
—
23.5
—
See the ADC
chapter in the
MCF51CN128
Reference Manual
for conversion time
variances
—
±3.0
—
P
—
±1
±2.5
8 bit mode
T
—
±0.5
±1.0
12 bit mode
T
—
±1.75
—
10 bit mode3
P
—
±0.5
±1.0
8 bit mode3
T
—
±0.3
±0.5
12 bit mode
T
—
±1.5
—
10 bit mode
P
—
±0.5
±1.0
8 bit mode
T
—
±0.3
±0.5
—
±1.5
—
Characteristic
Conditions
Conversion Time Short Sample (ADLSMP=0)
(Including
Long Sample (ADLSMP=1)
sample time)
Sample Time
Short Sample (ADLSMP=0)
P
Long Sample (ADLSMP=1)
C
Total Unadjusted 12 bit mode
Error
10 bit mode
Differential
Non-Linearity
Integral
Non-Linearity
C
T
tADS
ETUE
DNL
INL
Zero-Scale Error 12 bit mode
T
10 bit mode
P
—
±0.5
±1.5
8 bit mode
T
—
±0.5
±0.5
12 bit mode
T
—
±1.0
—
10 bit mode
P
—
±0.5
±1
8 bit mode
T
—
±0.5
±0.5
12 bit mode
D
—
-1 to 0
—
10 bit mode
—
—
±0.5
8 bit mode
—
—
±0.5
—
±2
—
10 bit mode
—
±0.2
±4
8 bit mode
—
±0.1
±1.2
—
1.646
—
—
1.769
—
—
701.2
—
Full-Scale Error
Quantization
Error
Input Leakage
Error
Temp Sensor
Slope
Temp Sensor
Voltage
12 bit mode
D
-40°C to 25°C
D
EZS
EFS
EQ
EIL
m
25°C to 85°C
25°C
D VTEMP25
ADCK
cycles
LSB2
Includes
Quantization
LSB2
LSB2
LSB2
VADIN = VSSAD
LSB2
VADIN = VDDAD
LSB2
LSB2
Pad leakage4 *
RAS{test=pad leakage
test}
mV/°C
mV
Typical values assume VDDAD = 3.3 V, Temp = 25 °C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
2 1 LSB = (V
N
REFH - VREFL)/2
3
Monotonicity and No-Missing-Codes guaranteed in 10 bit and 8 bit modes
4 Based on input pad leakage current. Refer to pad electricals.
1
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
34
Freescale Semiconductor
Electrical Characteristics
3.12.5
Flash Specifications
This section provides details about program/erase times and program-erase endurance for the flash memory.
Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed
information about program/erase operations, see the Memory section of the MCF51CN128 Reference Manual.
Table 22. Flash Characteristics
C
Characteristic
Symbol
Min
Typical
Max
Unit
D
Supply voltage for program/erase
-40 °C to 85 °C
Vprog/erase
1.8
—
3.6
V
D
Supply voltage for read operation
VRead
1.8
—
3.6
V
fFCLK
150
—
200
kHz
tFcyc
5
—
6.67
μs
frequency1
D
Internal FCLK
D
Internal FCLK period (1/FCLK)
P
Longword program time (random location)(2)
mode)(2)
tprog
9
tFcyc
P
Longword program time (burst
tBurst
4
tFcyc
P
Page erase
time2
tPage
4000
tFcyc
P
Mass erase
time(2)
tMass
20,000
tFcyc
D
Longword program current3
D
Page erase current
3
RIDDBP
—
9.7
—
mA
RIDDPE
—
7.6
—
mA
10,000
—
—
100,000
—
—
cycles
15
100
—
years
endurance4
C
Program/erase
TL to TH = –40°C to + 85°C
T = 25°C
C
Data retention5
tD_ret
1
The frequency of this clock is controlled by a software setting.
These values are hardware state machine controlled. User code does not need to count cycles. This information supplied
for calculating approximate time to program and erase.
3
The program and erase currents are additional to the standard run IDD. These values are measured at room temperatures
with VDD = 3.3 V, bus frequency = 8.0 MHz.
4 Typical endurance for flash was evaluated for this product family on the HC9S12Dx64. For additional information on
how Freescale defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile
Memory.
5 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and
de-rated to 25 °C using the Arrhenius equation. For additional information on how Freescale defines typical data retention,
refer to Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory.
2
3.13
EMC Performance
Electromagnetic compatibility (EMC) performance is highly dependent on the environment in which the MCU resides. Board
design and layout, circuit topology choices, location and characteristics of external components as well as MCU software
operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such
as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC
performance.
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
35
Ordering Information
3.13.1
Radiated Emissions
Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell method in accordance
with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed with the microcontroller installed on a
custom EMC evaluation board while running specialized EMC test software. The radiated emissions from the microcontroller
are measured in a TEM cell in two package orientations (North and East). For more detailed information concerning the
evaluation results, conditions and setup, please refer to the EMC Evaluation Report for this device.
4
Ordering Information
This section contains ordering information for MCF51CN128 devices.
Table 23. Ordering Information
Memory
Freescale Part Number1
Flash
RAM
Temperature Range
(°C)
Package2
MCF51CN128CLK
128K
24K
–40 to +85
80-pin LQFP
MCF51CN128CLH
128K
24K
–40 to +85
64-pin LQFP
MCF51CN128CGT
128K
24K
–40 to +85
48-pin QFN
1
See the MCF51CN128 Reference Manual (document MCF51CN128RM), for a complete description of modules included
on each device.
2 See Table 24 for package information.
5
Package Information
Table 24. Package Descriptions
Pin Count
6
Package Type
Abbreviation
Designator
Case No.
Document No.
80
Low Quad Flat Package
LQFP
LK
917A
98ASS23237W
64
Low Quad Flat Package
LQFP
LH
840F
98ASS23234W
48
Quad Flat No-Leads
QFN
GT
1314
98ARH99048A
Mechanical Outline Drawings
The following pages are mechanical drawings for the packages described in Table 24. For the latest available drawings, visit
freescale web site (http://www.freescale.com) and enter the package’s document number into the keyword search box.
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
36
Freescale Semiconductor
Mechanical Outline Drawings
6.1
80-pin LQFP
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
37
Mechanical Outline Drawings
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
38
Freescale Semiconductor
Mechanical Outline Drawings
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
39
Mechanical Outline Drawings
6.2
64-pin LQFP
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
40
Freescale Semiconductor
Mechanical Outline Drawings
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
41
Mechanical Outline Drawings
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
42
Freescale Semiconductor
Mechanical Outline Drawings
6.3
48-pin QFN
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
43
Mechanical Outline Drawings
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
44
Freescale Semiconductor
Mechanical Outline Drawings
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
45
Mechanical Outline Drawings
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
46
Freescale Semiconductor
Revision History
7
Revision History
This section lists the changes between versions of MCF51CN128 Data Sheet document.
Table 25. Revision History
Revision Number
Date
Description of Changes
1
August 2008
Alpha Customer Release.
2
January 2009
Pre-Launch Release.
3
January 2009
Launch Release.
4
May 2009
• Changed LVDH trip and recovery values in Table 8.
• Fixed Mini-FlexBus maximum frequency to 25.1666 MHz in
Section 3.10, “Mini-FlexBus Timing Specifications.”
• Updated FEC feature list to describe ethernet operation
between 3.0 V to 3.6 V.
• In Table 8, added a footnote to the operating voltage. It
describes an exception to the Fast Ethernet Controller (FEC),
because it is only operational above the operating voltage of
3 V.
• Corrected Freescale part numbers in Table 23.
• In Table 21, changed IDDAD classification to T.
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
47
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Document Number: MCF51CN128
Rev. 4
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