Freescale Semiconductor, Inc.
Data Sheet: Technical Data
K22P121M120SF5
Rev 4, 11/2014
Kinetis K22F Sub-Family Data
Sheet
MK22FX512VMC12
MK22FN1M0VMC12
120 MHz ARM® Cortex®-M4-based Microcontroller with FPU
The K22 product family members are optimized for cost-sensitive
applications requiring low-power, USB connectivity, processing
efficiency with floating point unit. It shares the comprehensive
enablement and scalability of the Kinetis family. This product
offers:
• Up to 1 MB of flash memory with up to 128 KB of SRAM
• Small package with high memory density
• Run power consumption down to 279 μA/MHz. Static
power consumption down to 5.1 μA with full state retention
and 5 μs wakeup. Lowest Static mode down to 268 nA
• USB LS/FS OTG 2.0 with embedded 3.3 V, 120 mA LDO
voltage regulator
Performance
• Up to 120 MHz ARM Cortex-M4-based core with DSP
instructions delivering 1.25 Dhrystone MIPS per MHz
Memories and memory interfaces
• Up to 1 MB program flash memory and 128 KB RAM
• Up to 128 KB FlexNVM and 4 KB FlexRAM on
FlexMemory devices
• FlexBus external bus interface
System peripherals
• Multiple low-power modes; low leakage wakeup unit
• Memory protection unit with multi-master protection
• 16-channel DMA controller
• External watchdog monitor and software watchdog
Security and integrity modules
• Hardware CRC module
• 128-bit unique identification (ID) number per chip
Analog modules
• Two 16-bit SAR ADCs
• Two 12-bit DACs
• Three analog comparators (CMP)
• Voltage reference
121 MAPBGA
8 x 8 x 1.4 mm Pitch 0.65 mm
Communication interfaces
• USB full-/low-speed On-the-Go controller
• USB Device Charger detect
• Controller Area Network (CAN) module
• Three SPI modules
• Three I2C modules
• Six UART modules
• Secure Digital host controller (SDHC)
• I2S module
Timers
• Two 8-channel Flex-Timers (PWM/Motor Control)
• Two 2-channel Flex-Timers (PWM/Quad Decoder)
• Periodic interrupt timers and 16-bit low-power timer
• Carrier modulator transmitter
• Real-time clock
• Programmable delay block
Clocks
• 3 to 32 MHz and 32 kHz crystal oscillator
• PLL, FLL, and multiple internal oscillators
Operating Characteristics
• Voltage range: 1.71 to 3.6 V
• Flash write voltage range: 1.71 to 3.6 V
• Temperature range (ambient): –40 to 105°C
Freescale reserves the right to change the detail specifications as may be required to
permit improvements in the design of its products. © 2013–2015 Freescale
Semiconductor, Inc. All rights reserved.
Ordering Information 1
Part Number
Memory
Maximum number of I\O's
Flash (KB)
SRAM (KB)
MK22FX512VMC12
512 KB
128
86
MK22FN1M0VMC12
1 MB
128
86
1. To confirm current availability of ordererable part numbers, go to http://www.freescale.com and perform a part number
search.
Related Resources
Type
Description
Resource
Selector
Guide
The Freescale Solution Advisor is a web-based tool that features
interactive application wizards and a dynamic product selector.
Solution Advisor
Product Brief
The Product Brief contains concise overview/summary information to
enable quick evaluation of a device for design suitability.
K20PB1
Reference
Manual
The Reference Manual contains a comprehensive description of the
structure and function (operation) of a device.
K22P121M50SF5RM1
Data Sheet
The Data Sheet includes electrical characteristics and signal
connections.
K22P121M50SF51
Package
drawing
Package dimensions are provided in package drawings.
• MAPBGA 121-pin:
98ASA00344D1
1. To find the associated resource, go to http://www.freescale.com and perform a search using this term.
2
Freescale Semiconductor, Inc.
Kinetis K22F Sub-Family Data Sheet, Rev4, 11/2014.
Kinetis K21D Family
ARM ® Cortex™-M4
Core
System
Memories and Memory Interfaces
Internal
and external
watchdogs
Program
flash
RAM
Clocks
Phaselocked loop
Debug
interfaces
DSP
DMA
FlexMemory
Frequencylocked loop
Interrupt
controller
Floating
point
Low-leakage
wakeup
Serial
programming
interface
Low/high
frequency
oscillators
Internal
reference
clocks
Security
and Integrity
CRC
Analog
16-bit ADC
Timers
Communication Interfaces
2
2
FlexTimers
I C
I S
Carrier
modulator
transmitter
UART
USB OTG
LS/FS/HS
SPI
USB LS/FS
transceiver
Random
number
generator
Analog
comparator
Hardware
encryption
6-bit DAC
Tamper
detect
12-bit DAC
Periodic
interrupt
timers
USB charger
detect
Voltage
reference
Low power
timer
USB voltage
regulator
Programmable
delay block
Human-Machine
Interface (HMI)
GPIO
Independent
real-time
clock
Figure 1. K20 block diagram
Kinetis K22F Sub-Family Data Sheet, Rev4, 11/2014.
3
Freescale Semiconductor, Inc.
Table of Contents
1 Ratings.................................................................................... 5
1.1 Thermal handling ratings................................................. 5
1.2 Moisture handling ratings................................................ 5
1.3 ESD handling ratings....................................................... 5
1.4 Voltage and current operating ratings............................. 5
2 General................................................................................... 6
2.1 AC electrical characteristics.............................................6
2.2 Nonswitching electrical specifications..............................7
2.2.1
Voltage and current operating requirements.....7
2.2.2
LVD and POR operating requirements............. 8
2.2.3
Voltage and current operating behaviors.......... 8
2.2.4
Power mode transition operating behaviors......10
2.2.5
Power consumption operating behaviors.......... 10
2.2.6
EMC radiated emissions operating behaviors...14
2.2.7
Designing with radiated emissions in mind....... 15
2.2.8
Capacitance attributes...................................... 15
2.3 Switching specifications...................................................15
2.3.1
Device clock specifications............................... 15
2.3.2
General switching specifications....................... 16
2.4 Thermal specifications..................................................... 17
2.4.1
Thermal operating requirements....................... 17
2.4.2
Thermal attributes............................................. 17
3 Peripheral operating requirements and behaviors.................. 18
3.1 Core modules.................................................................. 18
3.1.1
Debug trace timing specifications..................... 19
3.1.2
JTAG electricals................................................ 19
3.2 System modules.............................................................. 22
3.3 Clock modules................................................................. 22
3.3.1
MCG specifications........................................... 22
3.3.2
Oscillator electrical specifications..................... 25
3.3.3
32 kHz oscillator electrical characteristics.........27
3.4 Memories and memory interfaces................................... 27
4
Freescale Semiconductor, Inc.
4
5
6
7
8
3.4.1
Flash (FTFE) electrical specifications............... 27
3.4.2
EzPort switching specifications......................... 32
3.4.3
Flexbus switching specifications....................... 33
3.5 Security and integrity modules........................................ 36
3.6 Analog............................................................................. 36
3.6.1
ADC electrical specifications.............................37
3.6.2
CMP and 6-bit DAC electrical specifications.....41
3.6.3
12-bit DAC electrical characteristics................. 43
3.6.4
Voltage reference electrical specifications........ 46
3.7 Timers..............................................................................47
3.8 Communication interfaces............................................... 47
3.8.1
USB electrical specifications............................. 47
3.8.2
USB DCD electrical specifications.................... 48
3.8.3
USB VREG electrical specifications..................48
3.8.4
CAN switching specifications............................ 49
3.8.5
DSPI switching specifications (limited voltage
range)................................................................49
3.8.6
DSPI switching specifications (full voltage
range)................................................................51
3.8.7
I2C switching specifications.............................. 52
3.8.8
UART switching specifications.......................... 53
3.8.9
SDHC specifications......................................... 53
3.8.10 I2S switching specifications.............................. 54
Dimensions............................................................................. 66
4.1 Obtaining package dimensions....................................... 66
Pinout...................................................................................... 67
5.1 K22 Signal Multiplexing and Pin Assignments.................67
5.2 K22 Pinouts..................................................................... 72
Revision History...................................................................... 73
Copyright................................................................................. 0
Legal....................................................................................... 0
Kinetis K22F Sub-Family Data Sheet, Rev4, 11/2014.
Ratings
1 Ratings
1.1 Thermal handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
TSTG
Storage temperature
–55
150
°C
1
TSDR
Solder temperature, lead-free
—
260
°C
2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Symbol
MSL
Description
Moisture sensitivity level
Min.
Max.
Unit
Notes
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
VHBM
Electrostatic discharge voltage, human body model
-2000
+2000
V
1
VCDM
Electrostatic discharge voltage, charged-device
model
-500
+500
V
2
Latch-up current at ambient temperature of 105°C
-100
+100
mA
3
ILAT
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
1.4 Voltage and current operating ratings
Kinetis K22F Sub-Family Data Sheet, Rev4, 11/2014.
5
Freescale Semiconductor, Inc.
General
Symbol
Description
Min.
Max.
Unit
VDD
Digital supply voltage
–0.3
3.8
V
IDD
Digital supply current
—
185
mA
VDIO
Digital input voltage (except RESET, EXTAL, and XTAL)
–0.3
5.5
V
VAIO
Analog1,
–0.3
VDD + 0.3
V
ID
VDDA
RESET, EXTAL, and XTAL input voltage
Maximum current single pin limit (applies to all digital pins)
Analog supply voltage
–25
25
mA
VDD – 0.3
VDD + 0.3
V
VUSB0_DP
USB0_DP input voltage
–0.3
3.63
V
VUSB0_DM
USB0_DM input voltage
–0.3
3.63
V
RTC battery supply voltage
–0.3
3.8
V
VBAT
1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
2 General
2.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
VIH
Input Signal
High
Low
80%
50%
20%
Midpoint1
Fall Time
VIL
Rise Time
The midpoint is VIL + (VIH - VIL) / 2
Figure 2. Input signal measurement reference
All digital I/O switching characteristics assume:
1. output pins
• have CL=30pF loads,
• are configured for fast slew rate (PORTx_PCRn[SRE]=0), and
• are configured for high drive strength (PORTx_PCRn[DSE]=1)
2. input pins
• have their passive filter disabled (PORTx_PCRn[PFE]=0)
6
Freescale Semiconductor, Inc.
Kinetis K22F Sub-Family Data Sheet, Rev4, 11/2014.
General
2.2 Nonswitching electrical specifications
2.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol
Description
Min.
Max.
Unit
VDD
Supply voltage
1.71
3.6
V
VDDA
Analog supply voltage
1.71
3.6
V
VDD – VDDA VDD-to-VDDA differential voltage
–0.1
0.1
V
VSS – VSSA VSS-to-VSSA differential voltage
–0.1
0.1
V
1.71
3.6
V
• 2.7 V ≤ VDD ≤ 3.6 V
0.7 × VDD
—
V
• 1.71 V ≤ VDD ≤ 2.7 V
0.75 × VDD
—
V
• 2.7 V ≤ VDD ≤ 3.6 V
—
0.35 × VDD
V
• 1.71 V ≤ VDD ≤ 2.7 V
—
0.3 × VDD
V
0.06 × VDD
—
V
-5
—
mA
VBAT
VIH
VIL
RTC battery supply voltage
Input high voltage
Input low voltage
VHYS
Input hysteresis
IICDIO
Digital pin negative DC injection current — single pin
• VIN < VSS-0.3V
IICAIO
IICcont
1
Analog2, EXTAL, and XTAL pin DC injection current
— single pin
3
mA
• VIN < VSS-0.3V (Negative current injection)
-5
—
• VIN > VDD+0.3V (Positive current injection)
—
+5
-25
—
—
+25
Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents or sum of
positive injection currents of 16 contiguous pins
• Negative current injection
• Positive current injection
mA
VODPU
Open drain pullup voltage level
VDD
VDD
V
VRAM
VDD voltage required to retain RAM
1.2
—
V
VPOR_VBAT
—
V
VRFVBAT
Notes
VBAT voltage required to retain the VBAT register file
4
1. All 5 V tolerant digital I/O pins are internally clamped to VSS through an ESD protection diode. There is no diode
connection to VDD. If VIN is less than VDIO_MIN, a current limiting resistor is required. If VIN greater than VDIO_MIN
(=VSS-0.3V) is observed, then there is no need to provide current limiting resistors at the pads. The negative DC
injection current limiting resistor is calculated as R=(VDIO_MIN-VIN)/|IICDIO|.
2. Analog pins are defined as pins that do not have an associated general purpose I/O port function. Additionally, EXTAL
and XTAL are analog pins.
Kinetis K22F Sub-Family Data Sheet, Rev4, 11/2014.
7
Freescale Semiconductor, Inc.
General
3. All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is less than VAIO_MIN or
greater than VAIO_MAX, a current limiting resistor is required. The negative DC injection current limiting resistor is
calculated as R=(VAIO_MIN-VIN)/|IICAIO|. The positive injection current limiting resistor is calculated as R=(VIN-VAIO_MAX)/|
IICAIO|. Select the larger of these two calculated resistances if the pin is exposed to positive and negative injection
currents.
4. Open drain outputs must be pulled to VDD.
2.2.2 LVD and POR operating requirements
Table 2. VDD supply LVD and POR operating requirements
Symbol
Description
Min.
Typ.
Max.
Unit
VPOR
Falling VDD POR detect voltage
0.8
1.1
1.5
V
VLVDH
Falling low-voltage detect threshold — high
range (LVDV=01)
2.48
2.56
2.64
V
Low-voltage warning thresholds — high range
1
VLVW1H
• Level 1 falling (LVWV=00)
2.62
2.70
2.78
V
VLVW2H
• Level 2 falling (LVWV=01)
2.72
2.80
2.88
V
VLVW3H
• Level 3 falling (LVWV=10)
2.82
2.90
2.98
V
VLVW4H
• Level 4 falling (LVWV=11)
2.92
3.00
3.08
V
—
80
—
mV
1.54
1.60
1.66
V
VHYSH
Low-voltage inhibit reset/recover hysteresis —
high range
VLVDL
Falling low-voltage detect threshold — low
range (LVDV=00)
Low-voltage warning thresholds — low range
1
VLVW1L
• Level 1 falling (LVWV=00)
1.74
1.80
1.86
V
VLVW2L
• Level 2 falling (LVWV=01)
1.84
1.90
1.96
V
VLVW3L
• Level 3 falling (LVWV=10)
1.94
2.00
2.06
V
VLVW4L
• Level 4 falling (LVWV=11)
2.04
2.10
2.16
V
—
60
—
mV
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
Notes
VBG
Bandgap voltage reference
0.97
1.00
1.03
V
tLPO
Internal low power oscillator period — factory
trimmed
900
1000
1100
μs
1. Rising threshold is the sum of falling threshold and hysteresis voltage
Table 3. VBAT power operating requirements
Symbol
Description
VPOR_VBAT Falling VBAT supply POR detect voltage
8
Freescale Semiconductor, Inc.
Min.
Typ.
Max.
Unit
0.8
1.1
1.5
V
Notes
Kinetis K22F Sub-Family Data Sheet, Rev4, 11/2014.
General
2.2.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
Symbol
VOH
Description
Min.
Typ
Max.
Unit
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -8mA
VDD – 0.5
—
—
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -3mA
VDD – 0.5
—
—
V
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -2mA
VDD – 0.5
—
—
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -0.6mA
VDD – 0.5
—
—
V
—
—
100
mA
Notes
Output high voltage — high drive strength
Output high voltage — low drive strength
IOHT
Output high current total for all ports
VOL
Output low voltage — high drive strength
1
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 9mA
—
—
0.5
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 3mA
—
—
0.5
V
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 2mA
—
—
0.5
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 0.6mA
—
—
0.5
V
—
—
100
mA
Output low voltage — low drive strength
IOLT
Output low current total for all ports
IIND
Input leakage current, digital pins
• VSS ≤ VIN ≤ VIL
• All digital pins
2,
—
0.002
0.5
μA
• All digital pins except PTD7
—
0.002
0.5
μA
• PTD7
—
0.004
1
μA
3
• VIN = VDD
IIND
2
• VDD = 3.6 V
—
18
26
μA
• VDD = 3.0 V
—
12
19
μA
• VDD = 2.5 V
—
8
13
μA
• VDD = 1.7 V
—
3
6
μA
Input leakage current, digital pins
• VDD < VIN < 5.5 V
—
1
50
μA
IOZ
Hi-Z (off-state) leakage current (per pin)
—
—
0.25
μA
RPU
Internal pullup resistors
20
35
50
kΩ
4
RPD
Internal pulldown resistors
20
35
50
kΩ
5
IIND
1.
2.
3.
4.
Input leakage current, digital pins
• VIL < VIN < VDD
Open drain outputs must be pulled to VDD.
Measured at VDD=3.6V
Internal pull-up/pull-down resistors disabled.
Measured at VDD supply voltage = VDD min and Vinput = VSS
Kinetis K22F Sub-Family Data Sheet, Rev4, 11/2014.
9
Freescale Semiconductor, Inc.
General
5. Measured at VDD supply voltage = VDD min and Vinput = VDD
2.2.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSx→RUN recovery times in the following table
assume this clock configuration:
•
•
•
•
CPU and system clocks = 100 MHz
Bus clock = 50 MHz
FlexBus clock = 50 MHz
Flash clock = 25 MHz
Table 5. Power mode transition operating behaviors
Symbol
tPOR
Description
After a POR event, amount of time from the point VDD
reaches 1.71 V to execution of the first instruction
across the operating temperature range of the chip.
• VLLS0 → RUN
• VLLS1 → RUN
• VLLS2 → RUN
• VLLS3 → RUN
• LLS → RUN
• VLPS → RUN
• STOP → RUN
Min.
Max.
Unit
—
300
μs
—
183
μs
—
183
μs
—
105
μs
—
105
μs
—
5.0
μs
—
4.4
μs
—
4.4
μs
Notes
2.2.5 Power consumption operating behaviors
Table 6. Power consumption operating behaviors
Symbol
IDDA
IDD_RUN
Description
Analog supply current
Min.
Typ.
Max.
Unit
Notes
—
—
See note
mA
1
Run mode current — all peripheral clocks
disabled, code executing from flash
2
—
33.57
36.2
mA
—
33.51
36.1
mA
Table continues on the next page...
10
Freescale Semiconductor, Inc.
Kinetis K22F Sub-Family Data Sheet, Rev4, 11/2014.
General
Table 6. Power consumption operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
• @ 1.8V
• @ 3.0V
IDD_RUN
Run mode current — all peripheral clocks
enabled, code executing from flash
• @ 1.8V
• @ 3.0V
• @ 25°C
3, 4
—
46.36
50.1
mA
—
46.31
49.9
mA
—
57.4
—
mA
• @ 125°C
IDD_WAIT
Wait mode high frequency current at 3.0 V — all
peripheral clocks disabled
—
18.2
—
mA
2
IDD_WAIT
Wait mode reduced frequency current at 3.0 V
— all peripheral clocks disabled
—
7.2
—
mA
5
IDD_VLPR
Very-low-power run mode current at 3.0 V — all
peripheral clocks disabled
—
1.21
—
mA
6
IDD_VLPR
Very-low-power run mode current at 3.0 V — all
peripheral clocks enabled
—
1.88
—
mA
7
IDD_VLPW
Very-low-power wait mode current at 3.0 V — all
peripheral clocks disabled
—
0.80
—
mA
8
IDD_STOP
Stop mode current at 3.0 V
• @ –40 to 25°C
—
0.528
2.25
mA
• @ 70°C
—
1.6
8
mA
• @ 105°C
—
5.2
20
mA
• @ –40 to 25°C
—
78
700
μA
• @ 70°C
—
498
2400
μA
• @ 105°C
—
1300
3600
μA
• @ –40 to 25°C
—
5.1
15
μA
• @ 70°C
—
28
80
μA
• @ 105°C
—
124
300
μA
• @ –40 to 25°C
—
3.1
7.5
μA
• @ 70°C
—
14.5
45
μA
• @ 105°C
—
63.5
195
μA
—
2.0
5
μA
—
6.9
32
μA
IDD_VLPS
IDD_LLS
Very-low-power stop mode current at 3.0 V
Low leakage stop mode current at 3.0 V
IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
• @ –40 to 25°C
Table continues on the next page...
Kinetis K22F Sub-Family Data Sheet, Rev4, 11/2014.
11
Freescale Semiconductor, Inc.
General
Table 6. Power consumption operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
—
30
112
μA
• @ –40 to 25°C
—
1.25
2.1
μA
• @ 70°C
—
6.5
18.5
μA
• @ 105°C
—
37
108
μA
—
0.745
1.65
μA
—
6.03
18
μA
—
37
108
μA
—
0.268
1.25
μA
—
3.7
15
μA
—
22.9
95
μA
—
0.19
0.22
μA
—
0.49
0.64
μA
—
2.2
3.2
μA
• @ 70°C
Notes
• @ 105°C
IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit enabled
• @ –40 to 25°C
• @ 70°C
• @ 105°C
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit disabled
• @ –40 to 25°C
• @ 70°C
• @ 105°C
IDD_VBAT
Average current with RTC and 32kHz disabled
at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
IDD_VBAT
Average current when CPU is not accessing
RTC registers
9
• @ 1.8V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
—
0.68
0.8
μA
—
1.2
1.56
μA
—
3.6
5.3
μA
—
0.81
0.96
μA
—
1.45
1.89
μA
—
4.3
6.33
μA
• @ 3.0V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. 120 MHz core and system clock, 60 MHz bus 40 Mhz and FlexBus clock, and 24 MHz flash clock. MCG configured for
PEE mode. All peripheral clocks disabled.
3. 120 MHz core and system clock, 60 MHz bus and FlexBus clock, and 24 MHz flash clock. MCG configured for PEE
mode. All peripheral clocks enabled.
4. Max values are measured with CPU executing DSP instructions.
12
Freescale Semiconductor, Inc.
Kinetis K22F Sub-Family Data Sheet, Rev4, 11/2014.
General
5. 25 MHz core and system clock, 25 MHz bus clock, and 12.5 MHz FlexBus and flash clock. MCG configured for FEI
mode.
6. 4 MHz core, system, FlexBus, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral
clocks disabled. Code executing from flash.
7. 4 MHz core, system, FlexBus, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral
clocks enabled but peripherals are not in active operation. Code executing from flash.
8. 4 MHz core, system, FlexBus, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral
clocks disabled.
9. Includes 32kHz oscillator current and RTC operation.
2.2.5.1
Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
•
•
•
•
MCG in PEE mode at greater than 100 MHz frequencies
No GPIOs toggled
Code execution from flash with cache enabled
For the ALLOFF curve, all peripheral clocks are disabled except FTFE
Figure 3. Run mode supply current vs. core frequency
Kinetis K22F Sub-Family Data Sheet, Rev4, 11/2014.
13
Freescale Semiconductor, Inc.
General
Figure 4. VLPR mode supply current vs. core frequency
2.2.6 EMC radiated emissions operating behaviors
Table 7. EMC radiated emissions operating behaviors
Symbol
Description
Frequency
band
(MHz)
Typ.
Unit
Notes
1, 2
VRE1
Radiated emissions voltage, band 1
0.15–50
23
dBμV
VRE2
Radiated emissions voltage, band 2
50–150
27
dBμV
VRE3
Radiated emissions voltage, band 3
150–500
28
dBμV
VRE4
Radiated emissions voltage, band 4
500–1000
14
dBμV
IEC level
0.15–1000
K
—
VRE_IEC
2, 3
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement
of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and
Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic application code.
14
Freescale Semiconductor, Inc.
Kinetis K22F Sub-Family Data Sheet, Rev4, 11/2014.
General
The reported emission level is the value of the maximum measured emission, rounded up to the next whole number,
from among the measured orientations in each frequency range.
2. VDD = 3.3 V, TA = 25 °C, fOSC = 12 MHz (crystal), fSYS = 96 MHz, fBUS = 48MHz
3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and
Wideband TEM Cell Method
2.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.freescale.com.
2. Perform a keyword search for “EMC design.”
2.2.8 Capacitance attributes
Table 8. Capacitance attributes
Symbol
Description
Min.
Max.
Unit
CIN_A
Input capacitance: analog pins
—
7
pF
CIN_D
Input capacitance: digital pins
—
7
pF
2.3 Switching specifications
2.3.1 Device clock specifications
Table 9. Device clock specifications
Symbol
Description
Min.
Max.
Unit
System and core clock
—
120
MHz
System and core clock when Full Speed USB in
operation
20
—
MHz
Bus clock
—
60
MHz
FlexBus clock
—
50
MHz
fFLASH
Flash clock
—
25
MHz
fLPTMR
LPTMR clock
—
25
MHz
Notes
Normal run mode
fSYS
fSYS_USB
fBUS
FB_CLK
VLPR
mode1
fSYS
System and core clock
—
4
MHz
fBUS
Bus clock
—
4
MHz
Table continues on the next page...
Kinetis K22F Sub-Family Data Sheet, Rev4, 11/2014.
15
Freescale Semiconductor, Inc.
General
Table 9. Device clock specifications (continued)
Symbol
Description
Min.
Max.
Unit
FB_CLK
FlexBus clock
—
4
MHz
fFLASH
Flash clock
—
0.8
MHz
fERCLK
External reference clock
—
16
MHz
LPTMR clock
—
25
MHz
fLPTMR_ERCLK LPTMR external reference clock
fLPTMR_pin
—
16
MHz
fFlexCAN_ERCLK FlexCAN external reference clock
—
8
MHz
fI2S_MCLK
I2S master clock
—
12.5
MHz
fI2S_BCLK
I2S bit clock
—
4
MHz
Notes
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for
any other module.
2.3.2 General switching specifications
These general purpose specifications apply to all pins configured for:
• GPIO signaling
• Other peripheral module signaling not explicitly stated elsewhere
Table 10. General switching specifications
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock
cycles
1, 2
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous path
100
—
ns
3
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
16
—
ns
3
External reset pulse width (digital glitch filter disabled)
100
—
ns
3
2
—
Bus clock
cycles
Mode select (EZP_CS) hold time after reset
deassertion
Port rise and fall time (high drive strength)
4
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
—
12
ns
• 2.7 ≤ VDD ≤ 3.6V
—
6
ns
• 1.71 ≤ VDD ≤ 2.7V
—
36
ns
• 2.7 ≤ VDD ≤ 3.6V
—
24
ns
• Slew enabled
Port rise and fall time (low drive strength)
5
• Slew disabled
16
Freescale Semiconductor, Inc.
Kinetis K22F Sub-Family Data Sheet, Rev4, 11/2014.
General
Table 10. General switching specifications
Symbol
Description
Min.
Max.
Unit
• 1.71 ≤ VDD ≤ 2.7V
—
12
ns
• 2.7 ≤ VDD ≤ 3.6V
—
6
ns
• 1.71 ≤ VDD ≤ 2.7V
—
36
ns
• 2.7 ≤ VDD ≤ 3.6V
—
24
ns
Notes
• Slew enabled
1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses
may or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter
pulses can be recognized in that case.
2. The greater synchronous and asynchronous timing must be met.
3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS,
and VLLSx modes.
4. 75 pF load
5. 15 pF load
2.4 Thermal specifications
2.4.1 Thermal operating requirements
Table 11. Thermal operating requirements
Symbol
Description
Min.
Max.
Unit
TJ
Die junction temperature
–40
125
°C
TA
Ambient temperature
–40
105
°C
2.4.2 Thermal attributes
Board type
Symbol
Description
121 MAPBGA
Unit
Notes
Single-layer (1s)
RθJA
Thermal
resistance,
junction to
ambient (natural
convection)
65
°C/W
1
Four-layer (2s2p)
RθJA
Thermal
resistance,
junction to
ambient (natural
convection)
36
°C/W
1
Table continues on the next page...
Kinetis K22F Sub-Family Data Sheet, Rev4, 11/2014.
17
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Board type
Symbol
Description
121 MAPBGA
Unit
Notes
Single-layer (1s)
RθJMA
Thermal
resistance,
junction to
ambient (200 ft./
min. air speed)
52
°C/W
1
Four-layer (2s2p)
RθJMA
Thermal
resistance,
junction to
ambient (200 ft./
min. air speed)
31
°C/W
1
—
RθJB
Thermal
resistance,
junction to board
17
°C/W
2
—
RθJC
Thermal
resistance,
junction to case
13
°C/W
3
—
ΨJT
Thermal
characterization
parameter,
junction to
package top
outside center
(natural
convection)
3
°C/W
4
Notes
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal
Test Method Environmental Conditions—Natural Convection (Still Air), or EIA/
JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method
Environmental Conditions—Forced Convection (Moving Air).
2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal
Test Method Environmental Conditions—Junction-to-Board.
3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard,
Microcircuits, with the cold plate temperature used for the case temperature. The
value includes the thermal resistance of the interface material between the top of
the package and the cold plate.
4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal
Test Method Environmental Conditions—Natural Convection (Still Air).
3 Peripheral operating requirements and behaviors
18
Freescale Semiconductor, Inc.
Kinetis K22F Sub-Family Data Sheet, Rev4, 11/2014.
Peripheral operating requirements and behaviors
3.1 Core modules
3.1.1 Debug trace timing specifications
Table 12. Debug trace operating behaviors
Symbol
Description
Min.
Max.
Unit
Tcyc
Clock period
Frequency dependent
(limited to 50 MHz)
MHz
Twl
Low pulse width
2
—
ns
Twh
High pulse width
2
—
ns
Tr
Clock and data rise time
—
3
ns
Tf
Clock and data fall time
—
3
ns
Ts
Data setup
3
—
ns
Th
Data hold
2
—
ns
TRACECLK
Tr
Tf
Twh
Twl
Tcyc
Figure 5. TRACE_CLKOUT specifications
TRACE_CLKOUT
Ts
Th
Ts
Th
TRACE_D[3:0]
Figure 6. Trace data specifications
3.1.2 JTAG electricals
Table 13. JTAG limited voltage range electricals
Symbol
J1
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
TCLK frequency of operation
MHz
Table continues on the next page...
Kinetis K22F Sub-Family Data Sheet, Rev4, 11/2014.
19
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 13. JTAG limited voltage range electricals (continued)
Symbol
Description
Min.
Max.
• Boundary Scan
0
10
• JTAG and CJTAG
0
25
• Serial Wire Debug
0
50
1/J1
—
ns
• Boundary Scan
50
—
ns
• JTAG and CJTAG
20
—
ns
• Serial Wire Debug
10
—
ns
J4
TCLK rise and fall times
—
3
ns
J5
Boundary scan input data setup time to TCLK rise
20
—
ns
J6
Boundary scan input data hold time after TCLK rise
2.6
—
ns
J7
TCLK low to boundary scan output data valid
—
25
ns
J8
TCLK low to boundary scan output high-Z
—
25
ns
J9
TMS, TDI input data setup time to TCLK rise
8
—
ns
J10
TMS, TDI input data hold time after TCLK rise
1
—
ns
J11
TCLK low to TDO data valid
—
17
ns
J12
TCLK low to TDO high-Z
—
17
ns
J13
TRST assert time
100
—
ns
J14
TRST setup time (negation) to TCLK high
8
—
ns
J2
TCLK cycle period
J3
TCLK clock pulse width
Unit
Table 14. JTAG full voltage range electricals
Symbol
J1
Description
Min.
Max.
Operating voltage
1.71
3.6
TCLK frequency of operation
Unit
V
MHz
• Boundary Scan
0
10
• JTAG and CJTAG
0
20
• Serial Wire Debug
0
40
1/J1
—
ns
• Boundary Scan
50
—
ns
• JTAG and CJTAG
25
—
ns
• Serial Wire Debug
12.5
—
ns
J2
TCLK cycle period
J3
TCLK clock pulse width
J4
TCLK rise and fall times
—
3
ns
J5
Boundary scan input data setup time to TCLK rise
20
—
ns
J6
Boundary scan input data hold time after TCLK rise
0
—
ns
Table continues on the next page...
20
Freescale Semiconductor, Inc.
Kinetis K22F Sub-Family Data Sheet, Rev4, 11/2014.
Peripheral operating requirements and behaviors
Table 14. JTAG full voltage range electricals (continued)
Symbol
Description
Min.
Max.
Unit
J7
TCLK low to boundary scan output data valid
—
25
ns
J8
TCLK low to boundary scan output high-Z
—
25
ns
J9
TMS, TDI input data setup time to TCLK rise
8
—
ns
J10
TMS, TDI input data hold time after TCLK rise
1.4
—
ns
J11
TCLK low to TDO data valid
—
22.1
ns
J12
TCLK low to TDO high-Z
—
22.1
ns
J13
TRST assert time
100
—
ns
J14
TRST setup time (negation) to TCLK high
8
—
ns
J2
J3
J3
TCLK (input)
J4
J4
Figure 7. Test clock input timing
TCLK
J5
Data inputs
J6
Input data valid
J7
Data outputs
Output data valid
J8
Data outputs
J7
Data outputs
Output data valid
Figure 8. Boundary scan (JTAG) timing
Kinetis K22F Sub-Family Data Sheet, Rev4, 11/2014.
21
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
TCLK
J9
TDI/TMS
J10
Input data valid
J11
TDO
Output data valid
J12
TDO
J11
TDO
Output data valid
Figure 9. Test Access Port timing
TCLK
J14
J13
TRST
Figure 10. TRST timing
3.2 System modules
There are no specifications necessary for the device's system modules.
3.3 Clock modules
22
Freescale Semiconductor, Inc.
Kinetis K22F Sub-Family Data Sheet, Rev4, 11/2014.
Peripheral operating requirements and behaviors
3.3.1 MCG specifications
Table 15. MCG specifications
Symbol
Description
Min.
Typ.
Max.
Unit
fints_ft
Internal reference frequency (slow clock) —
factory trimmed at nominal VDD and 25 °C
—
32.768
—
kHz
fints_t
Internal reference frequency (slow clock) —
user trimmed
31.25
—
39.0625
kHz
Iints
Internal reference (slow clock) current
Notes
—
20
—
µA
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
—
± 0.3
± 0.6
%fdco
1
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM only
—
± 0.2
± 0.5
%fdco
1
Δfdco_t
Total deviation of trimmed average DCO output
frequency over voltage and temperature
—
± 0.5
±2
%fdco
Δfdco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
—
± 0.3
±1
%fdco
fintf_ft
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
—
4
—
MHz
fintf_t
Internal reference frequency (fast clock) —
user trimmed at nominal VDD and 25 °C
3
—
5
MHz
Internal reference (fast clock) current
—
25
—
µA
Iintf
floc_low
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
—
—
kHz
floc_high
Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
—
—
kHz
31.25
—
39.0625
kHz
20
20.97
25
MHz
40
41.94
50
MHz
60
62.91
75
MHz
80
83.89
100
MHz
—
23.99
—
MHz
—
47.97
—
MHz
—
71.99
—
MHz
1
,2
1
FLL
ffll_ref
fdco
FLL reference frequency range
DCO output
frequency range
Low range (DRS=00)
3, 4
640 × ffll_ref
Mid range (DRS=01)
1280 × ffll_ref
Mid-high range (DRS=10)
1920 × ffll_ref
High range (DRS=11)
2560 × ffll_ref
fdco_t_DMX3 DCO output
frequency
2
Low range (DRS=00)
5, 6
732 × ffll_ref
Mid range (DRS=01)
1464 × ffll_ref
Mid-high range (DRS=10)
Table continues on the next page...
Kinetis K22F Sub-Family Data Sheet, Rev4, 11/2014.
23
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 15. MCG specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
—
95.98
—
MHz
—
180
—
—
150
—
—
—
1
ms
48.0
—
120
MHz
—
1060
—
µA
—
600
—
µA
2.0
—
4.0
MHz
Notes
2197 × ffll_ref
High range (DRS=11)
2929 × ffll_ref
Jcyc_fll
FLL period jitter
• fDCO = 48 MHz
• fDCO = 98 MHz
tfll_acquire
FLL target frequency acquisition time
ps
7
PLL
fvco
VCO operating frequency
Ipll
PLL operating current
• PLL @ 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref
= 2 MHz, VDIV multiplier = 48)
Ipll
PLL operating current
• PLL @ 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref
= 2 MHz, VDIV multiplier = 24)
fpll_ref
PLL reference frequency range
Jcyc_pll
PLL period jitter (RMS)
Jacc_pll
• fvco = 48 MHz
—
120
—
ps
• fvco = 120 MHz
—
75
—
ps
PLL accumulated jitter over 1µs (RMS)
9
• fvco = 48 MHz
—
1350
—
ps
• fvco = 120 MHz
—
600
—
ps
Lock entry frequency tolerance
± 1.49
—
± 2.98
%
Dunl
Lock exit frequency tolerance
± 4.47
—
± 5.97
%
Lock detector detection time
8
9
Dlock
tpll_lock
8
—
—
10-6
150 ×
+ 1075(1/
fpll_ref)
s
10
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. 2 V
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