MMPF0200F0AEP

NXP Semiconductors Data Sheet: Technical Data Document Number: MMPF0200 Rev. 7, 7/2019 12 channel configurable power management integrated circuit PF0200 The PF0200 Power Management Integrated Circuit (PMIC) provides a highly programmable/ configurable architecture, with fully integrated power devices and minimal external components. With up to four buck converters, one boost regulator, six linear regulators, RTC supply, and coin-cell charger, the PF0200 can provide power for a complete system, including applications processors, memory, and system peripherals, in a wide range of applications. With on-chip One Time Programmable (OTP) memory, the PF0200 is available in preprogrammed standard versions, or non-programmed to support custom programming. The PF0200 is especially suited to the i.MX 6SoloLite, i.MX 6Solo and i.MX 6DualLite versions of the i.MX 6 family of devices and is supported by full system level reference designs, and pre-programmed versions of the device. This device is powered by SMARTMOS technology. Features: • Three to four buck converters, depending on configuration • Boost regulator to 5.0 V output • Six general purpose linear regulators • Programmable output voltage, sequence, and timing • OTP (One Time Programmable) memory for device configuration • Coin cell charger and RTC supply • DDR termination reference voltage • Power control logic with processor interface and event detection • I2C control • Individually programmable ON, OFF, and Standby modes PF0200 POWER MANAGEMENT EP SUFFIX (E-TYPE) 56 QFN 8X8 98ASA00405D Applications • Tablets • IPTV • Industrial Control • Medical monitoring • Home automation/ alarm/ energy management i.MX6X VREFDDR DDR MEMORY INTERFACE DDR Memory SW3A/B Processor Core Voltages SW1A/B SW2 SWBST SD-MMC/ NAND Mem. SATA HDD SATA - FLASH NAND - NOR Interfaces Control Signals Parallel control/GPIOS I2C Communication I2C Communication VGEN1 VGEN2 VGEN3 VGEN4 Camera External AMP Microphones Speakers Audio Codec Sensors Camera GPS MIPI uPCIe WAM GPS MIPI HDMI LDVS Display VGEN5 LICELL Charger COINCELL USB Ethernet CAN VGEN6 Main Supply Cluster/HUD Front USB POD Rear Seat Infotaiment Figure 1. Simplified application diagram © NXP B.V. 2019. ES SUFFIX (WF-TYPE) 56 QFN 8X8 98ASA00589D Rear USB POD Table of Contents 1 Orderable parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1 Pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.2 Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 General product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.2 Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 Functional block requirements and behaviors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.1 Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.2 16 MHz and 32 kHz clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.3 Bias and references block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.4 Power generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.5 Control interface I2C block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 7 Typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 7.2 PF0200 layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 7.3 Thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 8 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 9 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 8.1 Packaging dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 PF0200 2 NXP Semiconductors ORDERABLE PARTS 1 Orderable parts The PF0200 is available with both pre-programmed and non-programmed OTP memory configurations. The non-programmed device uses “NP” as the programming code. The pre-programmed devices are identified using the program codes from Table 1, which also list the associated NXP reference designs where applicable. Details of the OTP programming for each device can be found in Table 8. Contact your NXP representative for more details. Table 1. Orderable part variations Part number Temperature (TA) Package Programming Reference designs NP N/A (2)(1) F0 N/A (2)(1) F3 N/A MMPF0200F4AEP F4 N/A (2)(1) MMPF0200F6AEP F6 i.MX6SX-SDB (2)(1) F0 N/A (2)(1) F3 N/A F4 N/A MMPF0200NPAEP MMPF0200F0AEP MMPF0200F3AEP -40 to 85 °C 56 QFN 8x8 mm - 0.5 mm pitch E-Type QFN (full lead) MMPF0200F0ANES MMPF0200F3ANES -40 to 105 °C 56 QFN 8x8 mm - 0.5 mm pitch WF-Type QFN (wettable flank) MMPF0200F4ANES Qualification tier Consumer Extended Industrial Notes (2)(1) (2)(1) (2)(1) Notes 1. For Tape and Reel add an R2 suffix to the part number. 2. For programming details see Table 8. PF0200 NXP Semiconductors 3 INTERNAL BLOCK DIAGRAM 2 Internal block diagram PF0200 VGEN1 100 mA VIN1 VGEN1 SW1FB SW1A/B Single/Dual 2500 mA Buck VGEN2 250 mA VGEN2 VIN2 VGEN3 VGEN3 100 mA VGEN4 VGEN4 350 mA SW2 1500 mA Buck VGEN5 100 mA VGEN5 O/P Drive SW1AIN SW1ALX SW1BLX SW1BIN SW1VSSSNS Core Control logic VIN3 O/P Drive O/P Drive SW2LX SW2IN SW2IN SW2FB GNDREF1 Initialization State Machine VGEN6 200 mA VGEN6 Supplies Control OTP SW3AFB VDDOTP SW3A/B Single Phase 2500 mA Buck CONTROL I2C Interface VDDIO SCL SDA O/P Drive O/P Drive DVS CONTROL I2C Register map VCOREREF VCORE SW3BIN SW3VSSSNS Trim-In-Package Reference Generation SW3BLX SW3BFB DVS Control VCOREDIG SW3AIN SW3ALX SWBST 600 mA Boost Clocks and resets O/P Drive SWBSTLX SWBSTIN SWBSTFB GNDREF VREFDDR VINREFDDR Clocks 32 kHz and 16 MHz VHALF VIN Li Cell Charger Best of Supply LICELL RSVD6 RSVD5 RSVD4 RSVD3 RSVD2 RSVD1 INTB SDWNB STANDBY RESETBMCU ICTEST PWRON VSNVS VSNVS Figure 2. PF0200 simplified internal block diagram PF0200 4 NXP Semiconductors PIN CONNECTIONS SDA VCOREREF VCOREDIG VIN VCORE GNDREF VDDOTP SWBSTLX SWBSTIN SWBSTFB VSNVS Pinout diagram SCL 3.1 VDDIO Pin connections PWRON 3 56 55 54 53 52 51 50 49 48 47 46 45 44 43 INTB 1 42 LICELL SDWNB 2 41 VGEN6 RESETBMCU 3 40 VIN3 STANDBY 4 39 VGEN5 ICTEST 5 38 SW3AFB SW1FB 6 37 SW3AIN SW1AIN 7 36 SW3ALX SW1ALX 8 35 SW3BLX SW1BLX 9 34 SW3BIN SW1BIN 10 33 SW3BFB RSVD1 11 32 SW3VSSSNS RSVD2 12 31 VREFDDR RSVD3 13 30 VINREFDDR SW1VSSSNS 14 29 VHALF 15 16 17 18 19 20 21 22 23 24 25 26 27 28 GNDREF1 VGEN1 VIN1 VGEN2 RSVD4 RSVD5 RSVD6 SW2LX SW2IN SW2IN SW2FB VGEN3 VIN2 VGEN4 EP Figure 3. Pinout diagram PF0200 NXP Semiconductors 5 PIN CONNECTIONS 3.2 Pin definitions Table 2. PF0200 pin definitions Pin number Pin name Pin function Max rating Type 1 INTB O 3.6 V Digital Open drain interrupt signal to processor 2 SDWNB O 3.6 V Digital Open drain signal to indicate an imminent system shutdown 3 RESETBMCU O 3.6 V Digital Open drain reset output to processor. Alternatively can be used as a Power Good output. 4 STANDBY I 3.6 V Digital Standby input signal from processor 5 ICTEST I 7.5 V Digital/ Analog Reserved pin. Connect to GND in application. 6 SW1FB (4) I 3.6 V Analog Output voltage feedback for SW1A/B. Route this trace separately from the highcurrent path and terminate at the output capacitance. 7 SW1AIN (4) I 4.8 V Analog Input to SW1A regulator. Bypass with at least a 4.7 μF ceramic capacitor and a 0.1 μF decoupling capacitor as close to the pin as possible. 8 SW1ALX (4) O 4.8 V Analog Regulator 1A switch node connection 9 SW1BLX (4) O 4.8 V Analog Regulator 1B switch node connection 10 SW1BIN (4) I 4.8 V Analog Input to SW1B regulator. Bypass with at least a 4.7 μF ceramic capacitor and a 0.1 μF decoupling capacitor as close to the pin as possible. 11 RSVD1 - - Reserved Reserved for pin to pin compatibility. Internally connected. Leave this pin unconnected. 12 RSVD2 - - Reserved Reserved for pin to pin compatibility. Connect this pin to VIN. 13 RSVD3 - - Reserved Reserved for pin to pin compatibility. Internally connected. Leave this pin unconnected. 14 SW1VSSSNS GND - GND Ground reference for regulator SW1AB. It is connected externally to GNDREF through a board ground plane. 15 GNDREF1 GND - GND Ground reference for regulator SW2. It is connected externally to GNDREF, via board ground plane. 16 VGEN1 O 2.5 V Analog VGEN1 regulator output, Bypass with a 2.2 μF ceramic output capacitor. 17 VIN1 I 3.6 V Analog VGEN1, 2 input supply. Bypass with a 1.0 μF decoupling capacitor as close to the pin as possible. 18 VGEN2 O 2.5 V Analog VGEN2 regulator output, Bypass with a 4.7 μF ceramic output capacitor. 19 RSVD4 - - Reserved Reserved for pin to pin compatibility. Internally connected. Leave this pin unconnected. 20 RSVD5 - - Reserved Reserved for pin to pin compatibility. Connect this pin to VIN 21 RSVD6 - - Reserved Reserved for pin to pin compatibility. Internally connected. Leave this pin unconnected. 22 SW2LX (4) O 4.8 V Analog Regulator 2 switch node connection 23 SW2IN (4) I 4.8 V Analog 24 SW2IN (4) I 4.8 V Analog Input to SW2 regulator. Connect pin 23 together with pin 24 and bypass with at least a 4.7 μF ceramic capacitor and a 0.1 μF decoupling capacitor as close to these pins as possible. 25 SW2FB (4) I 3.6 V Analog Output voltage feedback for SW2. Route this trace separately from the high-current path and terminate at the output capacitance. 26 VGEN3 O 3.6 V Analog VGEN3 regulator output. Bypass with a 2.2 μF ceramic output capacitor. 27 VIN2 I 3.6 V Analog VGEN3,4 input. Bypass with a 1.0 μF decoupling capacitor as close to the pin as possible. Definition PF0200 6 NXP Semiconductors PIN CONNECTIONS Table 2. PF0200 pin definitions (continued) Pin number Pin name Pin function Max rating Type 28 VGEN4 O 3.6 V Analog VGEN4 regulator output, Bypass with a 4.7 μF ceramic output capacitor. 29 VHALF I 3.6 V Analog Half supply reference for VREFDDR 30 VINREFDDR I 3.6 V Analog VREFDDR regulator input. Bypass with at least 1.0 μF decoupling capacitor as close to the pin as possible. 31 VREFDDR O 3.6 V Analog VREFDDR regulator output 32 SW3VSSSNS GND - GND 33 SW3BFB (4) I 3.6 V Analog Output voltage feedback for SW3B. Route this trace separately from the high-current path and terminate at the output capacitance. 34 SW3BIN (4) I 4.8 V Analog Input to SW3B regulator. Bypass with at least a 4.7 μF ceramic capacitor and a 0.1 μF decoupling capacitor as close to the pin as possible. 35 SW3BLX (4) O 4.8 V Analog Regulator 3B switch node connection 36 SW3ALX (4) O 4.8 V Analog Regulator 3A switch node connection 37 SW3AIN (4) I 4.8 V Analog Input to SW3A regulator. Bypass with at least a 4.7 μF ceramic capacitor and a 0.1 μF decoupling capacitor as close to the pin as possible. 38 SW3AFB (4) I 3.6 V Analog Output voltage feedback for SW3A. Route this trace separately from the high-current path and terminate at the output capacitance. 39 VGEN5 O 3.6 V Analog VGEN5 regulator output. Bypass with a 2.2 μF ceramic output capacitor. 40 VIN3 I 4.8 V Analog VGEN5, 6 input. Bypass with a 1.0 μF decoupling capacitor as close to the pin as possible. 41 VGEN6 O 3.6 V Analog VGEN6 regulator output. By pass with a 2.2 μF ceramic output capacitor. 42 LICELL I/O 3.6 V Analog Coin cell supply input/output 43 VSNVS O 3.6 V Analog LDO or coin cell output to processor 44 SWBSTFB (4) I 5.5 V Analog Boost regulator feedback. Connect this pin to the output rail close to the load. Keep this trace away from other noisy traces and planes. 45 SWBSTIN (4) I 4.8 V Analog Input to SWBST regulator. Bypass with at least a 2.2 μF ceramic capacitor and a 0.1 μF decoupling capacitor as close to the pin as possible. 46 SWBSTLX (4) O 7.5 V Analog SWBST switch node connection 47 VDDOTP I 10 V (3) Digital & Analog 48 GNDREF GND - GND 49 VCORE O 3.6 V Analog Analog Core supply 50 VIN I 4.8 V Analog Main chip supply 51 VCOREDIG O 1.5 V Analog Digital Core supply 52 VCOREREF O 1.5 V Analog Main band gap reference 53 SDA I/O 3.6 V Digital I2C data line (Open drain) 54 SCL I 3.6 V Digital I2C clock 55 VDDIO I 3.6 V Analog Supply for I2C bus. Bypass with 0.1 μF decoupling capacitor as close to the pin as possible. 56 PWRON I 3.6 V Digital Power On/off from processor Definition Ground reference for the SW3 regulator. Connect to GNDREF externally via the board ground plane. Supply to program OTP fuses Ground reference for the main band gap regulator. PF0200 NXP Semiconductors 7 PIN CONNECTIONS Table 2. PF0200 pin definitions (continued) Pin number Pin name Pin function Max rating Type Definition - EP GND - GND Expose pad. Functions as ground return for buck regulators. Tie this pad to the inner and external ground planes through vias to allow effective thermal dissipation. Notes 3. 10 V Maximum voltage rating during OTP fuse programming. 7.5 V Maximum DC voltage rated otherwise. 4. Unused switching regulators should be connected as follow: Pins SWxLX and SWxFB should be unconnected and Pin SWxIN should be connected to VIN with a 0.1 μF bypass capacitor. PF0200 8 NXP Semiconductors GENERAL PRODUCT CHARACTERISTICS 4 General product characteristics 4.1 Absolute maximum ratings Table 3. Absolute maximum ratings All voltages are with respect to ground, unless otherwise noted. Exceeding these ratings may cause malfunction or permanent damage to the device. The detailed maximum voltage rating per pin can be found in the pin list section. Symbol Description Value Unit Main input supply voltage -0.3 to 4.8 V VDDOTP OTP programming input supply voltage -0.3 to 10 V VLICELL Coin cell voltage -0.3 to 3.6 V ±2000 ±500 V Notes Electrical ratings VIN VESD ESD Ratings Human Body Model Charge Device Model (5) Notes 5. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω), and the Charge Device Model (CDM), Robotic (CZAP = 4.0 pF). PF0200 NXP Semiconductors 9 GENERAL PRODUCT CHARACTERISTICS 4.2 Thermal characteristics Table 4. Thermal ratings Symbol Description (rating) Min. Max. Unit Thermal ratings TA Ambient Operating Temperature Range PF0200A PF0200AN -40 -40 85 105 °C TJ Operating Junction Temperature Range -40 125 °C Storage Temperature Range -65 150 °C – Note 8 °C (7)(8) Junction to Ambient Natural Convection Four layer board (2s2p) Eight layer board (2s6p) – – 28 15 °C/W (9)(10)(11) Junction to Ambient (@200 ft/min) Four layer board (2s2p) – 22 °C/W (9)(11) Junction to Board – 10 °C/W (12) RΘJCBOTTOM Junction to Case Bottom – 1.2 °C/W (13) ΨJT Junction to Package Top Natural Convection – 2.0 °C/W (14) TST TPPRT Peak Package Reflow Temperature (6) QFN56 Thermal resistance and package dissipation ratings RθJA RθJMA RθJB Notes 6. Do not operate beyond 125 °C for extended periods of time. Operation above 150 °C may cause permanent damage to the IC. See Table 5 for thermal protection features. 7. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause a malfunction or permanent damage to the device. 8. NXP’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), go to www.nxp.com, search by part number (remove prefixes/suffixes) and enter the core ID to view all orderable parts, and review parametrics. 9. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 10. The Board uses the JEDEC specifications for thermal testing (and simulation) JESD51-7 and JESD51-5. 11. Per JEDEC JESD51-6 with the board horizontal. 12. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 13. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 14. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD512. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. 4.2.1 Power dissipation During operation, the temperature of the die should not exceed the operating junction temperature noted in Table 4. To optimize the thermal management and to avoid overheating, the PF0200 provides thermal protection. An internal comparator monitors the die temperature. Interrupts THERM110I, THERM120I, THERM125I, and THERM130I will be generated when the respective thresholds specified in Table 5 are crossed in either direction. The temperature range can be determined by reading the THERMxxxS bits in register INTSENSE0. In the event of excessive power dissipation, thermal protection circuitry will shut down the PF0200. This thermal protection will act above the thermal protection threshold listed in Table 5. To avoid any unwanted power downs resulting from internal noise, the protection is debounced for 8.0 ms. This protection should be considered as a fail-safe mechanism and therefore the system should be configured such that this protection is not tripped under normal conditions. PF0200 10 NXP Semiconductors GENERAL PRODUCT CHARACTERISTICS Table 5. Thermal protection thresholds Parameter Min. Typ. Max. Units Thermal 110 °C Threshold (THERM110) 100 110 120 °C Thermal 120 °C Threshold (THERM120) 110 120 130 °C Thermal 125 °C Threshold (THERM125) 115 125 135 °C Thermal 130 °C Threshold (THERM130) 120 130 140 °C Thermal Warning Hysteresis 2.0 – 4.0 °C Thermal Protection Threshold 130 140 150 °C 4.3 Electrical characteristics 4.3.1 General specifications Notes Table 6. General PMIC static characteristics Consumer TA = -40 to 85 °C and Extended Industrial TA = -40 to 105 °C, VIN = 2.8 to 4.5 V, VDDIO = 1.7 to 3.6 V, typical external component values and full load current range, unless otherwise noted. Pin name PWRON RESETBMCU SCL SDA INTB SDWNB STANDBY VDDOTP Parameter Load condition Min. Max. Unit VIL – 0.0 0.2 * VSNVS V VIH – 0.8 * VSNVS 3.6 V VOL -2.0 mA 0.0 0.4 V VOH Open Drain 0.7* VIN VIN V VIL – 0.0 0.2 * VDDIO V VIH – 0.8 * VDDIO 3.6 V VIL – 0.0 0.2 * VDDIO V VIH – 0.8 * VDDIO 3.6 V VOL -2.0 mA 0.0 0.4 V VOH Open Drain 0.7*VDDIO VDDIO V VOL -2.0 mA 0.0 0.4 V VOH Open Drain 0.7* VIN VIN V VOL -2.0 mA 0.0 0.4 V VOH Open Drain 0.7* VIN VIN V VIL – 0.0 0.2 * VSNVS V VIH – 0.8 * VSNVS 3.6 V VIL – 0.0 0.3 V VIH – 1.1 1.7 V PF0200 NXP Semiconductors 11 GENERAL PRODUCT CHARACTERISTICS 4.3.2 Current consumption Table 7. Current consumption summary Consumer TA = -40 to 85 °C and Extended Industrial TA = -40 to 105 °C, VIN = 3.6 V, VDDIO = 1.7 to 3.6 V, LICELL = 1.8 to 3.3 V, VSNVS = 3.0 V, typical external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VDDIO = 3.3 V, LICELL = 3.0 V, VSNVS = 3.0 V and 25 °C, unless otherwise noted. Mode PF0200 conditions System Conditions Typ. Max. Unit (15),(16),(19) VSNVS from LICELL All other blocks off VIN = 0.0 V VSNVSVOLT[2:0] = 110 No load on VSNVS 4.0 7.0 μA Off (15)(17) VSNVS from VIN or LICELL Wake-up from PWRON active 32 k RC on All other blocks off VIN ≥ UVDET No load on VSNVS, PMIC able to wake-up 17 25 μA Sleep (18) VSNVS from VIN Wake-up from PWRON active Trimmed reference active SW3A/B PFM Trimmed 16 MHz RC off 32 k RC on VREFDDR disabled 122 220(20) No load on VSNVS. DDR memories in self refresh 122 250(21) VSNVS from either VIN or LICELL SW1A/B combined in PFM SW2 in PFM SW3A/B combined in PFM SWBST off Trimmed 16 MHz RC enabled Trimmed reference active VGEN1-6 enabled VREFDDR enabled No load on VSNVS. Processor enabled in low power mode. All rails powered on except boost (load = 0 mA) 270 430(20) 270 525(21) Coin Cell Standby (18) Notes 15. 16. 17. 18. 19. 20. 21. μA μA At 25 °C only. Refer to Figure 4 for Coin Cell mode characteristics over temperature. When VIN is below the UVDET threshold, in the range of 1.8 V ≤ VIN < 2.65 V, the quiescent current increases by 50 μA, typically. For PFM operation, headroom should be 300 mV or greater. Additional current may be drawn in the coin cell mode when RESETBMCU is pulled up to VSNVS due an internal path from RESETBMCU to VIN. The additional current is UVDET • PWRON_CFG = 1, for power button debounce timing In addition, when the 16 MHz is active in the ON mode, the debounce times in Table 25 are referenced to the 32 kHz derived from the 16 MHz clock. The exceptions are the LOWVINI and PWRONI interrupts, which are referenced to the 32 kHz untrimmed clock. Table 15. 16 MHz clock specifications Consumer TA = -40 to 85 °C and Extended Industrial TA = -40 to 105 °C, VIN = 2.8 to 4.5 V, LICELL = 1.8 to 3.3 V and typical external component values. Typical values are characterized at VIN = 3.6 V, LICELL = 3.0 V, and 25 °C, unless otherwise noted. Symbol Min. Typ. Max. Units Operating Voltage From VIN 2.8 – 4.5 V f16MHZ 16 MHz Clock Frequency 14.7 16 17.3 MHz f2MHZ 2.0 MHz Clock Frequency 1.84 – 2.16 MHz VIN16MHz Parameters Notes (26) Notes 26. 2.0 MHz clock is derived from the 16 MHz clock. 6.2.1 Clock adjustment The 16 MHz clock and hence the switching frequency of the regulators, can be adjusted to improve the noise integrity of the system. By changing the factory trim values of the 16MHz clock, the user may add an offset as small as ±3.0% of the nominal frequency. 6.3 Bias and references block description 6.3.1 Internal core voltage references All regulators use the main bandgap as the reference. The main bandgap is bypassed with a capacitor at VCOREREF. The bandgap and the rest of the core circuitry are supplied from VCORE. The performance of the regulators is directly dependent on the performance of the bandgap. No external DC loading is allowed on VCORE, VCOREDIG, or VCOREREF. VCOREDIG is kept powered as long as there is a valid supply and/or valid coin cell. Table 16 shows the main characteristics of the core circuitry. PF0200 22 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 16. Core voltages electrical specifications(28) Consumer TA = -40 to 85 °C and Extended Industrial TA = -40 to 105 °C, VIN = 2.8 to 4.5 V, LICELL = 1.8 to 3.3 V, and typical external component values. Typical values are characterized at VIN = 3.6 V, LICELL = 3.0 V, and 25 °C, unless otherwise noted. Symbol Parameters Min. Typ. Max. Units Notes – – 1.5 1.3 – – V (27) – – 2.775 0.0 – – V (27) Output Voltage – 1.2 – V (27) VCOREREFACC Absolute Accuracy – 0.5 – % VCOREREFTACC Temperature Drift – 0.25 – % VCOREDIG (digital core supply) Output Voltage ON mode Coin cell mode and OFF VCOREDIG VCORE (Analog core supply) Output Voltage ON mode and charging OFF and Coin cell mode VCORE VCOREREF (bandgap / regulator reference) VCOREREF Notes 27. 3.0 V < VIN < 4.5 V, no external loading on VCOREDIG, VCORE, or VCOREREF. Extended operation down to UVDET, but no system malfunction. 28. For information only. 6.3.1.1 External components Table 17. External components for core voltages 6.3.2 Regulator Capacitor value (μF) VCOREDIG 1.0 VCORE 1.0 VCOREREF 0.22 VREFDDR voltage reference VREFDDR is an internal PMOS half supply voltage follower capable of supplying up to 10 mA. The output voltage is at one half the input voltage. Its typically used as the reference voltage for DDR memories. A filtered resistor divider is utilized to create a low-frequency pole. This divider then utilizes a voltage follower to drive the load. VINREFDDR CHALF1 100 nf VINREFDDR VHALF CHALF2 100 nf _ + Discharge VREFDDR VREFDDR CREFDDR 1.0 uf Figure 7. VREFDDR block diagram PF0200 NXP Semiconductors 23 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS 6.3.2.1 VREFDDR control register The VREFDDR voltage reference is controlled by a single bit in VREFDDCRTL register in Table 18. Table 18. Register VREFDDCRTL - ADDR 0x6A Name Bit # R/W Default 3:0 – 0x00 UNUSED 4 R/W 0x00 Enable or disables VREFDDR output voltage 0 = VREFDDR Disabled 1 = VREFDDR Enabled 7:5 – 0x00 UNUSED UNUSED VREFDDREN UNUSED Description External components Table 19. VREFDDR external components(29) Capacitor VINREFDDR (30) to VHALF Capacitance (μF) 0.1 VHALF to GND 0.1 VREFDDR 1.0 Notes 29. Use X5R or X7R capacitors. 30. VINREFDDR to GND, 1.0 μF minimum capacitance is provided by buck regulator output. VREFDDR specifications Table 20. VREFDDR electrical characteristics Consumer TA = -40 to 85 °C and Extended Industrial TA = -40 to 105 °C, VIN = 3.6 V, IREFDDR = 0.0 mA, VINREFDDR = 1.5 V and typical external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, IREFDDR = 0.0 mA, VINREFDDR = 1.5 V, and 25 °C, unless otherwise noted. Symbol Parameter Min. Typ. Max. Unit Notes VREFDDR VINREFDDR Operating Input Voltage Range 1.2 – 1.8 V IREFDDR Operating Load Current Range 0.0 – 10 mA Current Limit IREFDDR when VREFDDR is forced to VINREFDDR/4 10.5 15 25 mA Quiescent Current – 8.0 – μA Output Voltage 1.2 V < VINREFDDR < 1.8 V 0.0 mA < IREFDDR < 10 mA – VINREFDDR/ 2 – V IREFDDRLIM IREFDDRQ (31) Active mode – DC VREFDDR VREFDDRTOL Output Voltage Tolerance (TA = -40 to 85 °C) 1.2 V < VINREFDDR < 1.8 V 0.6 mA ≤ IREFDDR ≤ 10 mA –1.0 – 1.0 % VREFDDRTOL Output Voltage Tolerance (TA = -40 to 85 °C), applicable only to the extended Industrial version 1.2 V < VINREFDDR < 1.8 V 0.6 mA ≤ IREFDDR ≤ 10 mA –1.20 – 1.2 % VREFDDRLOR Load Regulation 1.0 mA < IREFDDR < 10 mA 1.2 V < VINREFDDR < 1.8 V – 0.40 – mV/mA PF0200 24 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 20. VREFDDR electrical characteristics (continued) Consumer TA = -40 to 85 °C and Extended Industrial TA = -40 to 105 °C, VIN = 3.6 V, IREFDDR = 0.0 mA, VINREFDDR = 1.5 V and typical external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, IREFDDR = 0.0 mA, VINREFDDR = 1.5 V, and 25 °C, unless otherwise noted. Symbol Parameter Min. Typ. Max. Unit tONREFDDR Turn-on Time Enable to 90% of end value VINREFDDR = 1.2 V, 1.8 V IREFDDR = 0.0 mA – – 100 μs tOFFREFDDR Turn-off Time Disable to 10% of initial value VINREFDDR = 1.2 V, 1.8 V IREFDDR = 0.0 mA – – 10 ms VREFDDROSH Start-up Overshoot VINREFDDR = 1.2 V, 1.8 V IREFDDR = 0.0 mA – 1.0 6.0 % VREFDDRTLR Transient Load Response VINREFDDR = 1.2 V, 1.8 V – 5.0 – mV Notes Active mode – AC Notes 31. When VREFDDR is off there is a quiescent current of 1.5 μA typical. 6.4 Power generation 6.4.1 Modes of operation The operation of the PF0200 can be reduced to five states, or modes: ON, OFF, Sleep, Standby, and Coin Cell. Figure 8 shows the state diagram of the PF0200, along with the conditions to enter and exit from each state. PF0200 NXP Semiconductors 25 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Coin Cell VIN < UVDET VIN < UVDET VIN > UVDET PWRON = 0 held >= 4.0 sec Any SWxOMODE bits=1 & PWRONRSTEN = 1 (PWRON_CFG=1) VIN < UVDET Sleep PWRON = 0 Any SWxOMODE bits=1 (PWRON_CFG=0) Or PWRON=0 held >= 4.0 sec Any SWxOMODE bits=1 & PWRONRSTEN = 1 (PWRON_CFG=1) VIN < UVDET PWRON = 0 Any SWxOMODE bits=1 (PWRON_CFG=0) Or PWRON=0 held >= 4.0 sec Any SWxOMODE bits=1 & PWRONRSTEN = 1 (PWRON_CFG=1) Thermal shutdown PWRON=1 & VIN > UVDET (PWRON_CFG =0) Or PWRON= 0 < 4.0 sec & VIN > UVDET (PWRON_CFG=1) PWRON=1 & VIN > UVDET (PWRON_CFG = 0) Or PWRON= 0 < 4.0 sec & VIN > UVDET (PWRON_CFG=1) OFF PWRON = 0 All SWxOMODE bits= 0 (PWRON_CFG = 0) Or PWRON = 0 held >= 4.0 sec All SWxOMODE bits= 0 & PWRONRSTEN = 1 (PWRON_CFG = 1) ON Thermal shudown STANDBY asserted STANDBY de-asserted Standby PWRON = 0 All SWxOMODE bits= 0 (PWRON_CFG = 0) Or PWRON = 0 held >= 4.0 sec All SWxOMODE bits= 0 & PWRONRSTEN = 1 (PWRON_CFG = 1) Thermal shutdown Figure 8. State diagram To complement the state diagram in Figure 8, a description of the states is provided in following sections. Note that VIN must exceed the rising UVDET threshold to allow a power up. Refer to Table 27 for the UVDET thresholds. Additionally, I2C control is not possible in the Coin Cell mode and the interrupt signal, INTB, is only active in Sleep, Standby, and ON states. 6.4.1.1 ON mode The PF0200 enters the On mode after a turn-on event. RESETBMCU is de-asserted, high, in this mode of operation. 6.4.1.2 OFF mode The PF0200 enters the Off mode after a turn-off event. A thermal shutdown event also forces the PF0200 into the Off mode. Only VCOREDIG and VSNVS are powered in the mode of operation. To exit the Off mode, a valid turn-on event is required. RESETBMCU is asserted, LOW, in this mode. 6.4.1.3 Standby mode • Depending on STANDBY pin configuration, Standby is entered when the STANDBY pin is asserted. This is typically used for lowpower mode of operation. • When STANDBY is de-asserted, Standby mode is exited. PF0200 26 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS A product may be designed to go into a Low-power mode after periods of inactivity. The STANDBY pin is provided for board level control of going in and out of such deep sleep modes (DSM). When a product is in DSM, it may be able to reduce the overall platform current by lowering the regulator output voltage, changing the operating mode of the regulators or disabling some regulators. The configuration of the regulators in Standby is pre-programmed through the I2C interface. Note that the STANDBY pin is programmable for Active High or Active Low polarity, and that decoding of a Standby event will take into account the programmed input polarity as shown in Table 21. When the PF0200 is powered up first, regulator settings for the Standby mode are mirrored from the regulator settings for the ON mode. To change the STANDBY pin polarity to Active Low, set the STANDBYINV bit via software first, and then change the regulator settings for Standby mode as required. For simplicity, STANDBY will generally be referred to as active high throughout this document. Table 21. Standby Pin and polarity control STANDBY (Pin)(33) STANDBYINV (I2C bit)(34) STANDBY Control (32) 0 0 0 0 1 1 1 0 1 1 1 0 Notes 32. STANDBY = 0: System is not in Standby, STANDBY = 1: System is in Standby 33. The state of the STANDBY pin only has influence in On mode. 34. Bit 6 in Power Control Register (ADDR - 0x1B) Since STANDBY pin activity is driven asynchronously to the system, a finite time is required for the internal logic to qualify and respond to the pin level changes. A programmable delay is provided to hold off the system response to a Standby event. This allows the processor and peripherals some time after a standby instruction has been received to terminate processes to facilitate seamless entering into Standby mode. When enabled (STBYDLY = 01, 10, or 11) per Table 22, STBYDLY will delay the Standby initiated response for the entire IC, until the STBYDLY counter expires. An allowance should be made for three additional 32 k cycles required to synchronize the Standby event. Table 22. STANDBY delay - initiated response STBYDLY[1:0](35) Function 00 No Delay 01 One 32 k period (default) 10 Two 32 k periods 11 Three 32 k periods Notes 35. Bits [5:4] in Power Control Register (ADDR - 0x1B) 6.4.1.4 Sleep mode • Depending on PWRON pin configuration, Sleep mode is entered when PWRON is de-asserted and SWxOMODE bit is set. • To exit Sleep mode, assert the PWRON pin. In the Sleep mode, the regulator will use the set point as programmed by SW1ABOFF[5:0] for SW1A/B and by SWxOFF[6:0] for SW2 and SW3A/B. The activated regulators will maintain settings for this mode and voltage until the next turn-on event. Table 23 shows the control bits in Sleep mode. During Sleep mode, interrupts are active and the INTB pin will report any unmasked fault event. PF0200 NXP Semiconductors 27 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 23. Regulator mode control SWxOMODE Off operational mode (sleep) (36) 0 Off 1 PFM Notes 36. For sleep mode, an activated switching regulator, should use the off mode set point as programmed by SW1ABOFF[5:0] for SW1A/B and SWxOFF[6:0] for SW2 and SW3A/B. 6.4.1.5 Coin cell mode In the Coin Cell state, the coin cell is the only valid power source (VIN = 0.0 V) to the PMIC. No turn-on event is accepted in the Coin Cell state. Transition to the OFF state requires that VIN surpasses UVDET threshold. RESETBMCU is held low in this mode. If the coin cell is depleted, a complete system reset will occur. At the next application of power and the detection of a Turn-on event, the system will be re-initialized with all I2C bits including those that reset on COINPORB, are restored to their default states. 6.4.2 State machine flow summary Table 24 provides a summary matrix of the PF0200 flow diagram to show the conditions needed to transition from one state to another. Table 24. State machine flow summary STATE Next state OFF Coin cell Sleep Standby ON OFF X VIN < UVDET X X PWRON_CFG = 0 PWRON = 1 & VIN > UVDET or PWRON_CFG = 1 PWRON = 0 < 4.0 s & VIN > UNDET Coin cell VIN > UVDET X X X X Thermal Shutdown Initial State Sleep PWRON_CFG = 1 PWRON = 0 ≥ 4.0 s Any SWxOMODE = 1 & PWRONRSTEN = 1 VIN < UVDET X X PWRON_CFG = 0 PWRON = 1 & VIN > UVDET or PWRON_CFG = 1 PWRON = 0 < 4.0 s & VIN > UNDET VIN < UVDET PWRON_CFG = 0 PWRON = 0 Any SWxOMODE = 1 or PWRON_CFG = 1 PWRON = 0 ≥ 4.0 s Any SWxOMODE = 1 & PWRONRSTEN = 1 X Standby de-asserted VIN < UVDET PWRON_CFG = 0 PWRON = 0 Any SWxOMODE = 1 or PWRON_CFG = 1 PWRON = 0 ≥ 4.0 s Any SWxOMODE = 1 & PWRONRSTEN = 1 Standby asserted X Thermal Shutdown Standby PWRON_CFG = 0 PWRON = 0 All SWxOMODE = 0 or PWRON_CFG = 1 PWRON = 0 ≥ 4.0 s All SWxOMODE = 0 & PWRONRSTEN = 1 Thermal Shutdown ON PWRON_CFG = 0 PWRON = 0 All SWxOMODE = 0 or PWRON_CFG = 1 PWRON = 0 ≥ 4.0 s All SWxOMODE = 0 & PWRONRSTEN = 1 PF0200 28 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS 6.4.2.1 Turn on events From OFF and Sleep modes, the PMIC is powered on by a turn-on event. The type of Turn-on event depends on the configuration of PWRON. PWRON may be configured as an active high when PWRON_CFG = 0, or as the input of a mechanical switch when PWRON_CFG = 1. VIN must be greater than UVDET for the PMIC to turn-on. When PWRON is configured as an active high and PWRON is high (pulled up to VSNVS) before VIN is valid, a VIN transition from 0.0 V to a voltage greater than UVDET is also a Turn-on event. See the State diagram, Figure 8, and the Table 24 for more details. Any regulator enabled in the Sleep mode will remain enabled when transitioning from Sleep to ON, i.e., the regulator will not be turned off and then on again to match the start-up sequence. The following is a more detailed description of the PWRON configurations: • If PWRON_CFG = 0, the PWRON signal is high and VIN > UVDET, the PMIC will turn on; the interrupt and sense bits, PWRONI and PWRONS respectively, will be set. • If PWRON_CFG = 1, VIN > UVDET and PWRON transitions from high to low, the PMIC will turn on; the interrupt and sense bits, PWRONI and PWRONS respectively, will be set. The sense bit will show the real time status of the PWRON pin. In this configuration, the PWRON input can be a mechanical switch debounced through a programmable debouncer, PWRONDBNC[1:0], to avoid a response to a very short (i.e., unintentional) key press. The interrupt is generated for both the falling and the rising edge of the PWRON pin. By default, a 30 ms interrupt debounce is applied to both falling and rising edges. The falling edge debounce timing can be extended with PWRONDBNC[1:0] as defined in the table below. The interrupt is cleared by software, or when cycling through the OFF mode. Table 25. PWRON hardware debounce bit settings Bits PWRONDBNC[1:0] State Turn on debounce (ms) Falling edge INT debounce (ms) Rising edge INT debounce (ms) 00 0.0 31.25 31.25 01 31.25 31.25 31.25 10 125 125 31.25 11 750 750 31.25 Notes 37. The sense bit, PWRONS, is not debounced and follows the state of the PWRON pin. 6.4.2.2 Turn off events PWRON pin The PWRON pin is used to power off the PF0200. The PWRON pin can be configured with OTP to power off the PMIC under the following two conditions: 1. PWRON_CFG bit = 0, SWxOMODE bit = 0 and PWRON pin is low. 2. PWRON_CFG bit = 1, SWxOMODE bit = 0, PWRONRSTEN = 1 and PWRON is held low for longer than 4.0 seconds. Alternatively, the system can be configured to restart automatically by setting the RESTARTEN bit. Thermal protection If the die temperature surpasses a given threshold, the thermal protection circuit will power off the PMIC to avoid damage. A turn-on event will not power on the PMIC while it is in thermal protection. The part will remain in Off mode until the die temperature decreases below a given threshold. There are no specific interrupts related to this other than the warning interrupt. See Power dissipation section for more detailed information. Undervoltage detection When the voltage at VIN drops below the undervoltage falling threshold, UVDET, the state machine will transition to the Coin Cell mode. PF0200 NXP Semiconductors 29 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS 6.4.3 Power tree The PF0200 PMIC features four buck regulators, one boost regulator, six general purpose LDOs, one switch/LDO combination, and a DDR voltage reference to supply voltages for the application processor and peripheral devices. The buck regulators as well as the boost regulator are supplied directly from the main input supply (VIN). The inputs to all of the buck regulators must be tied to VIN, whether they are powered on or off. The six general use LDO regulators are directly supplied from the main input supply or from the switching regulators depending on the application requirements. Since VREFDDR is intended to provide DDR memory reference voltage, it should be supplied by any rail supplying voltage to DDR memories; the typical application recommends the use of SW3 as the input supply for VREFDDR. VSNVS is supplied by either the main input supply or the coin cell. Refer to Table 26 for a summary of all power supplies provided by the PF0200. Table 26. Power tree summary Supply Output voltage (V) Step size (mV) Maximum load current (mA) SW1A/B 0.3 - 1.875 25 2500 SW2 0.4 - 3.3 25/50 1500 SW3A/B 0.4 - 3.3 25/50 1250(38) SWBST 5.00/5.05/5.10/5.15 50 600 VGEN1 0.80 – 1.55 50 100 VGEN2 0.80 – 1.55 50 250 VGEN3 1.8 – 3.3 100 100 VGEN4 1.8 – 3.3 100 350 VGEN5 1.8 – 3.3 100 100 VGEN6 1.8 – 3.3 100 200 VSNVS 1.0 - 3.0 NA 0.4 VREFDDR 0.5*SW3A_OUT NA 10 Notes 38. Current rating per independent phase, when SW3A/B is set in single phase, current capability is up to 2500 mA. Figure 9 shows a simplified power map with various recommended options to supply the different block within the PF0200, as well as the typical application voltage domain on the i.MX 6 application processors. Note that each application power tree is dependent upon the system’s voltage and current requirements, therefore a proper input voltage should be selected for the regulators. The minimum operating voltage for the main VIN supply is 2.8 V, for lower voltages proper operation is not guaranteed. However at initial power up, the input voltage must surpass the rising UVDET threshold before proper operation is guaranteed. Refer to the representative tables and text specifying each supply for information on performance metrics and operating ranges. Table 27 summarizes the UVDET thresholds. Table 27. UVDET threshold UVDET Threshold VIN Rising 3.1 V Falling 2.65 V PF0200 30 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS SW1A CORE (0.3 to 1.875 V), 1.25 A i.MX6X MCU VDDARM_IN VDDSOC_IN (0.3 to 1.875 V), 1.25 A SW2 VDDHIGH (0.4 to 3.3 V), 1.5 A VIN 2.8 - 4.5 V VDDHIGH_IN SW3A DDR CORE (0.4 to 3.3 V), 1.25 A SW3B DDR IO (0.4 to 3.3 V), 1.25 A SWBST 5.0 V, 0.6 A VIN MUX / COIN CHRG Coincell VINMAX = 3.4 V VGEN2 (0.80 to 1.55 V), 250 mA VGEN3 (1.8 to 3.3 V), 100 mA VIN VINMAX = 3.6 V VSNVS_IN USB_OTG DDR3 Peripherals VGEN4 (1.8 to 3.3 V), 350 mA VGEN5 (1.8 to 3.3 V), 100 mA VIN SW2 VSNVS 1.0 to 3.0 V, 400 uA VGEN1 (0.80 to 1.55 V), 100 mA VIN SW2 LDO_3p0 VREFDDR 0.5*VDDR, 10 mA SW3A/B SW2 VDD_DDR_IO VINMAX = 4.5 V VGEN6 (1.8 to 3.3 V), 200 mA Figure 9. PF0200 typical power map PF0200 NXP Semiconductors 31 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS 6.4.4 Buck regulators Each buck regulator is capable of operating in PFM, APS, and PWM switching modes. 6.4.4.1 Current limit Each buck regulator has a programmable current limit. In an overcurrent condition, the current is limited cycle-by-cycle. If the current limit condition persists for more than 8.0 ms, a fault interrupt is generated. 6.4.4.2 General control To improve system efficiency the buck regulators can operate in different switching modes. Changing between switching modes can occur by any of the following means: I2C programming, exiting/entering the Standby mode, exiting/entering Sleep mode, and load current variation. Available switching modes for buck regulators are presented in Table 28. Table 28. Switching mode description Mode Description OFF The regulator is switched off and the output voltage is discharged. PFM In this mode, the regulator is always in PFM mode, which is useful at light loads for optimized efficiency. PWM In this mode, the regulator is always in PWM mode operation regardless of load conditions. APS In this mode, the regulator moves automatically between pulse skipping mode and PWM mode depending on load conditions. During soft-start of the buck regulators, the controller transitions through the PFM, APS, and PWM switching modes. 3.0 ms (typical) after the output voltage reaches regulation, the controller transitions to the selected switching mode. Depending on the particular switching mode selected, additional ripple may be observed on the output voltage rail as the controller transitions between switching modes. Table 29 summarizes the Buck regulator programmability for Normal and Standby modes. Table 29. Regulator mode control SWxMODE[3:0] Normal mode Standby mode 0000 Off Off 0001 PWM Off 0010 Reserved Reserved 0011 PFM Off 0100 APS Off 0101 PWM PWM 0110 PWM APS 0111 Reserved Reserved 1000 APS APS 1001 Reserved Reserved 1010 Reserved Reserved 1011 Reserved Reserved 1100 APS PFM 1101 PWM PFM 1110 Reserved Reserved 1111 Reserved Reserved Transitioning between Normal and Standby modes can affect a change in switching modes as well as output voltage. The rate of the output voltage change is controlled by the Dynamic Voltage Scaling (DVS), explained in Dynamic voltage scaling. The output voltage options are the same for Normal and Standby modes for each regulator. PF0200 32 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS When in Standby mode, the regulator outputs the voltage programmed in its standby voltage register and will operate in the mode selected by the SWxMODE[3:0] bits. Upon exiting Standby mode, the regulator will return to its normal switching mode and its output voltage programmed in its voltage register. Any regulators whose SWxOMODE bit is set to “1” will enter Sleep mode if a PWRON turn-off event occurs, and any regulator whose SWxOMODE bit is set to “0” will be turned off. In Sleep mode, the regulator outputs the voltage programmed in its off (Sleep) voltage register and operates in the PFM mode. The regulator will exit the Sleep mode when a turn-on event occurs. Any regulator whose SWxOMODE bit is set to “1” will remain on and change to its normal configuration settings when exiting the Sleep state to the ON state. Any regulator whose SWxOMODE bit is set to “0” will be powered up with the same delay in the start-up sequence as when powering On from Off. At this point, the regulator returns to its default ON state output voltage and switch mode settings. Table 23 shows the control bits in Sleep mode. When Sleep mode is activated by the SWxOMODE bit, the regulator will use the set point as programmed by SW1ABOFF[5:0] for SW1A/B and by SWxOFF[6:0] for SW2 and SW3A/B. Dynamic voltage scaling To reduce overall power consumption, processor core voltages can be varied depending on the mode or activity level of the processor. 1. Normal operation: The output voltage is selected by I2C bits SW1AB[5:0] for SW1A/B and SWx[6:0] for SW2 and SW3A/B. A voltage transition initiated by I2C is governed by the DVS stepping rates shown in Table 32 and Table 33. 2. Standby Mode: The output voltage can be higher, or lower than in normal operation, but is typically selected to be the lowest state retention voltage of a given processor; it is selected by I2C bits SW1ABSTBY[5:0] for SW1A/B and by bits SWxSTBY[6:0] for SW2 and SW3A/B. Voltage transitions initiated by a Standby event are governed by the SW1ABDVSSPEED[1:0] and SWxDVSSPEED[1:0] I2C bits shown in Table 32 and Table 33, respectively. 3. Sleep Mode: The output voltage can be higher or lower than in normal operation, but is typically selected to be the lowest state retention voltage of a given processor; it is selected by I2C bits SW1ABOFF[5:0] for SW1A/B and by bits SWxOFF[6:0] for SW2, and SW3A/B. Voltage transitions initiated by a turn-off event are governed by the SW1ABDVSSPEED[1:0] and SWxDVSSPEED[1:0] I2C bits shown in Table 32 and Table 33, respectively. Table 30, Table 31, Table 32, and Table 33 summarize the set point control and DVS time stepping applied to all regulators. Table 30. DVS control logic for SW1A/B STANDBY Set Point Selected by 0 SW1AB[5:0] 1 SW1ABSTBY[5:0] Table 31. DVS control logic for SW2 and SW3A/B STANDBY Set Point Selected by 0 SWx[6:0] 1 SWxSTBY[6:0] Table 32. DVS speed selection for SW1A/B SW1ABDVSSPEED[1:0] Function 00 25 mV step each 2.0 μs 01 (default) 25 mV step each 4.0 μs 10 25 mV step each 8.0 μs 11 25 mV step each 16 μs PF0200 NXP Semiconductors 33 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 33. DVS speed selection for SW2 and SW3A/B SWxDVSSPEED[1:0] Function SWx[6] = 0 or SWxSTBY[6] = 0 Function SWx[6] = 1 or SWxSTBY[6] = 1 00 25 mV step each 2.0 μs 50 mV step each 4.0 μs 01 (default) 25 mV step each 4.0 μs 50 mV step each 8.0 μs 10 25 mV step each 8.0 μs 50 mV step each 16 μs 11 25 mV step each 16 μs 50 mV step each 32 μs The regulators have a strong sourcing capability and sinking capability in PWM mode, therefore the fastest rising and falling slopes are determined by the regulator in PWM mode. However, if the regulators are programmed in PFM or APS mode during a DVS transition, the falling slope can be influenced by the load. Additionally, as the current capability in PFM mode is reduced, controlled DVS transitions in PFM mode could be affected. Critically timed DVS transitions are best assured with PWM mode operation. The following diagram shows the general behavior for the regulators when initiated with I2C programming, or standby control. During the DVS period the overcurrent condition on the regulator should be masked. Requested Set Point Output Voltage with light Load Internally Controlled Steps Example Actual Output Voltage Output Voltage Initial Set Point Actual Output Voltage Internally Controlled Steps Voltage Change Request Request for Higher Voltage Possible Output Voltage Window Request for Lower Voltage Initiated by I2C Programming, Standby Control Figure 10. Voltage stepping with DVS Regulator phase clock The SWxPHASE[1:0] bits select the phase of the regulator clock as shown in Table 34. By default, each regulator is initialized at 90 ° out of phase with respect to each other. For example, SW1A/B is set to 0 °, SW2 is set to 90 ° and SW3A/B is set to 180 ° by default at power up. Table 34. Regulator phase clock selection SWxPHASE[1:0] Phase of clock sent to regulator (degrees) 00 0 01 90 10 180 11 270 The SWxFREQ[1:0] register is used to set the desired switching frequency for each one of the buck regulators. Table 36 shows the selectable options for SWxFREQ[1:0]. For each frequency, all phases will be available, this allows regulators operating at different frequencies to have different relative switching phases. However, not all combinations are practical. For example, 2.0 MHz, 90 ° and 4.0 MHz, 180 ° are the same in terms of phasing. Table 35 shows the optimum phasing when using more than one switching frequency. PF0200 34 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 35. Optimum phasing Frequencies Optimum phasing 1.0 MHz 2.0 MHz 0° 180 ° 1.0 MHz 4.0 MHz 0° 180 ° 2.0 MHz 4.0 MHz 0° 180 ° 1.0 MHz 2.0 MHz 4.0 MHz 0° 90 ° 90 ° Table 36. Regulator frequency configuration SWxFREQ[1:0] Frequency 00 1.0 MHz 01 2.0 MHz 10 4.0 MHz 11 Reserved Programmable maximum current The maximum current, ISWxMAX, of each buck regulator is programmable. This allows the use of smaller inductors where lower currents are required. Programmability is accomplished by choosing the number of paralleled power stages in each regulator. The SWx_PWRSTG[2:0] bits on the Extended page 2 of the register map control the number of power stages. See Table 37 for the programmable options. Bit[0] must always be enabled to ensure the stage with the current sensor is chosen. The default setting, SWx_PWRSTG[2:0] = 111, represents the highest maximum current. The current limit for each option is also scaled by the percentage of power stages that are enabled. Table 37. Programmable current configuration Regulators Control bits % of power stages enabled SW1AB_PWRSTG[2:0] SW1AB ISW1ABMAX 0 0 1 40% 1.0 0 1 1 80% 2.0 1 0 1 60% 1.5 1 1 1 100% 2.5 SW2_PWRSTG[2:0] SW2 ISW2MAX 0 0 1 38% 0.55 0 1 1 75% 1.125 1 0 1 63% 0.95 1 1 1 100% 1.5 SW3A_PWRSTG[2:0] SW3A Rated current (A) ISW3AMAX 0 0 1 40% 0.5 0 1 1 80% 1.0 1 0 1 60% 0.75 1 1 1 100% 1.25 PF0200 NXP Semiconductors 35 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 37. Programmable current configuration (continued) Regulators Control bits % of power stages enabled Rated current (A) SW3B_PWRSTG[2:0] SW3B 6.4.4.3 ISW3BMAX 0 0 1 40% 0.5 0 1 1 80% 1.0 1 0 1 60% 0.75 1 1 1 100% 1.25 SW1A/B SW1A/B is a 2.5 A single phase regulator. The SW1ALX and SW1BLX pins should be connected together on the board. SW1_CONFIG[1:0] = 01 is the only configuration supported. The single phase configuration is programmed by OTP by using SW1_CONFIG[1:0] bits in the register map Extended page 1, as shown in Table 38. . Table 38. SW1 configuration SW1_CONFIG[1:0] Description 00 Reserved 01 A/B Single Phase 10 Reserved 11 Reserved SW1A/B single phase In this configuration, SW1A/B is connected as a single phase with a single inductor. This configuration allows reduced component count by using only one inductor for SW1A/B. Figure 11 shows the physical connection for SW1A/B in single phase. VIN SW1AIN SW1AMODE ISENSE CINSW1A SW1A/B SW1ALX LSW1A Controller Driver COSW1A SW1AFAULT Internal Compensation SW1FB I2C Z2 Z1 EA VREF DAC I2C Interface VIN SW1BIN SW1BMODE ISENSE CINSW1B SW1BLX EP Controller Driver SW1BFAULT Figure 11. SW1A/B single phase block diagram Both SW1ALX and SW1BLX nodes operate at the same DVS, frequency, and phase configured by the SW1ABCONF register. PF0200 36 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS SW1A/B setup and control registers SW1A/B output voltage is programmable from 0.300 to 1.875 V in steps of 25 mV. The output voltage set point is independently programmed for Normal, Standby, and Sleep mode by setting the SW1AB[5:0], SW1ABSTBY[5:0], and SW1ABOFF[5:0] bits respectively. Table 39 shows the output voltage coding for SW1A/B. Note: Output voltages of 0.6 V and below are not supported. Table 39. SW1A/B output voltage configuration Set point SW1AB[5:0] SW1ABSTBY[5:0] SW1ABOFF[5:0] SW1AB output (V) Set point SW1AB[5:0] SW1ABSTBY[5:0] SW1ABOFF[5:0] SW1AB output (V) 0 000000 0.3000 32 100000 1.1000 1 000001 0.3250 33 100001 1.1250 2 000010 0.3500 34 100010 1.1500 3 000011 0.3750 35 100011 1.1750 4 000100 0.4000 36 100100 1.2000 5 000101 0.4250 37 100101 1.2250 6 000110 0.4500 38 100110 1.2500 7 000111 0.4750 39 100111 1.2750 8 001000 0.5000 40 101000 1.3000 9 001001 0.5250 41 101001 1.3250 10 001010 0.5500 42 101010 1.3500 11 001011 0.5750 43 101011 1.3750 12 001100 0.6000 44 101100 1.4000 13 001101 0.6250 45 101101 1.4250 14 001110 0.6500 46 101110 1.4500 15 001111 0.6750 47 101111 1.4750 16 010000 0.7000 48 110000 1.5000 17 010001 0.7250 49 110001 1.5250 18 010010 0.7500 50 110010 1.5500 19 010011 0.7750 51 110011 1.5750 20 010100 0.8000 52 110100 1.6000 21 010101 0.8250 53 110101 1.6250 22 010110 0.8500 54 110110 1.6500 23 010111 0.8750 55 110111 1.6750 24 011000 0.9000 56 111000 1.7000 25 011001 0.9250 57 111001 1.7250 26 011010 0.9500 58 111010 1.7500 27 011011 0.9750 59 111011 1.7750 28 011100 1.0000 60 111100 1.8000 29 011101 1.0250 61 111101 1.8250 30 011110 1.0500 62 111110 1.8500 31 011111 1.0750 63 111111 1.8750 Table 40 provides a list of registers used to configure and operate SW1A/B and a detailed description on each one of these register is provided in Table 41 through Table 45. PF0200 NXP Semiconductors 37 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 40. SW1A/B register summary Register Address Output SW1ABVOLT 0x20 SW1AB Output voltage set point in normal operation SW1ABSTBY 0x21 SW1AB Output voltage set point on Standby SW1ABOFF 0x22 SW1AB Output voltage set point on Sleep SW1ABMODE 0x23 SW1AB Switching Mode selector register SW1ABCONF 0x24 SW1AB DVS, Phase, Frequency and ILIM configuration Table 41. Register SW1ABVOLT - ADDR 0x20 Name Bit # R/W Default Description SW1AB 5:0 R/W 0x00 Sets the SW1AB output voltage during normal operation mode. See Table 39 for all possible configurations. UNUSED 7:6 – 0x00 UNUSED Table 42. Register SW1ABSTBY - ADDR 0x21 Name Bit # R/W Default Description SW1ABSTBY 5:0 R/W 0x00 Sets the SW1AB output voltage during Standby mode. See Table 39 for all possible configurations. UNUSED 7:6 – 0x00 UNUSED Table 43. Register SW1ABOFF - ADDR 0x22 Name Bit # R/W Default Description SW1ABOFF 5:0 R/W 0x00 Sets the SW1AB output voltage during Sleep mode. See Table 39 for all possible configurations. UNUSED 7:6 – 0x00 UNUSED Table 44. Register SW1ABMODE - ADDR 0x23 Name Bit # R/W Default 3:0 R/W 0x80 Sets the SW1AB switching operation mode. See Table 29 for all possible configurations. UNUSED 4 – 0x00 UNUSED SW1ABOMODE 5 R/W 0x00 Set status of SW1AB when in Sleep mode 0 = OFF 1 = PFM 7:6 – 0x00 UNUSED SW1ABMODE UNUSED Description PF0200 38 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 45. Register SW1ABCONF - ADDR 0x24 Name Bit # R/W Default Description SW1ABILIM 0 R/W 0x00 SW1AB current limit level selection 0 = High level current limit 1 = Low level current limit UNUSED 1 R/W 0x00 Unused SW1ABFREQ 3:2 R/W 0x00 SW1A/B switching frequency selector See Table 36. SW1ABPHASE 5:4 R/W 0x00 SW1A/B Phase clock selection See Table 34. SW1ABDVSSPEED 7:6 R/W 0x00 SW1A/B DVS speed selection See Table 32. SW1A/B external components Table 46. SW1A/B external component recommendations Components Description Mode A/B Single Phase CINSW1A(39) SW1A Input capacitor 4.7 μF CIN1AHF(39) SW1A Decoupling input capacitor 0.1 μF CINSW1B(39) SW1B Input capacitor 4.7 μF CIN1BHF (39) SW1B Decoupling input capacitor COSW1AB(39) SW1A/B Output capacitor LSW1A SW1A/B Inductor 0.1 μF 4 x 22 μF 1.0 μH DCR = 12 mΩ ISAT = 4.5 A Notes 39. Use X5R or X7R capacitors. PF0200 NXP Semiconductors 39 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS SW1A/B specifications Table 47. SW1A/B electrical characteristics All parameters are specified at Consumer TA = -40 to 85 °C and Extended Industrial TA = -40 to 105 °C, VIN = VINSW1x = 3.6 V, VSW1AB = 1.2 V, ISW1AB = 100 mA, SW1AB_PWRSTG[2:0] = [111], typical external component values, fSW1AB = 2.0 MHz, unless otherwise noted. Typical values are characterized at VIN = VINSW1x = 3.6 V, VSW1AV = 1.2 V, ISW1AB = 100 mA, SW1AB_PWRSTG[2:0] = [111], and 25 °C, unless otherwise noted. Symbol Parameter Min. Typ. Max. Unit Notes SW1A/B (single phase) VINSW1A VINSW1B Operating Input Voltage 2.8 – 4.5 V VSW1AB Nominal Output Voltage – Table 39 – V -25 -3.0% - 25 3.0% -65 -45 -3.0% – – – 65 45 3.0% – – 2500 4.5 3.3 6.5 4.9 8.5 6.4 VSW1ABACC Output Voltage Accuracy • PWM, APS, 2.8 V < VIN < 4.5 V, 0 < ISW1AB < 2.5 A 0.625 V ≤ VSW1AB ≤ 1.450 V 1.475 V ≤ VSW1AB ≤ 1.875 V • PFM, steady state, 2.8 V < VIN < 4.5 V, 0 < ISW1AB < 150 mA 0.625 V < VSW1AB < 0.675 V 0.7 V < VSW1AB < 0.85 V 0.875 V < VSW1AB < 1.875 V ISW1AB Rated Output Load Current, 2.8 V < VIN < 4.5 V, 0.625 V < VSW1AB < 1.875 V ISW1ABLIM Current Limiter Peak Current Detection • SW1A/B Single Phase (current through inductor) SW1ABILIM = 0 SW1ABILIM = 1 mV % (40) mA (41) A (41) VSW1ABOSH Start-up Overshoot ISW1AB = 0.0 mA DVS clk = 25 mV/4 μs, VIN = VINSW1x = 4.5 V, VSW1AB = 1.875 V – – 66 mV tONSW1AB Turn-on Time Enable to 90% of end value ISW1AB = 0.0 mA DVS clk = 25 mV/4 μs, VIN = VINSW1x = 4.5 V, VSW1AB = 1.875 V – – 500 µs fSW1AB Switching Frequency SW1ABFREQ[1:0] = 00 SW1ABFREQ[1:0] = 01 SW1ABFREQ[1:0] = 10 – – – 1.0 2.0 4.0 – – – ηSW1AB Efficiency (Single Phase) • VIN = 3.6 V, fSW1AB = 2.0 MHz, LSW1AB = 1.0 μH PFM, 0.9 V, 1.0 mA PFM, 1.2 V, 50 mA APS, PWM, 1.2 V, 500 mA APS, PWM, 1.2 V, 750 mA APS, PWM, 1.2 V, 1250 mA APS, PWM, 1.2 V, 2500 mA – – – – – – 82 84 86 87 82 71 – – – – – – Output Ripple – 10 – mV VSW1ABLIR Line Regulation (APS, PWM) – – 20 mV VSW1ABLOR DC Load Regulation (APS, PWM) – – 20 mV VSW1ABLOTR Transient Load Regulation • Transient load = 0 to 1.25 A, di/dt = 100 mA/μs Overshoot Undershoot – – – – 50 50 ΔVSW1AB MHz % mV PF0200 40 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 47. SW1A/B electrical characteristics (continued) All parameters are specified at Consumer TA = -40 to 85 °C and Extended Industrial TA = -40 to 105 °C, VIN = VINSW1x = 3.6 V, VSW1AB = 1.2 V, ISW1AB = 100 mA, SW1AB_PWRSTG[2:0] = [111], typical external component values, fSW1AB = 2.0 MHz, unless otherwise noted. Typical values are characterized at VIN = VINSW1x = 3.6 V, VSW1AV = 1.2 V, ISW1AB = 100 mA, SW1AB_PWRSTG[2:0] = [111], and 25 °C, unless otherwise noted. Symbol Parameter Min. Typ. Max. Unit – – 18 235 – – µA Notes SW1A/B (single phase) (continued) ISW1ABQ Quiescent Current PFM Mode APS Mode RONSW1AP SW1A P-MOSFET RDSON VINSW1A = 3.3 V – 215 245 mΩ RONSW1AN SW1A N-MOSFET RDSON VINSW1A = 3.3 V – 258 326 mΩ ISW1APQ SW1A P-MOSFET Leakage Current VINSW1A = 4.5 V – – 7.5 µA ISW1ANQ SW1A N-MOSFET Leakage Current VINSW1A = 4.5 V – – 2.5 µA RONSW1BP SW1B P-MOSFET RDSON VINSW1B = 3.3 V – 215 245 mΩ RONSW1BN SW1B N-MOSFET RDSON VINSW1B = 3.3 V – 258 326 mΩ ISW1BPQ SW1B P-MOSFET Leakage Current VINSW1B = 4.5 V – – 7.5 µA ISW1BNQ SW1B N-MOSFET Leakage Current VINSW1B = 4.5 V – – 2.5 µA Discharge Resistance – 600 – Ω RSW1ABDIS Notes 40. Accuracy specification is inclusive of load and line regulation. 41. Current rating of SW1AB supports the Power Virus mode of operation of the i.MX6X processor. SW1AB single phase 100 90 Efficiency (%) 80 70 ) % ( 60 yc n 50 ie icf 40 fE 30 PFM - Vout = 1.2V 20 APS - Vout = 1.2V 10 PWM - Vout = 1.2v 0 0.1 1 10 100 1000 Load Current (mA) Figure 12. SW1AB efficiency waveforms PF0200 NXP Semiconductors 41 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS 6.4.4.4 SW2 SW2 is a single phase, 1.5 A rated buck regulator. Table 28 describes the modes, and Table 29 show the options for the SWxMODE[3:0] bits. Figure 13 shows the block diagram and the external component connections for SW2 regulator. VIN SW2IN SW2MODE ISENSE CINSW2 SW2 Controller SW2LX Driver LSW2 COSW2 SW2FAULT EP Internal Compensation SW2FB I2C Interface I2C Z2 Z1 VREF EA DAC Figure 13. SW2 block diagram SW2 setup and control registers SW2 output voltage is programmable from 0.400 to 3.300 V; however, bit SW2[6] in register SW2VOLT is read-only during normal operation. Its value is determined by the default configuration, or may be changed by using the OTP registers. Therefore, once SW2[6] is set to “0”, the output will be limited to the lower output voltages from 0.400 to 1.975 V with 25 mV increments, as determined by bits SW2[5:0]. Likewise, once bit SW2[6] is set to “1”, the output voltage will be limited to the higher output voltage range from 0.800 to 3.300 V with 50 mV increments, as determined by bits SW2[5:0]. In order to optimize the performance of the regulator, it is recommended that only voltages from 2.000 to 3.300 V be used in the high range, and the lower range be used for voltages from 0.400 to 1.975 V. The output voltage set point is independently programmed for Normal, Standby, and Sleep mode by setting the SW2[5:0], SW2STBY[5:0] and SW2OFF[5:0] bits, respectively. However, the initial state of bit SW2[6] will be copied into bits SW2STBY[6], and SW2OFF[6] bits. Therefore, the output voltage range will remain the same in all three operating modes. Table 48 shows the output voltage coding valid for SW2. Note: Output voltages of 0.6 V and below are not supported. Table 48. SW2 output voltage configuration Low output voltage range(42) High output voltage range Set point SW2[6:0] SW2STBY[6:0] SW2OFF[6:0] SW2 output Set point SW2[6:0] SW2STBY[6:0] SW2OFF[6:0] SW2 output 0 0000000 0.4000 64 1000000 0.8000 1 0000001 0.4250 65 1000001 0.8500 2 0000010 0.4500 66 1000010 0.9000 3 0000011 0.4750 67 1000011 0.9500 4 0000100 0.5000 68 1000100 1.0000 5 0000101 0.5250 69 1000101 1.0500 6 0000110 0.5500 70 1000110 1.1000 7 0000111 0.5750 71 1000111 1.1500 8 0001000 0.6000 72 1001000 1.2000 9 0001001 0.6250 73 1001001 1.2500 10 0001010 0.6500 74 1001010 1.3000 11 0001011 0.6750 75 1001011 1.3500 PF0200 42 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 48. SW2 output voltage configuration (continued) Low output voltage range(42) High output voltage range Set point SW2[6:0] SW2STBY[6:0] SW2OFF[6:0] SW2 output Set point SW2[6:0] SW2STBY[6:0] SW2OFF[6:0] SW2 output 12 0001100 0.7000 76 1001100 1.4000 13 0001101 0.7250 77 1001101 1.4500 14 0001110 0.7500 78 1001110 1.5000 15 0001111 0.7750 79 1001111 1.5500 16 0010000 0.8000 80 1010000 1.6000 17 0010001 0.8250 81 1010001 1.6500 18 0010010 0.8500 82 1010010 1.7000 19 0010011 0.8750 83 1010011 1.7500 20 0010100 0.9000 84 1010100 1.8000 21 0010101 0.9250 85 1010101 1.8500 22 0010110 0.9500 86 1010110 1.9000 23 0010111 0.9750 87 1010111 1.9500 24 0011000 1.0000 88 1011000 2.0000 25 0011001 1.0250 89 1011001 2.0500 26 0011010 1.0500 90 1011010 2.1000 27 0011011 1.0750 91 1011011 2.1500 28 0011100 1.1000 92 1011100 2.2000 29 0011101 1.1250 93 1011101 2.2500 30 0011110 1.1500 94 1011110 2.3000 31 0011111 1.1750 95 1011111 2.3500 32 0100000 1.2000 96 1100000 2.4000 33 0100001 1.2250 97 1100001 2.4500 34 0100010 1.2500 98 1100010 2.5000 35 0100011 1.2750 99 1100011 2.5500 36 0100100 1.3000 100 1100100 2.6000 37 0100101 1.3250 101 1100101 2.6500 38 0100110 1.3500 102 1100110 2.7000 39 0100111 1.3750 103 1100111 2.7500 40 0101000 1.4000 104 1101000 2.8000 41 0101001 1.4250 105 1101001 2.8500 42 0101010 1.4500 106 1101010 2.9000 43 0101011 1.4750 107 1101011 2.9500 44 0101100 1.5000 108 1101100 3.0000 45 0101101 1.5250 109 1101101 3.0500 46 0101110 1.5500 110 1101110 3.1000 47 0101111 1.5750 111 1101111 3.1500 48 0110000 1.6000 112 1110000 3.2000 PF0200 NXP Semiconductors 43 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 48. SW2 output voltage configuration (continued) Low output voltage range(42) High output voltage range Set point SW2[6:0] SW2STBY[6:0] SW2OFF[6:0] SW2 output Set point SW2[6:0] SW2STBY[6:0] SW2OFF[6:0] SW2 output 49 0110001 1.6250 113 1110001 3.2500 50 0110010 1.6500 114 1110010 3.3000 51 0110011 1.6750 115 1110011 Reserved 52 0110100 1.7000 116 1110100 Reserved 53 0110101 1.7250 117 1110101 Reserved 54 0110110 1.7500 118 1110110 Reserved 55 0110111 1.7750 119 1110111 Reserved 56 0111000 1.8000 120 1111000 Reserved 57 0111001 1.8250 121 1111001 Reserved 58 0111010 1.8500 122 1111010 Reserved 59 0111011 1.8750 123 1111011 Reserved 60 0111100 1.9000 124 1111100 Reserved 61 0111101 1.9250 125 1111101 Reserved 62 0111110 1.9500 126 1111110 Reserved 63 0111111 1.9750 127 1111111 Reserved Notes 42. For voltages less than 2.0 V, only use set points 0 to 63 Setup and control of SW2 is done through I2C registers listed in Table 49, and a detailed description of each one of the registers is provided in Tables 50 to Table 54. Table 49. SW2 register summary Register Address Description SW2VOLT 0x35 Output voltage set point on normal operation SW2STBY 0x36 Output voltage set point on Standby SW2OFF 0x37 Output voltage set point on Sleep SW2MODE 0x38 Switching Mode selector register SW2CONF 0x39 DVS, Phase, Frequency, and ILIM configuration Table 50. Register SW2VOLT - ADDR 0x35 Name Bit # R/W Default Description SW2 5:0 R/W 0x00 Sets the SW2 output voltage during normal operation mode. See Table 48 for all possible configurations. SW2 6 R 0x00 Sets the operating output voltage range for SW2. Set during OTP or TBB configuration only. See Table 48 for all possible configurations. UNUSED 7 – 0x00 UNUSED PF0200 44 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 51. Register SW2STBY - ADDR 0x36 Name SW2STBY Bit # R/W Default Description 5:0 R/W 0x00 Sets the SW2 output voltage during Standby mode. See Table 48 for all possible configurations. SW2STBY 6 R 0x00 Sets the operating output voltage range for SW2 on Standby mode. This bit inherits the value configured on bit SW2[6] during OTP or TBB configuration. See Table 48 for all possible configurations. UNUSED 7 – 0x00 UNUSED Table 52. Register SW2OFF - ADDR 0x37 Name Bit # R/W Default Description SW2OFF 5:0 R/W 0x00 Sets the SW2 output voltage during Sleep mode. See Table 48 for all possible configurations. SW2OFF 6 R 0x00 Sets the operating output voltage range for SW2 on Sleep mode. This bit inherits the value configured on bit SW2[6] during OTP or TBB configuration. See Table 48 for all possible configurations. UNUSED 7 – 0x00 UNUSED Table 53. Register SW2MODE - ADDR 0x38 Name Bit # R/W Default 3:0 R/W 0x80 Sets the SW2 switching operation mode. See Table 28 for all possible configurations. UNUSED 4 – 0x00 UNUSED SW2OMODE 5 R/W 0x00 Set status of SW2 when in Sleep mode 0 = OFF 1 = PFM 7:6 – 0x00 UNUSED SW2MODE UNUSED Description Table 54. Register SW2CONF - ADDR 0x39 Name Bit # R/W Default Description SW2ILIM 0 R/W 0x00 SW2 current limit level selection 0 = High level current limit 1 = Low level current limit UNUSED 1 R/W 0x00 Unused SW2FREQ 3:2 R/W 0x00 SW2 switching frequency selector. See Table 36. SW2PHASE 5:4 R/W 0x00 SW2 Phase clock selection. See Table 34. SW2DVSSPEED 7:6 R/W 0x00 SW2 DVS speed selection. See Table 33. PF0200 NXP Semiconductors 45 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS SW2 external components Table 55. SW2 external component recommendations Components SW2 Input capacitor (43) SW2 Decoupling input capacitor CINSW2 CIN2HF Description (43) COSW2(43) SW2 Output capacitor LSW2 SW2 Inductor Values 4.7 μF 0.1 μF 2 x 22 μF 1.0 μH DCR = 50 mΩ ISAT = 2.65 A Notes 43. Use X5R or X7R capacitors. SW2 specifications Table 56. SW2 electrical characteristics All parameters are specified at Consumer TA = -40 to 85 °C and Extended Industrial TA = -40 to 105 °C, VIN = VINSW2 = 3.6 V, VSW2 = 3.15 V, ISW2 = 100 mA, SW2_PWRSTG[2:0] = [111], typical external component values, fSW2 = 2.0 MHz, unless otherwise noted. Typical values are characterized at VIN = VINSW2 = 3.6 V, VSW2 = 3.15 V, ISW2 = 100 mA, SW2_PWRSTG[2:0] = [111], and 25 °C, unless otherwise noted. Symbol Parameter Min. Typ. Max. Unit Notes (44) Switch mode supply SW2 VINSW2 Operating Input Voltage 2.8 – 4.5 V VSW2 Nominal Output Voltage – Table 48 – V -25 -3.0% -6.0% – – – 25 3.0% 6.0% PFM, 2.8 V < VIN < 4.5 V, 0 < ISW2 ≤ 50 mA 0.625 V < VSW2 < 0.675 V 0.7 V < VSW2 < 0.85 V 0.875 V < VSW2 < 1.975 V 2.0 V < VSW2 < 3.3 V -65 -45 -3.0% -3.0% – – – – 65 45 3.0% 3.0% Rated Output Load Current 2.8 V < VIN < 4.5 V, 0.625 V < VSW2 < 3.3 V – – 2.1 1.57 VSW2ACC ISW2 ISW2LIM Output Voltage Accuracy • PWM, APS, 2.8 V < VIN < 4.5 V, 0 < ISW2 < 1.5 A 0.625 V < VSW2 < 0.85 V 0.875 V < VSW2 < 1.975 V 2.0 V < VSW2 < 3.3 V • Current Limiter Peak Current Detection • Current through Inductor SW2ILIM = 0 SW2ILIM = 1 mV % (45) 1500 mA (46) 3.0 2.25 3.9 2.93 A VSW2OSH Start-up Overshoot ISW2 = 0.0 mA DVS clk = 25 mV/4 μs, VIN = VINSW2 = 4.5 V – – 66 mV tONSW2 Turn-on Time Enable to 90% of end value ISW2 = 0.0 mA DVS clk = 50 mV/8 μs, VIN = VINSW2 = 4.5 V – – 550 µs – – – 1.0 2.0 4.0 – – – fSW2 Switching Frequency SW2FREQ[1:0] = 00 SW2FREQ[1:0] = 01 SW2FREQ[1:0] = 10 MHz PF0200 46 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 56. SW2 electrical characteristics (continued) All parameters are specified at Consumer TA = -40 to 85 °C and Extended Industrial TA = -40 to 105 °C, VIN = VINSW2 = 3.6 V, VSW2 = 3.15 V, ISW2 = 100 mA, SW2_PWRSTG[2:0] = [111], typical external component values, fSW2 = 2.0 MHz, unless otherwise noted. Typical values are characterized at VIN = VINSW2 = 3.6 V, VSW2 = 3.15 V, ISW2 = 100 mA, SW2_PWRSTG[2:0] = [111], and 25 °C, unless otherwise noted. Symbol Min. Typ. Max. – – – – – – 94 95 96 94 92 89 – – – – – – Output Ripple – 10 – mV VSW2LIR Line Regulation (APS, PWM) – – 20 mV VSW2LOR DC Load Regulation (APS, PWM) – – 20 mV VSW2LOTR Transient Load Regulation • Transient load = 0.0 mA to 1.0 A, di/dt = 100 mA/μs Overshoot Undershoot – – – – 50 50 Quiescent Current PFM Mode APS Mode (Low output voltage settings) APS Mode (High output voltage settings) – – – 23 145 305 – – – ηSW2 Parameter Efficiency • VIN = 3.6 V, fSW2 = 2.0 MHz, LSW2 = 1.0 μH PFM, 3.15 V, 1.0 mA PFM, 3.15 V, 50 mA APS, PWM, 3.15 V, 400 mA APS, PWM, 3.15 V, 600 mA APS, PWM, 3.15 V, 1000 mA APS, PWM, 3.15 V, 1500 mA Unit Notes % Switch mode supply SW2 (continued) ΔVSW2 ISW2Q mV µA RONSW2P SW2 P-MOSFET RDSON at VIN = VINSW2 = 3.3 V – 190 209 mΩ RONSW2N SW2 N-MOSFET RDSON at VIN = VINSW2 = 3.3 V – 212 255 mΩ ISW2PQ SW2 P-MOSFET Leakage Current VIN = VINSW2 = 4.5 V – – 12 µA ISW2NQ SW2 N-MOSFET Leakage Current VIN = VINSW2 = 4.5 V – – 4.0 µA RSW2DIS Discharge Resistance – 600 – Ω Notes 44. When output is set to > 2.6 V the output will follow the input down when VIN gets near 2.8 V. 45. 46. Accuracy specification is inclusive of load and line regulation. The higher output voltages available depend on the voltage drop in the conduction path as given by the following equation: (VINSW2 - VSW2) = ISW2* (DCR of Inductor +RONSW2P + PCB trace resistance). PF0200 NXP Semiconductors 47 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS 100 90 80 PFM - Vout = 3.15V 20 APS - Vout = 3.15V Efficiency (%) 70 ) (% 60 cy n 50 e ic if 40 fE 30 10 PWM - Vout = 3.15V 0 0.1 1 10 100 1000 Load Current (mA) Figure 14. SW2 efficiency waveforms 6.4.4.5 SW3A/B SW3A/B are 1.25 to 2.5 A rated buck regulators, depending on the configuration. Table 28 describes the available switching modes and Table 29 show the actual configuration options for the SW3xMODE[3:0] bits. SW3A/B can be configured in various phasing schemes, depending on the desired cost/performance trade-offs. The following configurations are available: • A single phase • Independent regulators The desired configuration is programmed in OTP by using the SW3_CONFIG[1:0] bits.Table 57 shows the options for the SW3CFG[1:0] bits. Table 57. SW3 Configuration SW3_CONFIG[1:0] Description 00 A/B Single Phase 01 A/B Single Phase 10 Reserved 11 A/B Independent SW3A/B single phase In this configuration, SW3ALX and SW3BLX are connected in single phase with a single inductor a shown in Figure 15. This configuration reduces cost and component count. Feedback is taken from the SW3AFB pin and the SW3BFB pin must be left open. Although control is from SW3A, registers of both regulators, SW3A and SW3B, must be identically set. PF0200 48 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS VIN SW3AIN SW3AMODE ISENSE CINSW3A SW3 SW3ALX LSW3A Controller Driver COSW3A SW3AFAULT Internal Compensation SW3AFB I2C Z2 Z1 VREF EA DAC I2C Interface VIN SW3BIN SW3BMODE ISENSE CINSW3B SW3BLX Controller Driver SW3BFAULT EP I2C Internal Compensation SW3BFB Z2 VREF Z1 EA DAC Figure 15. SW3A/B single phase block diagram PF0200 NXP Semiconductors 49 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS SW3A - SW3B independent outputs SW3A and SW3B can be configured as independent outputs as shown in Figure 16, providing flexibility for applications requiring more voltage rails with less current capability. Each output is configured and controlled independently by its respective I2C registers as shown in Table 59. VIN SW3AIN SW3AMODE ISENSE CINSW3A SW3A SW3ALX LSW3A Controller Driver COSW3A SW3AFAULT Internal Compensation SW3AFB I2C Z2 Z1 VREF EA DAC VIN SW3BIN SW3BLX LSW3B COSW3B I2C Interface ISENSE CINSW3B SW3B SW3BMODE Controller Driver SW3BFAULT EP Internal Compensation SW3BFB I2C Z2 Z1 EA VREF DAC Figure 16. SW3A/B independent output block diagram SW3A/B setup and control registers SW3A/B output voltage is programmable from 0.400 to 3.300 V; however, bit SW3x[6] in register SW3xVOLT is read-only during normal operation. Its value is determined by the default configuration, or may be changed by using the OTP registers. Therefore, once SW3x[6] is set to “0”, the output will be limited to the lower output voltages from 0.40 to 1.975 V with 25 mV increments, as determined by bits SW3x[5:0]. Likewise, once bit SW3x[6] is set to "1", the output voltage will be limited to the higher output voltage range from 0.800 to 3.300 V with 50 mV increments, as determined by bits SW3x[5:0]. In order to optimize the performance of the regulator, it is recommended that only voltages from 2.00 to 3.300 V be used in the high range and that that the lower range be used for voltages from 0.400 to 1.975 V. The output voltage set point is independently programmed for Normal, Standby, and Sleep mode by setting the SW3x[5:0], SW3xSTBY[5:0], and SW3xOFF[5:0] bits respectively; however, the initial state of the SW3x[6] bit will be copied into the SW3xSTBY[6] and SW3xOFF[6] bits. Therefore, the output voltage range will remain the same on all three operating modes. Table 58 shows the output voltage coding valid for SW3x. Note: Output voltages of 0.6 V and below are not supported. PF0200 50 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 58. SW3A/B output voltage configuration Low output voltage range(47) High output voltage range Set point SW3x[6:0] SW3xSTBY[6:0] SW3xOFF[6:0] SW3x output Set Point SW3x[6:0] SW3xSTBY[6:0] SW3xOFF[6:0] sw3xoutput 0 0000000 0.4000 64 1000000 0.8000 1 0000001 0.4250 65 1000001 0.8500 2 0000010 0.4500 66 1000010 0.9000 3 0000011 0.4750 67 1000011 0.9500 4 0000100 0.5000 68 1000100 1.0000 5 0000101 0.5250 69 1000101 1.0500 6 0000110 0.5500 70 1000110 1.1000 7 0000111 0.5750 71 1000111 1.1500 8 0001000 0.6000 72 1001000 1.2000 9 0001001 0.6250 73 1001001 1.2500 10 0001010 0.6500 74 1001010 1.3000 11 0001011 0.6750 75 1001011 1.3500 12 0001100 0.7000 76 1001100 1.4000 13 0001101 0.7250 77 1001101 1.4500 14 0001110 0.7500 78 1001110 1.5000 15 0001111 0.7750 79 1001111 1.5500 16 0010000 0.8000 80 1010000 1.6000 17 0010001 0.8250 81 1010001 1.6500 18 0010010 0.8500 82 1010010 1.7000 19 0010011 0.8750 83 1010011 1.7500 20 0010100 0.9000 84 1010100 1.8000 21 0010101 0.9250 85 1010101 1.8500 22 0010110 0.9500 86 1010110 1.9000 23 0010111 0.9750 87 1010111 1.9500 24 0011000 1.0000 88 1011000 2.0000 25 0011001 1.0250 89 1011001 2.0500 26 0011010 1.0500 90 1011010 2.1000 27 0011011 1.0750 91 1011011 2.1500 28 0011100 1.1000 92 1011100 2.2000 29 0011101 1.1250 93 1011101 2.2500 30 0011110 1.1500 94 1011110 2.3000 31 0011111 1.1750 95 1011111 2.3500 32 0100000 1.2000 96 1100000 2.4000 33 0100001 1.2250 97 1100001 2.4500 34 0100010 1.2500 98 1100010 2.5000 35 0100011 1.2750 99 1100011 2.5500 PF0200 NXP Semiconductors 51 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 58. SW3A/B output voltage configuration (continued) Low output voltage range(47) High output voltage range Set point SW3x[6:0] SW3xSTBY[6:0] SW3xOFF[6:0] SW3x output Set Point SW3x[6:0] SW3xSTBY[6:0] SW3xOFF[6:0] sw3xoutput 36 0100100 1.3000 100 1100100 2.6000 37 0100101 1.3250 101 1100101 2.6500 38 0100110 1.3500 102 1100110 2.7000 39 0100111 1.3750 103 1100111 2.7500 40 0101000 1.4000 104 1101000 2.8000 41 0101001 1.4250 105 1101001 2.8500 42 0101010 1.4500 106 1101010 2.9000 43 0101011 1.4750 107 1101011 2.9500 44 0101100 1.5000 108 1101100 3.0000 45 0101101 1.5250 109 1101101 3.0500 46 0101110 1.5500 110 1101110 3.1000 47 0101111 1.5750 111 1101111 3.1500 48 0110000 1.6000 112 1110000 3.2000 49 0110001 1.6250 113 1110001 3.2500 50 0110010 1.6500 114 1110010 3.3000 51 0110011 1.6750 115 1110011 Reserved 52 0110100 1.7000 116 1110100 Reserved 53 0110101 1.7250 117 1110101 Reserved 54 0110110 1.7500 118 1110110 Reserved 55 0110111 1.7750 119 1110111 Reserved 56 0111000 1.8000 120 1111000 Reserved 57 0111001 1.8250 121 1111001 Reserved 58 0111010 1.8500 122 1111010 Reserved 59 0111011 1.8750 123 1111011 Reserved 60 0111100 1.9000 124 1111100 Reserved 61 0111101 1.9250 125 1111101 Reserved 62 0111110 1.9500 126 1111110 Reserved 63 0111111 1.9750 127 1111111 Reserved Notes 47. For voltages less than 2.0 V, only use set points 0 to 63. PF0200 52 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 59 provides a list of registers used to configure and operate SW3A/B. A detailed description on each of these register is provided on Tables 60 through Table 69. Table 59. SW3AB register summary Register Address Output SW3AVOLT 0x3C SW3A Output voltage set point on normal operation SW3ASTBY 0x3D SW3A Output voltage set point on Standby SW3AOFF 0x3E SW3A Output voltage set point on Sleep SW3AMODE 0x3F SW3A Switching mode selector register SW3ACONF 0x40 SW3A DVS, phase, frequency and ILIM configuration SW3BVOLT 0x43 SW3B Output voltage set point on normal operation SW3BSTBY 0x44 SW3B Output voltage set point on Standby SW3BOFF 0x45 SW3B Output voltage set point on Sleep SW3BMODE 0x46 SW3B Switching mode selector register SW3BCONF 0x47 SW3B DVS, phase, frequency and ILIM configuration Table 60. Register SW3AVOLT - ADDR 0x3C Name SW3A Bit # 5:0 R/W R/W Default Description 0x00 Sets the SW3A output voltage (Independent) or SW3A/B output voltage (Single phase), during normal operation mode. See Table 58 for all possible configurations. SW3A 6 R 0x00 Sets the operating output voltage range for SW3A (Independent) or SW3A/B (Single phase). Set during OTP or TBB configuration only. See Table 58 for all possible configurations. UNUSED 7 – 0x00 UNUSED Table 61. Register SW3ASTBY - ADDR 0x3D Name SW3ASTBY Bit # 5:0 R/W R/W Default Description 0x00 Sets the SW3A output voltage (Independent) or SW3A/B output voltage (Single phase), during Standby mode. See Table 58 for all possible configurations. SW3ASTBY 6 R 0x00 Sets the operating output voltage range for SW3A (Independent) or SW3A/B (Single phase) on Standby mode. This bit inherits the value configured on bit SW3A[6] during OTP or TBB configuration. See Table 58 for all possible configurations. UNUSED 7 – 0x00 UNUSED PF0200 NXP Semiconductors 53 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 62. Register SW3AOFF - ADDR 0x3E Name SW3AOFF Bit # 5:0 R/W R/W Default Description 0x00 Sets the SW3A output voltage (Independent) or SW3A/B output voltage (Single phase), during Sleep mode. See Table 58 for all possible configurations. SW3AOFF 6 R 0x00 Sets the operating output voltage range for SW3A (Independent) or SW3A/B (Single phase) on Sleep mode. This bit inherits the value configured on bit SW3A[6] during OTP or TBB configuration. See Table 58 for all possible configurations. UNUSED 7 – 0x00 UNUSED Table 63. Register SW3AMODE - ADDR 0x3F Name SW3AMODE UNUSED SW3AOMODE UNUSED Bit # R/W Default Description 3:0 R/W 0x80 Sets the SW3A (Independent) or SW3A/B (Single phase) switching operation mode. See Table 28 for all possible configurations. 4 – 0x00 UNUSED 5 R/W 0x00 Set status of SW3A (Independent) or SW3A/B (Single phase) when in Sleep mode. 0 = OFF 1 = PFM 7:6 – 0x00 UNUSED Table 64. Register SW3ACONF - ADDR 0x40 Name Bit # R/W Default Description SW3AILIM 0 R/W 0x00 SW3A current limit level selection 0 = High level current limit 1 = Low level current limit UNUSED 1 R/W 0x00 Unused SW3AFREQ 3:2 R/W 0x00 SW3A switching frequency selector. See Table 36. SW3APHASE 5:4 R/W 0x00 SW3A Phase clock selection. See Table 34. SW3ADVSSPEED 7:6 R/W 0x00 SW3A DVS speed selection. See Table 33. Table 65. Register SW3BVOLT - ADDR 0x43 Name SW3B Bit # R/W Default Description 5:0 R/W 0x00 Sets the SW3B output voltage (Independent) during normal operation mode. See Table 58 for all possible configurations. SW3B 6 R 0x00 Sets the operating output voltage range for SW3B (Independent). Set during OTP or TBB configuration only. See Table 58 for all possible configurations. UNUSED 7 – 0x00 UNUSED PF0200 54 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 66. Register SW3BSTBY - ADDR 0x44 Name SW3BSTBY Bit # R/W Default Description 5:0 R/W 0x00 Sets the SW3B output voltage (Independent) during Standby mode. See Table 58 for all possible configurations. SW3BSTBY 6 R 0x00 Sets the operating output voltage range for SW3B (Independent) on Standby mode. This bit inherits the value configured on bit SW3B[6] during OTP or TBB configuration. See Table 58 for all possible configurations. UNUSED 7 – 0x00 UNUSED Table 67. Register SW3BOFF - ADDR 0x45 Name SW3BOFF Bit # R/W Default Description 5:0 R/W 0x00 Sets the SW3B output voltage (Independent) during Sleep mode. See Table 58 for all possible configurations. SW3BOFF 6 R 0x00 Sets the operating output voltage range for SW3B (Independent) on Sleep mode. This bit inherits the value configured on bit SW3B[6] during OTP or TBB configuration. See Table 58 for all possible configurations. UNUSED 7 – 0x00 UNUSED Table 68. Register SW3BMODE - ADDR 0x46 Name SW3BMODE UNUSED SW3BOMODE UNUSED Bit # R/W Default Description 3:0 R/W 0x80 Sets the SW3B (Independent) switching operation mode. See Table 28 for all possible configurations. 4 – 0x00 UNUSED 5 R/W 0x00 Set status of SW3B (Independent) when in Sleep mode. 0 = OFF 1 = PFM 7:6 – 0x00 UNUSED Table 69. Register SW3BCONF - ADDR 0x47 Name Bit # R/W Default Description SW3BILIM 0 R/W 0x00 SW3B current limit level selection 0 = High level Current limit 1 = Low level Current limit UNUSED 1 R/W 0x00 Unused SW3BFREQ 3:2 R/W 0x00 SW3B switching frequency selector. See Table 36. SW3BPHASE 5:4 R/W 0x00 SW3B Phase clock selection. See Table 34. SW3BDVSSPEED 7:6 R/W 0x00 SW3B DVS speed selection. See Table 33. PF0200 NXP Semiconductors 55 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS SW3A/B external components Table 70. SW3A/B external component requirements Mode Components CINSW3A(48) Description SW3A/B single phase SW3A independent SW3B independent SW3A Input capacitor 4.7 μF 4.7 μF (48) SW3A Decoupling input capacitor 0.1 μF 0.1 μF (48) SW3B Input capacitor 4.7 μF 4.7 μF (48) SW3B Decoupling input capacitor 0.1 μF 0.1 μF COSW3A (48) SW3A Output capacitor 4 x 22 μF 2 x 22 μF COSW3B (48) SW3B Output capacitor – 2 x 22 μF CIN3AHF CINSW3B CIN3BHF LSW3A SW3A Inductor 1.0 μH DCR = 50 mΩ ISAT = 3.9 A 1.0 μH DCR = 60 mΩ ISAT = 3.0 A LSW3B SW3B Inductor – 1.0 μH DCR = 60 mΩ ISAT = 3.0 A Notes 48. Use X5R or X7R capacitors. SW3A/B specifications Table 71. SW3A/B electrical characteristics All parameters are specified at Consumer TA = -40 to 85 °C and Extended Industrial TA = -40 to 105 °C, VIN = VINSW3x = 3.6 V, VSW3x = 1.5 V, ISW3x = 100 mA, SW3x_PWRSTG[2:0] = [111], typical external component values, fSW3x = 2.0 MHz, single phase and independent mode unless, otherwise noted. Typical values are characterized at VIN = VINSW3x = 3.6 V, VSW3x = 1.5 V, ISW3x = 100 mA, SW3x_PWRSTG[2:0] = [111], and 25 °C, unless otherwise noted. Parameter Symbol Min. Typ. Max. Unit 2.8 – 4.5 V - Table 58 - V -25 -3.0% -6.0% – – – 25 3.0% 6.0% -65 -45 -3.0% -3.0% – – – – 65 45 3.0% 3.0% – – – – 2500 1250 Notes Switch mode supply SW3a/B VINSW3x VSW3x VSW3xACC ISW3x Operating Input Voltage(49) Nominal Output Voltage Output Voltage Accuracy • PWM, APS 2.8 V < VIN < 4.5 V, 0 < ISW3x < ISW3xMAX 0.625 V < VSW3x < 0.85 V 0.875 V < VSW3x < 1.975 V 2.0 V < VSW3x < 3.3 V • PFM , steady state (2.8 V < VIN < 4.5 V, 0 < ISW3x < 50 mA) 0.625 V < VSW3x < 0.675 V 0.7 V < VSW3x < 0.85 V 0.875 V < VSW3x < 1.975 V 2.0 V < VSW3x < 3.3 V Rated Output Load Current (51) • 2.8 V < VIN < 4.5 V, 0.625 V < VSW3x < 3.3 V PWM, APS mode single phase PWM, APS mode independent (per phase) mV % (50) mA PF0200 56 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 71. SW3A/B electrical characteristics (continued) All parameters are specified at Consumer TA = -40 to 85 °C and Extended Industrial TA = -40 to 105 °C, VIN = VINSW3x = 3.6 V, VSW3x = 1.5 V, ISW3x = 100 mA, SW3x_PWRSTG[2:0] = [111], typical external component values, fSW3x = 2.0 MHz, single phase and independent mode unless, otherwise noted. Typical values are characterized at VIN = VINSW3x = 3.6 V, VSW3x = 1.5 V, ISW3x = 100 mA, SW3x_PWRSTG[2:0] = [111], and 25 °C, unless otherwise noted. Parameter Symbol Min. Typ. Max. 3.5 2.7 5.0 3.8 6.5 4.9 Unit Notes Switch mode supply SW3a/B (continued) ISW3xLIM Current Limiter Peak Current Detection • Single phase (Current through inductor) SW3xILIM = 0 SW3xILIM = 1 • Independent mode (Current through inductor per phase) SW3xILIM = 0 SW3xILIM = 1 A 1.8 1.3 2.5 1.9 3.3 2.5 VSW3xOSH Start-up Overshoot ISW3x = 0.0 mA DVS clk = 25 mV/4 μs, VIN = VINSW3x = 4.5 V – – 66 mV tONSW3x Turn-on Time Enable to 90% of end value ISW3x = 0 mA DVS clk = 25 mV/4 μs, VIN = VINSW3x = 4.5 V – – 500 µs Switching Frequency SW3xFREQ[1:0] = 00 SW3xFREQ[1:0] = 01 SW3xFREQ[1:0] = 10 – – – 1.0 2.0 4.0 – – – ηSW3AB Efficiency (Single Phase) • fSW3 = 2.0 MHz, LSW3x 1.0 μH PFM, 1.5 V, 1.0 mA PFM, 1.5 V, 50 mA APS, PWM 1.5 V, 500 mA APS, PWM 1.5 V, 750 mA APS, PWM 1.5 V, 1250 mA APS, PWM 1.5 V, 2500 mA – – – – – – 84 85 85 84 80 74 – – – – – – ΔVSW3x Output Ripple – 10 – mV VSW3xLIR Line Regulation (APS, PWM) – – 20 mV VSW3xLOR DC Load Regulation (APS, PWM) – – 20 mV VSW3xLOTR Transient Load Regulation • Transient Load = 0.0 mA to ISW3x/2, di/dt = 100 mA/μs Overshoot Undershoot – – – – 50 50 Quiescent Current PFM Mode (Single Phase) APS Mode (Single Phase) PFM Mode (Independent mode) APS Mode (SW3A Independent mode) APS Mode (SW3B Independent mode) – – – – – 22 300 50 250 150 – – – – – 215 245 mΩ 258 326 mΩ – 7.5 µA fSW3x ISW3xQ RONSW3AP SW3A P-MOSFET RDSON at VIN = VINSW3A = 3.3 V – RONSW3AN SW3A N-MOSFET RDSON at VIN = VINSW3A = 3.3 V – SW3A P-MOSFET Leakage Current VIN = VINSW3A = 4.5 V – ISW3APQ MHz % mV µA PF0200 NXP Semiconductors 57 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 71. SW3A/B electrical characteristics (continued) All parameters are specified at Consumer TA = -40 to 85 °C and Extended Industrial TA = -40 to 105 °C, VIN = VINSW3x = 3.6 V, VSW3x = 1.5 V, ISW3x = 100 mA, SW3x_PWRSTG[2:0] = [111], typical external component values, fSW3x = 2.0 MHz, single phase and independent mode unless, otherwise noted. Typical values are characterized at VIN = VINSW3x = 3.6 V, VSW3x = 1.5 V, ISW3x = 100 mA, SW3x_PWRSTG[2:0] = [111], and 25 °C, unless otherwise noted. Parameter Symbol Min. Typ. Max. Unit SW3A N-MOSFET Leakage Current VIN = VINSW3A = 4.5 V – – 2.5 µA RONSW3BP SW3B P-MOSFET RDS(on) at VIN = VINSW3B = 3.3 V – 215 245 mΩ RONSW3BN SW3B N-MOSFET RDS(on) at VIN = VINSW3B = 3.3 V – 258 326 mΩ ISW3BPQ SW3B P-MOSFET Leakage Current VIN = VINSW3B = 4.5 V – – 7.5 µA ISW3BPQ SW3B N-MOSFET Leakage Current VIN = VINSW3B = 4.5 V – – 2.5 µA RSW3xDIS Discharge Resistance – 600 – Ω Notes Switch mode supply SW3a/B (continued) ISW3ANQ Notes 49. When output is set to > 2.6 V the output will follow the input down when VIN gets near 2.8 V. 50. 51. Accuracy specification is inclusive of load and line regulation. The higher output voltages available depend on the voltage drop in the conduction path as given by the following equation: (VINSW3x - VSW3x) = ISW3x* (DCR of Inductor +RONSW3xP + PCB trace resistance). 100 90 80 PFM - Vout = 1.5V 20 APS - Vout = 1.5V Efficiency (%) 70 ) (% 60 yc n 50 ie ci ff 40 E 30 10 PWM - Vout = 1.5V 0 0.1 1 10 100 1000 Load Current (mA) Figure 17. SW3AB single phase efficiency waveforms 6.4.5 Boost regulator SWBST is a boost regulator with a programmable output from 5.0 to 5.15 V. SWBST can supply the VUSB regulator for the USB PHY in OTG mode, as well as the VBUS voltage. Note that the parasitic leakage path for a boost regulator will cause the SWBSTOUT and SWBSTFB voltage to be a Schottky drop below the input voltage whenever SWBST is disabled. The switching NMOS transistor is integrated on-chip. Figure 18 shows the block diagram and component connection for the boost regulator. PF0200 58 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS VIN CINBST LBST VOBST SWBSTIN DBST SWBSTMODE SWBSTLX Driver OC RSENSE EP VREFSC Controller SWBSTFAULT I2C Interface SC VREFUV UV SWBSTFB Internal Compensation Z2 COSWBST Z1 EA VREF Figure 18. Boost regulator architecture 6.4.5.1 SWBST setup and control Boost regulator control is done through a single register SWBSTCTL described in Table 72. SWBST is included in the power-up sequence if its OTP power-up timing bits, SWBST_SEQ[4:0], are not all zeros. Table 72. Register SWBSTCTL - ADDR 0x66 Name SWBST1VOLT SWBST1MODE UNUSED SWBST1STBYMODE UNUSED Bit # 1:0 R/W R/W Default Description 0x00 Set the output voltage for SWBST 00 = 5.000 V 01 = 5.050 V 10 = 5.100 V 11 = 5.150 V 3:2 R 0x02 Set the Switching mode on Normal operation 00 = OFF 01 = PFM 10 = Auto (Default)(52) 11 = APS 4 – 0x00 UNUSED 6:5 R/W 0x02 Set the Switching mode on Standby 00 = OFF 01 = PFM 10 = Auto (Default)(52) 11 = APS 7 – 0x00 UNUSED Notes 52. In Auto mode, the controller automatically switches between PFM and APS modes depending on the load current. The SWBST regulator starts up by default in the Auto mode, if SWBST is part of the startup sequence. PF0200 NXP Semiconductors 59 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS 6.4.5.2 SWBST external components Table 73. SWBST external component requirements Components CINBST(53) CINBSTHF COBST (53) (53) Description Values SWBST input capacitor 10 μF SWBST decoupling input capacitor 0.1 μF 2 x 22 μF SWBST output capacitor LSBST SWBST inductor DBST SWBST boost diode 2.2 μH 1.0 A, 20 V Schottky Notes 53. Use X5R or X7R capacitors. 6.4.5.3 SWBST specifications Table 74. SWBST electrical specifications All parameters are specified at Consumer TA = -40 to 85 °C and Extended Industrial TA = -40 to 105 °C, VIN = VINSWBST = 3.6 V, VSWBST = 5.0 V, ISWBST = 100 mA, typical external component values, fSWBST = 2.0 MHz, otherwise noted. Typical values are characterized at VIN = VINSWBST = 3.6 V, VSWBST = 5.0 V, ISWBST = 100 mA, and 25 °C, unless otherwise noted. Symbol Parameters Min. Typ. Max. Units 2.8 – 4.5 V – Table 72 – V -4.0 – 3.0 % Output Ripple 2.8 V ≤ VIN ≤ 4.5 V 0 < ISWBST < ISWBSTMAX, excluding reverse recovery of Schottky diode – – 120 mV Vp-p VSWBSTLOR DC Load Regulation 0 < ISWBST < ISWBSTMAX – 0.5 – mV/mA VSWBSTLIR DC Line Regulation 2.8 V ≤ VIN ≤ 4.5 V, ISWBST = ISWBSTMAX – 50 – mV – – – – 500 600 mA Quiescent Current AUTO – 222 289 μA RDSONBST MOSFET on Resistance – 206 306 mΩ ISWBSTLIM Peak Current Limit 1400 2200 3200 mA Start-up Overshoot ISWBST = 0.0 mA – – 500 mV VSWBSTTR Transient Load Response ISWBST from 1.0 to 100 mA in 1.0 µs Maximum transient Amplitude – – 300 mV VSWBSTTR Transient Load Response ISWBST from 100 to 1.0 mA in 1.0 µs Maximum transient Amplitude – – 300 mV Notes Switch mode supply SWBST VINSWBST VSWBST VSWBSTACC ΔVSWBST ISWBST ISWBSTQ VSWBSTOSH Input Voltage Range Nominal Output Voltage Output Voltage Accuracy 2.8 V ≤ VIN ≤ 4.5 V 0 < ISWBST < ISWBSTMAX Continuous Load Current 2.8 V ≤ VIN ≤ 3.0 V 3.0 V ≤ VIN ≤ 4.5 V (54) PF0200 60 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 74. SWBST electrical specifications (continued) All parameters are specified at Consumer TA = -40 to 85 °C and Extended Industrial TA = -40 to 105 °C, VIN = VINSWBST = 3.6 V, VSWBST = 5.0 V, ISWBST = 100 mA, typical external component values, fSWBST = 2.0 MHz, otherwise noted. Typical values are characterized at VIN = VINSWBST = 3.6 V, VSWBST = 5.0 V, ISWBST = 100 mA, and 25 °C, unless otherwise noted. Symbol Parameters Min. Typ. Max. Units Notes Switch mode supply SWBST (continued) tSWBSTTR Transient Load Response ISWBST from 1.0 to 100 mA in 1.0 µs Time to settle 80% of transient – – 500 µs tSWBSTTR Transient Load Response ISWBST from 100 to 1.0 mA in 1.0 µs Time to settle 80% of transient – – 20 ms ISWBSTHSQ NMOS Off Leakage SWBSTIN = 4.5 V, SWBSTMODE [1:0] = 00 – 1.0 5.0 µA tONSWBST Turn-on Time Enable to 90% of VSWBST, ISWBST = 0.0 mA – – 2.0 ms fSWBST Switching Frequency – 2.0 – MHz ηSWBST Efficiency ISWBST = ISWBSTMAX – 86 – % Notes 54. Only in Auto mode. 6.4.6 LDO regulators description This section describes the LDO regulators provided by the PF0200. All regulators use the main bandgap as reference. Refer to Bias and references block description section for further information on the internal reference voltages. A Low Power mode is automatically activated by reducing bias currents when the load current is less than I_Lmax/5. However, the lowest bias currents may be attained by forcing the part into its Low Power mode by setting the VGENxLPWR bit. The use of this bit is only recommended when the load is expected to be less than I_Lmax/50, otherwise performance may be degraded. When a regulator is disabled, the output will be discharged by an internal pull-down. The pull-down is also activated when RESETBMCU is low. VINx VINx VREF _ VGENxEN + VGENxLPWR VGENx VGENx I2C Interface CGENx VGENx Discharge Figure 19. General LDO block diagram PF0200 NXP Semiconductors 61 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS 6.4.6.1 Transient response waveforms Idealized stimulus and response waveforms for transient line and transient load tests are depicted in Figure 20. Note that the transient line and load response refers to the overshoot, or undershoot only, excluding the DC shift. IMAX ILOAD IMAX/10 1.0 us 1.0 us Transient Load Stimulus IL = IMAX/10 IL = IMAX Overshoot VOUT Undershoot VOUT Transient Load Response VINx_INITIAL VINx VINx_FINAL 10 us 10 us Transient Line Stimulus VINx_INITIAL VINx_FINAL Overshoot VOUT Undershoot VOUT Transient Line Response Figure 20. Transient waveforms PF0200 62 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS 6.4.6.2 Short-circuit protection All general purpose LDOs have short-circuit protection capability. The Short-circuit Protection (SCP) system includes debounced fault condition detection, regulator shutdown, and processor interrupt generation, to contain failures and minimize the chance of product damage. If a short-circuit condition is detected, the LDO will be disabled by resetting its VGENxEN bit, while at the same time, an interrupt VGENxFAULTI will be generated to flag the fault to the system processor. The VGENxFAULTI interrupt is maskable through the VGENxFAULTM mask bit. The SCP feature is enabled by setting the REGSCPEN bit. If this bit is not set, the regulators will not automatically be disabled upon a short-circuit detection. However, the current limiter will continue to limit the output current of the regulator. By default, the REGSCPEN is not set; therefore, at start-up none of the regulators will be disabled if an overloaded condition occurs. A fault interrupt, VGENxFAULTI, will be generated in an overload condition regardless of the state of the REGSCPEN bit. See Table 75 for SCP behavior configuration. Table 75. Short-circuit behavior 6.4.6.3 REGSCPEN[0] Short-circuit behavior 0 Current limit 1 Shutdown LDO regulator control Each LDO is fully controlled through its respective VGENxCTL register. This register enables the user to set the LDO output voltage according to Table 76 for VGEN1 and VGEN2; and uses the voltage set point on Table 77 for VGEN3 through VGEN6. Table 76. VGEN1, VGEN2 output voltage configuration Set point VGENx[3:0] VGENx output (V) 0 0000 0.800 1 0001 0.850 2 0010 0.900 3 0011 0.950 4 0100 1.000 5 0101 1.050 6 0110 1.100 7 0111 1.150 8 1000 1.200 9 1001 1.250 10 1010 1.300 11 1011 1.350 12 1100 1.400 13 1101 1.450 14 1110 1.500 15 1111 1.550 PF0200 NXP Semiconductors 63 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 77. VGEN3/ 4/ 5/ 6 output voltage configuration Set point VGENx[3:0] VGENx output (V) 0 0000 1.80 1 0001 1.90 2 0010 2.00 3 0011 2.10 4 0100 2.20 5 0101 2.30 6 0110 2.40 7 0111 2.50 8 1000 2.60 9 1001 2.70 10 1010 2.80 11 1011 2.90 12 1100 3.00 13 1101 3.10 14 1110 3.20 15 1111 3.30 Besides the output voltage configuration, the LDOs can be enabled or disabled at anytime during normal mode operation, as well as programmed to stay “ON” or be disabled when the PMIC enters Standby mode. Each regulator has associated I2C bits for this. Table 78 presents a summary of all valid combinations of the control bits on VGENxCTL register and the expected behavior of the LDO output. Table 78. LDO control VGENxEN VGENxLPWR VGENxSTBY STANDBY(55) VGENxOUT 0 X X X Off 1 0 0 X On 1 1 0 X Low Power 1 X 1 0 On 1 0 1 1 Off 1 1 1 1 Low Power Notes 55. STANDBY refers to a Standby event as described earlier. For more detail information, Table 79 through Table 84 provide a description of all registers necessary to operate all six general purpose LDO regulators. PF0200 64 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 79. Register VGEN1CTL - ADDR 0x6C Name Bit # R/W Default 3:0 R/W 0x80 Sets VGEN1 output voltage. See Table 76 for all possible configurations. VGEN1EN 4 – 0x00 Enables or Disables VGEN1 output 0 = OFF 1 = ON VGEN1STBY 5 R/W 0x00 Set VGEN1 output state when in Standby. Refer to Table 78. VGEN1LPWR 6 R/W 0x00 Enable Low Power mode for VGEN1. Refer to Table 78. UNUSED 7 – 0x00 UNUSED VGEN1 Description Table 80. Register VGEN2CTL - ADDR 0x6D Name Bit # R/W Default 3:0 R/W 0x80 Sets VGEN2 output voltage. See Table 76 for all possible configurations. VGEN2EN 4 – 0x00 Enables or Disables VGEN2 output 0 = OFF 1 = ON VGEN2STBY 5 R/W 0x00 Set VGEN2 output state when in Standby. Refer to Table 78. VGEN2LPWR 6 R/W 0x00 Enable Low Power Mode for VGEN2. Refer to Table 78. UNUSED 7 – 0x00 UNUSED VGEN2 Description Table 81. Register VGEN3CTL - ADDR 0x6E Name Bit # R/W Default 3:0 R/W 0x80 Sets VGEN3 output voltage. See Table 77 for all possible configurations. VGEN3EN 4 – 0x00 Enables or Disables VGEN3 output 0 = OFF 1 = ON VGEN3STBY 5 R/W 0x00 Set VGEN3 output state when in Standby. Refer to Table 78. VGEN3LPWR 6 R/W 0x00 Enable Low Power mode for VGEN3. Refer to Table 78. UNUSED 7 – 0x00 UNUSED VGEN3 Description PF0200 NXP Semiconductors 65 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 82. Register VGEN4CTL - ADDR 0x6F Name Bit # R/W Default 3:0 R/W 0x80 Sets VGEN4 output voltage. See Table 77 for all possible configurations. VGEN4EN 4 – 0x00 Enables or Disables VGEN4 output 0 = OFF 1 = ON VGEN4STBY 5 R/W 0x00 Set VGEN4 output state when in Standby. Refer to Table 78. VGEN4LPWR 6 R/W 0x00 Enable Low Power mode for VGEN4. Refer to Table 78. UNUSED 7 – 0x00 UNUSED VGEN4 Description Table 83. Register VGEN5CTL - ADDR 0x70 Name Bit # R/W Default 3:0 R/W 0x80 Sets VGEN5 output voltage. See Table 77 for all possible configurations. VGEN5EN 4 – 0x00 Enables or Disables VGEN5 output 0 = OFF 1 = ON VGEN5STBY 5 R/W 0x00 Set VGEN5 output state when in Standby. Refer to Table 78. VGEN5LPWR 6 R/W 0x00 Enable Low Power mode for VGEN5. Refer to Table 78. UNUSED 7 – 0x00 UNUSED VGEN5 Description Table 84. Register VGEN6CTL - ADDR 0x71 Name Bit # R/W Default 3:0 R/W 0x80 Sets VGEN6 output voltage. See Table 77 for all possible configurations. VGEN6EN 4 – 0x00 Enables or Disables VGEN6 output 0 = OFF 1 = ON VGEN6STBY 5 R/W 0x00 Set VGEN6 output state when in Standby. Refer to Table 78. VGEN6LPWR 6 R/W 0x00 Enable Low Power mode for VGEN6. Refer to Table 78. UNUSED 7 – 0x00 UNUSED VGEN6 Description PF0200 66 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS 6.4.6.4 External components Table 85 lists the typical component values for the general purpose LDO regulators. Table 85. LDO external components Regulator Output capacitor (μF)(56) VGEN1 2.2 VGEN2 4.7 VGEN3 2.2 VGEN4 4.7 VGEN5 2.2 VGEN6 2.2 Notes 56. 6.4.6.5 Use X5R/X7R ceramic capacitors. LDO specifications VGEN1 Table 86. VGEN1 electrical characteristics All parameters are specified at Consumer TA = -40 to 85 °C and Extended Industrial TA = -40 to 105 °C, VIN = 3.6 V, VIN1 = 3.0 V, VGEN1[3:0] = 1111, IGEN1 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, IN1 = 3.0 V, VGEN1[3:0] = 1111, IGEN1 = 10 mA, and 25 °C, unless otherwise noted. Symbol Parameter Min. Typ. Max. Unit Notes VGEN1 VIN1 Operating Input Voltage 1.75 – 3.40 V VGEN1NOM Nominal Output Voltage – Table 76 – V IGEN1 Operating Load Current 0.0 – 100 mA VGEN1TOL Output Voltage Tolerance 1.75 V < VIN1 < 3.4 V 0.0 mA < IGEN1 < 100 mA VGEN1[3:0] = 0000 to 1111 -3.0 – 3.0 % VGEN1LOR Load Regulation (VGEN1 at IGEN1 = 100 mA) - (VGEN1 at IGEN1 = 0.0 mA) For any 1.75 V < VIN1 < 3.4 V – 0.15 – mV/mA VGEN1LIR Line Regulation (VGEN1 at VIN1 = 3.4 V) - (VGEN1 at VIN1 = 1.75 V) For any 0.0 mA < IGEN1 < 100 mA – 0.30 – mV/mA IGEN1LIM Current Limit IGEN1 when VGEN1 is forced to VGEN1NOM/2 122 167 200 mA IGEN1OCP Overcurrent Protection Threshold IGEN1 required to cause the SCP function to disable LDO when REGSCPEN = 1 115 – 200 mA – 14 – μA VGEN1 DC IGEN1Q Quiescent Current No load, Change in IVIN and IVIN1 When VGEN1 enabled PF0200 NXP Semiconductors 67 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 86. VGEN1 electrical characteristics (continued) All parameters are specified at Consumer TA = -40 to 85 °C and Extended Industrial TA = -40 to 105 °C, VIN = 3.6 V, VIN1 = 3.0 V, VGEN1[3:0] = 1111, IGEN1 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, IN1 = 3.0 V, VGEN1[3:0] = 1111, IGEN1 = 10 mA, and 25 °C, unless otherwise noted. Symbol Parameter Min. Typ. Max. PSRRVGEN1 PSRR • IGEN1 = 75 mA, 20 Hz to 20 kHz VGEN1[3:0] = 0000 - 1101 VGEN1[3:0] = 1110, 1111 50 37 60 45 – – NOISEVGEN1 Output Noise Density VIN1 = 1.75 V, IGEN1 = 75 mA 100 Hz –