N74F299N,602

INTEGRATED CIRCUITS 74F299 8-bit universal shift/storage register (3-State) Product data Supersedes data of 1990 Mar 01 
   2003 Feb 05 Philips Semiconductors Product data 8-bit universal shift/storage register (3-State) FEATURES 74F299 PIN CONFIGURATION • Common parallel I/O for reduced pin count • Additional serial inputs and outputs for expansion • Four operating modes: Shift left, shift right, load and store • 3-State outputs for bus-oriented applications S0 1 20 VCC OE0 2 19 S1 OE1 3 18 DS7 I/O6 4 17 Q7 I/O4 5 16 I/O7 I/O2 6 15 I/O5 I/O0 7 14 I/O3 Q0 8 13 I/O1 MR 9 12 CP DESCRIPTION The 74F299 is an 8-bit universal shift/storage register with 3-State outputs. Four modes of operation are possible: Hold (store), shift left, shift right and parallel load. The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins. Additional outputs are provided for flip-flops Q0 and Q7 to allow easy serial cascading. A separate active-LOW Master Reset is used to reset the register. GND 10 11 DS0 SF00865 The 74F299 contains eight edge-triggered D-type flip-flops and the interstage logic necessary to perform synchronous shift left, shift right, parallel load and hold operations. The type of operation is determined by S0 and S1, as shown in the Function Table. All flip-flop outputs are brought out through 3-State buffers to separate I/O pins that also serve as data inputs in the parallel load mode. Q0 and Q7 are also brought out on other pins for expansion in serial shifting of longer words. TYPE TYPICAL fMAX TYPICAL SUPPLY CURRENT (TOTAL) 74F299 115 MHz 58 mA ORDERING INFORMATION A LOW signal on MR overrides the Select and CP inputs and resets the flip-flops. All other state changes are initiated by the rising edge of the clock. Inputs can change when the clock is in either state provided only that the recommended set-up and hold times, relative to the rising edge of clock are observed. ORDER CODE DESCRIPTION A HIGH signal on either OE0 or OE1 disables the 3-State buffers and puts the I/O pins in the high impedance state. In this condition the shift, hold, load and reset operations can still occur. The 3-State buffers are also disabled by High signals on both S0 and S1 in preparation for a parallel load operation. COMMERCIAL RANGE VCC = 5 V ±10%, Tamb = 0 °C to +70 °C PKG DWG # 20-pin plastic DIP N74F299N SOT146-1 20-pin plastic SOL N74F299D SOT163-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 74F(U.L.) HIGH / LOW LOAD VALUE HIGH / LOW DS0 Serial data input for right shift 1.0 / 1.0 20 µA / 0.6 mA DS7 Serial data input for left shift 1.0 / 1.0 20 µA / 0.6 mA S0, S1 Mode select inputs 1.0 / 2.0 20 µA / 1.2 mA CP Clock pulse input (Active rising edge) 1.0 / 1.0 20 µA / 0.6 mA MR Asynchronous Master Reset input (Active LOW) 1.0 / 1.0 20 µA / 0.6 mA OE0, OE1 Output Enable input (Active LOW) 1.0 / 1.0 20 µA / 0.6 mA Q0, Q7 Serial outputs 50 / 33 1.0 mA / 20 mA Multiplexed parallel data inputs 3.5 / 1.0 70 µA / 0.6 mA 3-State parallel outputs 150 / 40 NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20 µA in the HIGH State and 0.6 mA in the LOW state. 3.0 mA / 24 mA I/On 2003 Feb 05 2 Philips Semiconductors Product data 8-bit universal shift/storage register (3-State) LOGIC SYMBOL 74F299 LOGIC SYMBOL (IEEE/IEC) 11 SRG8 18 9 2 DS0 4R & 1 S0 1 0 19 S1 19 1 12 CP 12 9 MR 2 OE0 3 11 7 OE1 Q0 I/00 8 7 3EN13 3 DS7 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 Q7 16 17 13 M 0 3 C4/1→ /2← 8 1, 4D 3, 4D 5, 13 Z5 3, 4D 6, 13 Z6 6 VCC = Pin 20 GND = Pin 10 13 6 14 5 15 4 14 SF00866 5 15 4 16 3, 4D 18 12, 13 2, 4D Z12 17 SF00890 FUNCTION TABLE INPUTS OEn H L X ↑ = = = = INPUTS MR S1 S0 CP OPERATING MODE L L X X X Asynchronous Reset; Q0 – Q7 = LOW L H H H ↑ Parallel load; I/On → Qn (I/On outputs disabled) L H L H ↑ Shift right; DS0 → Q0, Q0 → Q1, etc. L H H L ↑ Shift left; DS7 → Q7, Q7 → Q6, etc. L H L L X Hold X X X Outputs in High-Z H X HIGH voltage level LOW voltage level Don’t care LOW-to-HIGH clock transition 2003 Feb 05 3 Philips Semiconductors Product data 8-bit universal shift/storage register (3-State) 74F299 LOGIC DIAGRAM DS7 18 OE0 2 3 D S0 Q7 16 I/O7 4 I/O6 15 I/O5 5 I/O4 14 I/O3 6 I/O2 13 I/O1 CP OE1 S1 17 Q 19 RD 1 CP D Q RD CP D Q RD CP D Q RD CP D Q RD CP D Q RD CP D Q RD CP D DS0 VCC = Pin 20 GND = Pin 10 2003 Feb 05 12 MR 9 7 I/O0 RD 11 CP Q 8 Q0 SF00868 4 Philips Semiconductors Product data 8-bit universal shift/storage register (3-State) 74F299 ABSOLUTE MAXIMUM RATINGS (Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL PARAMETER RATING UNIT V VCC Supply voltage –0.5 to +7.0 VIN Input voltage –0.5 to +7.0 V IIN Input current –30 to +5 mA VOUT Voltage applied to output in HIGH output state IOUT O Current applied to output in LOW output state Tamb Operating free-air temperature range Tstg Storage temperature –0.5 to +VCC V Q0, Q7 40 mA I/On 48 mA 0 to +70 °C –65 to +150 °C RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMITS UNIT MIN NOM MAX 5.0 5.5 VCC Supply voltage 4.5 VIH HIGH-level input voltage 2.0 VIL LOW-level input voltage 0.8 V IIK Input clamp current –18 mA IOH O HIGH level output current HIGH-level Q0, Q7 –1 mA I/On –3 mA IOL O LOW level output current LOW-level Q0, Q7 20 mA I/On 24 mA Tamb Operating free-air temperature range 70 °C 2003 Feb 05 0 5 V V Philips Semiconductors Product data 8-bit universal shift/storage register (3-State) 74F299 DC ELECTRICAL CHARACTERISTICS Over recommended operating free-air temperature range unless otherwise noted. SYMBOL Q0 Q7 Q0, VOH O HIGH level output voltage HIGH-level I/On VOL O LOW level output voltage LOW-level VIK Input clamp voltage II In ut current at maximum Input input voltage IIH HIGH-level input current IIL LOW level input current LOW-level IIH + IOZH Off-state output current, HIGH-level voltage applied IIL + IOZL Off-state output current LOW-level voltage applied IOS Short-circuit output current3 VCC = MIN, VIL = MAX MAX, VIH = MIN VCC = MIN, VIL = MAX, MAX VIH = MIN IOH 1 mA O = –1 3 mA IOH O = –3 IOL O = MAX ±10%VCC 2.5 ±5%VCC 2.7 ±10%VCC 2.4 ±5%VCC 2.7 ±10%VCC ±5%VCC TYP2 MAX UNIT V 3.4 V V 3.3 V 0.35 0.50 V 0.35 0.50 V –0.73 –1.2 V others VCC = MAX, VI = 7.0 V 100 µA I/On VCC = 5.5V, VI = 5.5 V 1 mA except I/On VCC = MAX, VI = 2.7 V 20 µA –1.2 mA –0.6 mA VCC = MAX, VO = 2.7 V 70 µA VCC = MAX, VO = 0.5 V –0.6 mA S0, S1 others Supply current (total) MIN VCC = MIN, II = IIK I/On only MAX VI = 0 5V VCC = MAX, 0.5 VCC = MAX ICCH ICC LIMITS TEST CONDITIONS1 PARAMETER ICCL VCC = MAX ICCZ –60 –150 mA 55 60 mA 70 90 mA 65 95 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5 V, Tamb = 25 °C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a HIGH output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 2003 Feb 05 6 Philips Semiconductors Product data 8-bit universal shift/storage register (3-State) 74F299 AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITIONS I/O Waveform 1 Tamb = +25 °C VCC = +5.0 V CL = 50 pF, RL = 500 Ω Tamb = 0 °C to +70 °C VCC = +5.0 V ± 10% CL = 50 pF, RL = 500 Ω MAX MIN UNIT MIN TYP 70 100 70 MAX MHz 85 115 85 MHz fMAX Maximum clock frequency tPLH tPHL Propagation delay CP to Q0 or Q7 Waveform 1 4.0 4.5 5.0 6.0 7.5 8.0 3.5 4.5 8.5 8.5 ns ns tPLH tPHL Propagation delay CP to I/On Waveform 1 4.0 4.0 6.0 6.5 9.0 9.0 4.0 4.0 10.0 10.0 ns ns tPHL Propagation delay MR to Q0 or Q7 Waveform 2 5.5 7.5 9.5 5.5 10.5 ns tPHL Propagation delay MR to I/On Waveform 2 5.5 7.5 10.0 5.5 10.5 ns tPZH tPZL Output Enable time Sn, OE to I/On Waveform 4 Waveform 5 3.5 4.0 6.0 7.5 8.0 10.0 3.5 4.0 9.0 11.0 ns ns tPHZ tPLZ Output Disable time Sn, OE to I/On Waveform 4 Waveform 5 2.5 1.5 4.5 2.5 7.0 5.5 2.5 1.5 8.0 6.5 ns ns Qn AC SET-UP REQUIREMENTS LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = +25 °C VCC = +5.0 V CL = 50 pF, RL = 500 Ω MIN TYP MAX Tamb = 0 °C to +70 °C VCC = +5.0 V ± 10% CL = 50 pF, RL = 500 Ω MIN UNIT MAX ts(H) ts(L) Set-up time, HIGH or LOW S0 or S1 to CP Waveform 3 6.5 6.5 7.5 7.5 ns ns th(H) th(L) Hold time, HIGH or LOW S0 or S1 to CP Waveform 3 0 0 0 0 ns ns ts(H) ts(L) Set-up time, HIGH or LOW I/On, DSL or DSR to CP Waveform 3 3.5 3.5 4.0 4.0 ns ns th(H) th(L) Hold time, HIGH or LOW I/On, DSL or DSR to CP Waveform 3 0 0 0 0 ns ns tw(H) tw(L) CP Pulse width, HIGH or LOW Waveform 1 5.0 4.5 5.0 4.5 ns tw(L) MR Pulse width, LOW Waveform 2 4.5 4.5 ns trec Recovery time, MR to CP Waveform 2 4.0 4.0 ns 2003 Feb 05 7 Philips Semiconductors Product data 8-bit universal shift/storage register (3-State) 74F299 AC WAVEFORMS For all waveforms, VM = 1.5 V The shaded areas indicate when the input is permitted to change for predictable output performance. 1/fMAX CP MR VM VM VM tW(H) VM tW(L) tREC CP tW(L) tPHL VM tPLH tPHL Q0, Q7, I/On VM VM Q0, Q7, I/On VM SF00869 SF00870 Waveform 2. Master Reset pulse width, Master Reset to output delay, and Master Reset to clock recovery time Waveform 1. Propagation delay, clock input to output, clock width, and maximum clock frequency S0, S1, I/On VM DSL, DSR ts(H) CP VM VM th(H) ts(L) VM VM Sn, OEn th(L) VM VM tPZH VM I/On tPHZ VOH -0.3V VM 0V SF00871 SF00872 Waveform 3. Set-up and hold times Sn, OEn VM VM tPZL I/On Waveform 4. 3-State Output Enable time to HIGH level and Output Disable time from HIGH level tPLZ VM VOL +0.3V SF00873 Waveform 5. 3-State Output Enable time to LOW level and Output Disable time from LOW level 2003 Feb 05 8 Philips Semiconductors Product data 8-bit universal shift/storage register (3-State) 74F299 TEST CIRCUIT AND WAVEFORM VCC 7.0V VIN RL VOUT PULSE GENERATOR tw 90% NEGATIVE PULSE VM CL AMP (V) VM 10% D.U.T. RT 90% 10% tTHL (tf ) tTLH (tr ) tTLH (tr ) tTHL (tf ) 0V RL AMP (V) 90% 90% Test Circuit for 3-State Outputs POSITIVE PULSE VM VM 10% TEST tPLZ tPZL All other SWITCH closed closed open DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators. 10% tw SWITCH POSITION 0V Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate tw tTLH tTHL 1MHz 500ns 2.5ns 2.5ns SF00777 2003 Feb 05 9 Philips Semiconductors Product data 8-bit universal shift/storage register (3-State) DIP20: plastic dual in-line package; 20 leads (300 mil) 2003 Feb 05 10 74F299 SOT146-1 Philips Semiconductors Product data 8-bit universal shift/storage register (3-State) SO20: plastic small outline package; 20 leads; body width 7.5 mm 2003 Feb 05 11 74F299 SOT163-1 Philips Semiconductors Product data 8-bit universal shift/storage register (3-State) 74F299 REVISION HISTORY Rev Date Description _3 20030205 Product data (9397 750 11037); ECN 853-0365 29307 of 17 December 2002. Supersedes Product specification (9397 750 05117) of 01 March 1990. Modifications: • Delete all references to DB package. Package option was discontinued. _2 19900301 Product specification (9397 750 05117); ECN 853-0365 29307 of 01 March 1990. Data sheet status Level Data sheet status [1] Product status [2] [3] Definitions I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.  Koninklijke Philips Electronics N.V. 2003 All rights reserved. Printed in U.S.A. Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 Date of release: 02-03 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. Document order number: 
   2003 Feb 05 12 9397 750 11037