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NTS0102GF,115

NTS0102GF,115

  • 厂商:

    NXP(恩智浦)

  • 封装:

    XSON8

  • 描述:

    TXRX TRANSLATING DUAL 8XSON

  • 数据手册
  • 价格&库存
NTS0102GF,115 数据手册
NTS0102 Dual supply translating transceiver; open-drain; auto direction sensing Rev. 4.4 — 6 October 2022 1 Product data sheet General description The NTS0102 is a 2-bit, dual supply translating transceiver with auto direction sensing, that enables bidirectional voltage level translation. It features two 2-bit input-output ports (An and Bn), one output enable input (OE) and two supply pins (VCC(A) and VCC(B)). VCC(A) can be supplied at any voltage between 1.65 V and 3.6 V and VCC(B) can be supplied at any voltage between 2.3 V and 5.5 V, making the device suitable for translating between any of the voltage nodes (1.8 V, 2.5 V, 3.3 V, and 5.0 V). Pins An and OE are referenced to VCC(A) and pins Bn are referenced to VCC(B). A LOW level at pin OE causes the outputs to assume a high-impedance OFF-state. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. 2 Features and benefits • Wide supply voltage range: – VCC(A): 1.65 V to 3.6 V and VCC(B): 2.3 V to 5.5 V • Maximum data rates: – Push-pull: 50 Mbit/s • IOFF circuitry provides partial Power-down mode operation • Inputs accept voltages up to 5.5 V • ESD protection: – HBM JESD22-A114E Class 2 exceeds 2500 V for A port – HBM JESD22-A114E Class 3B exceeds 8000 V for B port – CDM JESD22-C101E exceeds 1500 V • Latch-up performance exceeds 100 mA per JESD 78B Class II • Multiple package options • Specified from –40 °C to +85 °C and -40 °C to +125 °C 3 Applications 2 • I C/SMBus • UART • GPIO NTS0102 NXP Semiconductors Dual supply translating transceiver; open-drain; auto direction sensing 4 Ordering information Table 1. Ordering information Type number Topside marking Package Name Description Version NTS0102DP s02 TSSOP8 plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2 NTS0102GT s02 XSON8 plastic extremely thin small outline package; no leads; 8 terminals; body 1 × 1.95 × 0.5 mm SOT833-1 NTS0102GD s02 XSON8 plastic extremely thin small outline package; no leads; 8 terminals; body 3 × 2 × 0.5 mm SOT996-2 NTS0102GF s2 XSON8 extremely thin small outline package; no leads; 8 terminals; body 1.35 × 1 × 0.5 mm SOT1089 NTS0102TL tS2 XSON8 plastic extremely thin small outline package; no leads; 8 terminals; body 3 x 2 x 0.5 mm SOT1052-2 4.1 Ordering options Table 2. Ordering options Type number Orderable part number Package Packing [1] method Minimum order quantity Temperature NTS0102DP NTS0102DP,125 TSSOP8 Reel 7" Q3 NDP 3000 –40 °C to +125 °C NTS0102GT NTS0102GT,115 XSON8 Reel 7" Q1 NDP 5000 –40 °C to +125 °C NTS0102GD NTS0102GD,125 XSON8 Reel 7" Q3 NDP 3000 –40 °C to +125 °C NTS0102GF NTS0102GF,115 XSON8 Reel 7" Q1 NDP 5000 –40 °C to +125 °C NTS0102TL NTS0102TLH XSON8 Reel 7" Q3 NDP 4000 –40 °C to +125 °C [2] [1] [2] Standard packing quantities and other packaging data are available at www.nxp.com/packages/. Discontinuation Notice 202111012DN - drop in replacement is NTS0102TLH. The TL package has a center pad vs no center pad for the GD package. The TL package pad is not electrically connected to the silicon and is not required to connect to the PCB so it can drop onto the GD package PCB layout. If the existing GD package has a trace underneath the risk is low since the TL package center pad is not connected to the silicon. If there are multiple traces there could be EMI and cross talk. In both cases the customer needs to evaluate risk. Note: The length and width are reversed between the "GD" and "TL" package drawings but the shorter edge contains the pins and is 2.0 mm in both cases. NTS0102 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4.4 — 6 October 2022 © 2022 NXP B.V. All rights reserved. 2 / 38 NTS0102 NXP Semiconductors Dual supply translating transceiver; open-drain; auto direction sensing 5 Functional diagram OE A2 GATE BIAS 6 4 1 A1 B2 5 8 VCC(A) GATE BIAS B1 VCC(B) 001aal905 Figure 1. Logic symbol 6 Pinning information 6.1 Pinning NTS0102 NTS0102 B2 1 8 B1 GND 2 7 VCC(B) VCC(A) 3 6 OE A2 4 5 A1 8 B1 GND 2 7 VCC(B) VCC(A) 3 6 OE A2 4 5 A1 001aam489 Figure 2. Pin configuration SOT505-2 (TSSOP8) Product data sheet 1 Transparent top view 001aam488 NTS0102 B2 Figure 3. Pin configuration SOT833-1 (XSON8) and SOT1089 (XSON8) All information provided in this document is subject to legal disclaimers. Rev. 4.4 — 6 October 2022 © 2022 NXP B.V. All rights reserved. 3 / 38 NTS0102 NXP Semiconductors Dual supply translating transceiver; open-drain; auto direction sensing NTS0102 NTS0102TLH B2 1 8 B1 B2 1 8 B1 GND 2 7 VCC(B) GND 2 7 VCC(B) VCC(A) 3 6 OE VCC(A) 3 6 OE A2 4 5 A1 A2 4 5 A1 001aam490 aaa-044580 Transparent top view Transparent top view Figure 4. Pin configuration SOT996-2 (XSON8) Figure 5. Pin configuration SOT1052-2 (XSON8) 6.2 Pin description Table 3. Pin description Symbol Pin Description B2, B1 1, 8 data input or output (referenced to VCC(B)) GND 2 ground (0 V) VCC(A) 3 supply voltage A A2, A1 4, 5 data input or output (referenced to VCC(A)) OE 6 output enable input (active HIGH; referenced to VCC(A)) VCC(B) 7 supply voltage B 7 Functional description Table 4. Function table [1] Supply voltage Input Input/output VCC(A) VCC(B) OE An Bn 1.65 V to VCC(B) 2.3 V to 5.5 V L Z Z 1.65 V to VCC(B) 2.3 V to 5.5 V H input or output output or input X Z Z GND [1] [2] [2] GND [2] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. When either VCC(A) or VCC(B) is at GND level, the device goes into power-down mode. 8 Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC(A) supply voltage A VCC(B) supply voltage B VI input voltage NTS0102 Product data sheet Conditions Min Max Unit –0.5 +6.5 V –0.5 +6.5 V A port and OE input [1] [2] –0.5 +6.5 V B port [1] [2] –0.5 +6.5 V All information provided in this document is subject to legal disclaimers. Rev. 4.4 — 6 October 2022 © 2022 NXP B.V. All rights reserved. 4 / 38 NTS0102 NXP Semiconductors Dual supply translating transceiver; open-drain; auto direction sensing Table 5. Limiting values...continued In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VO Parameter Conditions Min Max Unit –0.5 VCCO + 0.5 V A port –0.5 +4.6 V B port –0.5 +6.5 V –50 — mA –50 — mA — ±50 mA — 100 mA –100 — mA –65 +150 °C — 250 mW Active mode output voltage [1] [2] A or B port Power-down or 3-state mode IIK input clamping current VI < 0 V IOK output clamping current VO < 0 V IO output current VO = 0 V to VCCO ICC supply current ICC(A) or ICC(B) IGND ground current Tstg storage temperature Ptot [1] [2] [3] total power dissipation Tamb = -40 °C to +125 °C [1] [2] [3] The minimum input and minimum output voltage ratings may be exceeded if the input and output current ratings are observed. VCCO is the supply voltage associated with the output. For TSSOP8 package: above 55 °C, the value of Ptot derates linearly with 2.5 mW/K. For XSON8 packages: above 118 °C, the value of Ptot derates linearly with 7.8 mW/K. 9 Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter VCC(A) [1][2] Conditions Min Max Unit supply voltage A 1.65 3.6 V VCC(B) supply voltage B 2.3 5.5 V Tamb ambient temperature –40 +125 °C Δt/ΔV input transition rise and fall rate — 10 ns/V — 10 ns/V A or B port; push-pull driving VCC(A) = 1.65 V to 3.6 V; VCC(B) = 2.3 V to 5.5 V OE input VCC(A) = 1.65 V to 3.6 V; VCC(B) = 2.3 V to 5.5 V [1] [2] The A and B sides of an unused I/O pair must be held in the same state, both at VCCI or both at GND. VCC(A) must be less than or equal to VCC(B). 10 Static characteristics Table 7. Typical static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 °C. Symbol Parameter Conditions Min Typ Max Unit II OE input; VI = 0 V to 3.6 V; VCC(A) = 1.65 V to 3.6 V; VCC(B) = 2.3 V to 5.5 V — — ±1 μA input leakage current NTS0102 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4.4 — 6 October 2022 © 2022 NXP B.V. All rights reserved. 5 / 38 NTS0102 NXP Semiconductors Dual supply translating transceiver; open-drain; auto direction sensing Table 7. Typical static characteristics...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 °C. Symbol Parameter Conditions Min Typ Max Unit — — ±1 μA A port; VI or VO = 0 V to 3.6 V; VCC(A) = 0 V; VCC(B) = 0 V to 5.5 V — — ±1 μA B port; VI or VO = 0 V to 5.5 V; VCC(B) = 0 V; VCC(A) = 0 V to 3.6 V — — ±1 μA IOZ OFF-state output A or B port; VO = 0 V or VCCO; VCC(A) = 1.65 V to 3.6 V; current VCC(B) = 2.3 V to 5.5 V IOFF power-off leakage current [1] CI input capacitance OE input; VCC(A) = 3.3 V; VCC(B) = 3.3 V — 1 — pF CI/O input/output capacitance A port — 5 — pF B port — 8.5 — pF A or B port; VCC(A) = 3.3 V; VCC(B) = 3.3 V — 11 — pF [1] VCCO is the supply voltage associated with the output. Table 8. Typical supply current At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 °C. VCC(A) VCC(B) Unit 2.5 V 3.3 V 5.0 V ICC(A) ICC(B) ICC(A) ICC(B) ICC(A) ICC(B) 1.8 V 0.1 0.5 0.1 1.5 0.1 4.6 μA 2.5 V 0.1 0.1 0.1 0.8 0.1 3.8 μA 3.3 V — 0.1 0.1 0.1 2.8 μA — Table 9. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH HIGH-level input voltage Conditions -40 °C to +85 °C -40 °C to +125 °C Min Max Min Max Unit A port VCC(A) = 1.65 V to 1.95 V; VCC(B) = 2.3 V to 5.5 V [1] VCCI - 0.2 — VCCI - 0.2 — V VCC(A) = 2.3 V to 3.6 V; VCC(B) = 2.3 V to 5.5 V [1] VCCI - 0.4 — VCCI - 0.4 — V [1] VCCI - 0.4 — VCCI - 0.4 — V 0.65VCC(A) — 0.65VCC(A) — V B port VCC(A) = 1.65 V to 3.6 V; VCC(B) = 2.3 V to 5.5 V OE input VCC(A) = 1.65 V to 3.6 V; VCC(B) = 2.3 V to 5.5 V NTS0102 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4.4 — 6 October 2022 © 2022 NXP B.V. All rights reserved. 6 / 38 NTS0102 NXP Semiconductors Dual supply translating transceiver; open-drain; auto direction sensing Table 9. Static characteristics...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VIL LOW-level input voltage Conditions -40 °C to +85 °C -40 °C to +125 °C Unit Min Max Min Max — 0.15 — 0.15 — 0.35VCC(A) — 0.67VCCO — 0.67VCCO — V — 0.4 — 0.4 V — ±2 — ±12 μA — ±2 — ±12 μA A or B port VCC(A) = 1.65 V to 3.6 V; VCC(B) = 2.3 V to 5.5 V V OE input VCC(A) = 1.65 V to 3.6 V; VCC(B) = 2.3 V to 5.5 V 0.35VCC(A) V HIGH-level output voltage IO = -20 μA LOW-level output voltage A or B port; IO = 1 mA II input leakage current OE input; VI = 0 V to 3.6 V; VCC(A) = 1.65 V to 3.6 V; VCC(B) = 2.3 V to 5.5 V IOZ OFF-state output current A or B port; VO = 0 V or VCCO; VCC(A) = 1.65 V to 3.6 V; VCC(B) = 2.3 V to 5.5 V IOFF power-off leakage current A port; VI or VO = 0 V to 3.6 V; VCC(A) = 0 V; VCC(B) = 0 V to 5.5 V — ±2 — ±12 μA B port; VI or VO = 0 V to 3.6 V; VCC(B) = 0 V; VCC(A) = 0 V to 3.6 V — ±2 — ±12 μA supply current VI = 0 V or VCCI; IO = 0 A VCC(A) = 1.65 V to 3.6 V; VCC(B) = 2.3 V to 5.5 V — 2.4 — 15 μA VCC(A) = 3.6 V; VCC(B) = 0 V — 2.2 — 15 μA VCC(A) = 0 V; VCC(B) = 5.5 V — –1 — –8 μA VCC(A) = 1.65 V to 3.6 V; VCC(B) = 2.3 V to 5.5 V — 12 — 30 μA VCC(A) = 3.6 V; VCC(B) = 0 V — –1 — –5 μA VCC(A) = 0 V; VCC(B) = 5.5 V — 1 — 6 μA — 14.4 — 30 μA VOH VOL ICC VCC(A) = 1.65 V to 3.6 V; VCC(B) = 2.3 V to 5.5 V [2] [2] VI ≤ 0.15 V; VCC(A) = 1.65 V to 3.6 V; VCC(B) = 2.3 V to 5.5 V [2] [1] ICC(A) ICC(B) ICC(A) + ICC(B) VCC(A) = 1.65 V to 3.6 V; VCC(B) = 2.3 V to 5.5 V [1] [2] VCCI is the supply voltage associated with the input. VCCO is the supply voltage associated with the output. NTS0102 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4.4 — 6 October 2022 © 2022 NXP B.V. All rights reserved. 7 / 38 NTS0102 NXP Semiconductors Dual supply translating transceiver; open-drain; auto direction sensing 11 Dynamic characteristics [1] Table 10. Dynamic characteristics for temperature range -40 °C to +85 °C Voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 8; for wave forms see Figure 6 and Figure 7. Symbol Parameter Conditions VCC(B) Unit 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5.0 V ± 0.5 V Min Max Min Max Min Max VCC(A) = 1.8 V ± 0.15 V tPHL HIGH to LOW propagation delay A to B — 4.6 — 4.7 — 5.8 ns tPLH LOW to HIGH propagation delay A to B — 6.8 — 6.8 — 7.0 ns tPHL HIGH to LOW propagation delay B to A — 4.4 — 4.5 — 4.7 ns tPLH LOW to HIGH propagation delay B to A — 5.3 — 4.5 — 0.5 ns ten enable time OE to A; B — 200 — 200 — 200 ns OE to A; no external load [2] — 25 — 25 — 25 ns OE to B; no external load [2] — 25 — 25 — 25 ns OE to A — 230 — 230 — 230 ns OE to B — 200 — 200 — 200 ns LOW to HIGH output transition time A port 3.2 9.5 2.3 9.3 1.8 7.6 ns B port 3.3 10.8 2.7 9.1 2.7 7.6 ns HIGH to LOW output transition time A port 2.0 5.9 1.9 6.0 1.7 13.3 ns B port 2.9 7.6 2.8 7.5 2.8 10.0 ns tsk(o) output skew time between channels — 0.7 — 0.7 — 0.7 ns tW pulse width data inputs 20 — 20 — 20 — ns fdata data rate — 50 — 50 — 50 Mbit/s tdis tTLH tTHL disable time [3] VCC(A) = 2.5 V ± 0.2 V tPHL HIGH to LOW propagation delay A to B — 3.2 — 3.3 — 3.4 ns tPLH LOW to HIGH propagation delay A to B — 3.5 — 4.1 — 4.4 ns tPHL HIGH to LOW propagation delay B to A — 3.0 — 3.6 — 4.3 ns tPLH LOW to HIGH propagation delay B to A — 2.5 — 1.6 — 0.7 ns ten enable time OE to A; B tdis disable time — 200 — 200 — 200 ns OE to A; no external load [2] — 20 — 20 — 20 ns OE to B; no external load [2] — 20 — 20 — 20 ns — 200 — 200 — 200 ns OE to A NTS0102 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4.4 — 6 October 2022 © 2022 NXP B.V. All rights reserved. 8 / 38 NTS0102 NXP Semiconductors Dual supply translating transceiver; open-drain; auto direction sensing [1] Table 10. Dynamic characteristics for temperature range -40 °C to +85 °C ...continued Voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 8; for wave forms see Figure 6 and Figure 7. Symbol Parameter Conditions VCC(B) Unit 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5.0 V ± 0.5 V Min Max Min Max Min Max OE to B — 200 — 200 — 200 ns LOW to HIGH output transition time A port 2.8 7.4 2.6 6.6 1.8 6.2 ns B port 3.2 8.3 2.9 7.9 2.4 6.8 ns HIGH to LOW output transition time A port 1.9 5.7 1.9 5.5 1.8 5.3 ns B port 2.2 7.8 2.4 6.7 2.6 6.6 ns tsk(o) output skew time between channels — 0.7 — 0.7 — 0.7 ns tW pulse width data inputs 20 — 20 — 20 — ns fdata data rate — 50 — 50 — 50 Mbit/s tTLH tTHL [3] VCC(A) = 3.3 V ± 0.3 V tPHL HIGH to LOW propagation delay A to B — — — 2.4 — 3.1 ns tPLH LOW to HIGH propagation delay A to B — — — 4.2 — 4.4 ns tPHL HIGH to LOW propagation delay B to A — — — 2.5 — 3.3 ns tPLH LOW to HIGH propagation delay B to A — — — 2.5 — 2.6 ns ten enable time OE to A; B — — — 200 — 200 ns OE to A; no external load [2] — — — 15 — 15 ns OE to B; no external load [2] — — — 15 — 15 ns OE to A — — — 260 — 260 ns OE to B — — — 200 — 200 ns LOW to HIGH output transition time A port — — 2.3 5.6 1.9 5.9 ns B port — — 2.5 6.4 2.1 7.4 ns HIGH to LOW output transition time A port — — 2.0 5.4 1.9 5.0 ns B port — — 2.3 7.4 2.4 7.6 ns tsk(o) output skew time between channels — — — 0.7 — 0.7 ns tW pulse width data inputs — — 20 — 20 — ns fdata data rate — — — 50 — 50 Mbit/s tdis disable time tTLH tTHL [1] [2] [3] [3] ten is the same as tPZL and tPZH. tdis is the same as tPLZ and tPHZ. Delay between OE going LOW and when the outputs are actually disabled. Skew between any two outputs of the same package switching in the same direction. NTS0102 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4.4 — 6 October 2022 © 2022 NXP B.V. All rights reserved. 9 / 38 NTS0102 NXP Semiconductors Dual supply translating transceiver; open-drain; auto direction sensing [1] Table 11. Dynamic characteristics for temperature range -40 °C to +125 °C Voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 8; for wave forms see Figure 6 and Figure 7. Symbol Parameter Conditions VCC(B) Unit 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5.0 V ± 0.5 V Min Max Min Max Min Max VCC(A) = 1.8 V ± 0.15 V tPHL HIGH to LOW propagation delay A to B — 5.8 — 5.9 — 7.3 ns tPLH LOW to HIGH propagation delay A to B — 8.5 — 8.5 — 8.8 ns tPHL HIGH to LOW propagation delay B to A — 5.5 — 5.7 — 5.9 ns tPLH LOW to HIGH propagation delay B to A — 6.7 — 5.7 — 0.7 ns ten enable time OE to A; B — 200 — 200 — 200 ns OE to A; no external load [2] — 30 — 30 — 30 ns OE to B; no external load [2] — 30 — 30 — 30 ns OE to A — 250 — 250 — 250 ns OE to B — 220 — 220 — 220 ns LOW to HIGH output transition time A port 3.2 11.9 2.3 11.7 1.8 9.5 ns B port 3.3 13.5 2.7 11.4 2.7 9.5 ns HIGH to LOW output transition time A port 2.0 7.4 1.9 7.5 1.7 16.7 ns B port 2.9 9.5 2.8 9.4 2.8 12.5 ns tsk(o) output skew time between channels — 0.8 — 0.8 — 0.8 ns tW pulse width data inputs 20 — 20 — 20 — ns fdata data rate — 50 — 50 — 50 Mbit/ s tdis tTLH tTHL disable time [3] VCC(A) = 2.5 V ± 0.2 V tPHL HIGH to LOW propagation delay A to B — 4.0 — 4.2 — 4.3 ns tPLH LOW to HIGH propagation delay A to B — 4.4 — 5.2 — 5.5 ns tPHL HIGH to LOW propagation delay B to A — 3.8 — 4.5 — 5.4 ns tPLH LOW to HIGH propagation delay B to A — 3.2 — 2.0 — 0.9 ns ten enable time OE to A; B tdis disable time NTS0102 Product data sheet — 200 — 200 — 200 ns OE to A; no external load [2] — 25 — 25 — 25 ns OE to B; no external load [2] — 25 — 25 — 25 ns OE to A — 220 — 220 — 220 ns OE to B — 220 — 220 — 220 ns All information provided in this document is subject to legal disclaimers. Rev. 4.4 — 6 October 2022 © 2022 NXP B.V. All rights reserved. 10 / 38 NTS0102 NXP Semiconductors Dual supply translating transceiver; open-drain; auto direction sensing [1] Table 11. Dynamic characteristics for temperature range -40 °C to +125 °C ...continued Voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 8; for wave forms see Figure 6 and Figure 7. Symbol Parameter Conditions VCC(B) Unit 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5.0 V ± 0.5 V Min Max Min Max Min Max LOW to HIGH output transition time A port 2.8 9.3 2.6 8.3 1.8 7.8 ns B port 3.2 10.4 2.9 9.7 2.4 8.3 ns HIGH to LOW output transition time A port 1.9 7.2 1.9 6.9 1.8 6.7 ns B port 2.2 9.8 2.4 8.4 2.6 8.3 ns tsk(o) output skew time between channels — 0.8 — 0.8 — 0.8 ns tW pulse width data inputs 20 — 20 — 20 — ns fdata data rate — 50 — 50 — 50 Mbit/ s tTLH tTHL [3] VCC(A) = 3.3 V ± 0.3 V tPHL HIGH to LOW propagation delay A to B — — — 3.0 — 3.9 ns tPLH LOW to HIGH propagation delay A to B — — — 5.3 — 5.5 ns tPHL HIGH to LOW propagation delay B to A — — — 3.2 — 4.2 ns tPLH LOW to HIGH propagation delay B to A — — — 3.2 — 3.3 ns ten enable time OE to A; B — — — 200 — 200 ns OE to A; no external load [2] — — — 20 — 20 ns OE to B; no external load [2] — — — 20 — 20 ns OE to A — — — 280 — 280 ns OE to B — — — 220 — 220 ns LOW to HIGH output transition time A port — — 2.3 7.0 1.9 7.4 ns B port — — 2.5 8.0 2.1 9.3 ns HIGH to LOW output transition time A port — — 2.0 6.8 1.9 6.3 ns B port — — 2.3 9.3 2.4 9.5 ns tsk(o) output skew time between channels — — — 0.8 — 0.8 ns tW pulse width data inputs — — 20 — 20 — ns fdata data rate — — — 50 — 50 Mbit/ s tdis disable time tTLH tTHL [1] [2] [3] [3] ten is the same as tPZL and tPZH. tdis is the same as tPLZ and tPHZ. Delay between OE going LOW and when the outputs are actually disabled. Skew between any two outputs of the same package switching in the same direction. NTS0102 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4.4 — 6 October 2022 © 2022 NXP B.V. All rights reserved. 11 / 38 NTS0102 NXP Semiconductors Dual supply translating transceiver; open-drain; auto direction sensing 12 Waveforms VI An, Bn input VM GND tPHL VOH Bn, An output tPLH 90 % VM 10 % VOL tTHL tTLH 001aal918 Measurement points are given in Table 12. VOL and VOH are typical output voltage levels that occur with the output load. Figure 6. The data input (An, Bn) to data output (Bn, An) propagation delay times VI OE input VM GND tPLZ output LOW-to-OFF OFF-to-LOW tPZL VCCO VM VX VOL tPHZ output HIGH-to-OFF OFF-to-HIGH VOH tPZH VY VM GND outputs enabled outputs disabled outputs enabled 001aal919 Measurement points are given in Table 12. VOL and VOH are typical output voltage levels that occur with the output load. Figure 7. Enable and disable times Table 12. Measurement points [1][2] Supply voltage Input Output VCCO VM VM VX VY 1.8 V ± 0.15 V 0.5VCCI 0.5VCCO VOL + 0.15 V VOH – 0.15 V 2.5 V ± 0.2 V 0.5VCCI 0.5VCCO VOL + 0.15 V VOH – 0.15 V 3.3 V ± 0.3 V 0.5VCCI 0.5VCCO VOL + 0.3 V VOH – 0.3 V 5.0 V ± 0.5 V 0.5VCCI 0.5VCCO VOL + 0.3 V VOH– 0.3 V [1] [2] VCCI is the supply voltage associated with the input. VCCO is the supply voltage associated with the output. NTS0102 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4.4 — 6 October 2022 © 2022 NXP B.V. All rights reserved. 12 / 38 NTS0102 NXP Semiconductors Dual supply translating transceiver; open-drain; auto direction sensing tW VI 90 % negative pulse VM VM 10 % 0V tf tr tr VI tf 90 % positive pulse VM VM 10 % 0V tW VEXT VCC G VI RL VO DUT CL RL 001aal963 Test data is given in Table 13. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz; ZO = 50 Ω; dV/dt ≥ 1.0 V/ ns. RL = Load resistance. CL = Load capacitance including jig and probe capacitance. VEXT = External voltage for measuring switching times. Figure 8. Test circuit for measuring switching times Table 13. Test data Supply voltage Input VCC(A) VCC(B) [1] VI Δt/ΔV CL [2] RL 1.65 V to 3.6 V 2.3 V to 5.5 V VCCI ≤ 1.0 ns/V 15 pF 50 kΩ, 1 MΩ open [1] [2] [3] Load VEXT tPLH, tPHL [3] tPZH, tPHZ tPZL, tPLZ open 2VCCO VCCI is the supply voltage associated with the input. For measuring data rate, pulse width, propagation delay, and output rise and fall measurements, RL = 1 MΩ; for measuring enable and disable times, RL = 50 KΩ. VCCO is the supply voltage associated with the output. 13 Application information 13.1 Applications Voltage level-translation applications. The NTS0102 can be used in point-to-point applications to interface between devices or systems operating at different supply 2 voltages. The device is primarily targeted at I C or 1-wire which use open-drain drivers, it may also be used in applications where push-pull drivers are connected to the ports, however the NTB0102 may be more suitable. NTS0102 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4.4 — 6 October 2022 © 2022 NXP B.V. All rights reserved. 13 / 38 NTS0102 NXP Semiconductors Dual supply translating transceiver; open-drain; auto direction sensing 1.8 V 3.3 V 0.1 µF 1.8 V SYSTEM CONTROLLER VCC(A) VCC(B) 3.3 V SYSTEM 0.1 µF 1 µF OE NTS0102 DATA A1 B1 A2 B2 DATA 001aam491 Figure 9. Typical operating circuit 13.2 Architecture The architecture of the NTS0102 is shown in Figure 10. The device does not require an extra input signal to control the direction of data flow from A to B or B to A. VCC(A) VCC(B) T1 ONE SHOT ONE SHOT T2 10 kΩ 10 kΩ GATE BIAS A T3 B 001aal965 Figure 10. Architecture of NTS0102 I/O cell (one channel) The NTS0102 is a "switch" type voltage translator, it employs two key circuits to enable voltage translation: 1. A pass-gate transistor (N-channel) that ties the ports together. 2. An output edge-rate accelerator that detects and accelerates rising edges on the I/O pins. The gate bias voltage of the pass gate transistor (T3) is set at approximately one threshold voltage above the VCC level of the low-voltage side. During a LOW-to-HIGH transition, the output one-shot accelerates the output transition by switching on the PMOS transistors (T1, T2) bypassing the 10 kΩ pull-up resistors and increasing current drive capability. The one-shot is activated once the input transition reaches approximately VCCI/2; it is de-activated approximately 50 ns after the output reaches VCCO/2. During the acceleration time, the driver output resistance is between approximately 50 Ω and 70 Ω. To avoid signal contention and minimize dynamic ICC, the user should wait for the oneshot circuit to turn-off before applying a signal in the opposite direction. Pull-up resistors are included in the device for DC current sourcing capability. NTS0102 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4.4 — 6 October 2022 © 2022 NXP B.V. All rights reserved. 14 / 38 NTS0102 NXP Semiconductors Dual supply translating transceiver; open-drain; auto direction sensing 13.3 Input driver requirements As the NTS0102 is a switch type translator, properties of the input driver directly effect the output signal. The external open-drain or push-pull driver applied to an I/O determines the static current sinking capability of the system; the max data rate, HIGHto-LOW output transition time (tTHL), and propagation delay (tPHL) are dependent upon the output impedance and edge-rate of the external driver. The limits provided for these parameters in the data sheet assume a driver with output impedance below 50 Ω is used. 13.4 Output load considerations The maximum lumped capacitive load that can be driven is dependent upon the one-shot pulse duration. In cases with very heavy capacitive loading, there is a risk that the output will not reach the positive rail within the one-shot pulse duration. To avoid excessive capacitive loading, and to ensure correct triggering of the oneshot, it's recommended to use short trace lengths and low capacitance connectors on NTS0102 PCB layouts. To ensure low impedance termination and avoid output signal oscillations and one-shot re-triggering, the length of the PCB trace should be such that the round trip delay of any reflection is within the one-shot pulse duration (approximately 50 ns). 13.5 Power up During operation VCC(A) must never be higher than VCC(B), however during power-up VCC(A) ≥ VCC(B) does not damage the device, so either power supply can be ramped up first. There is no special power-up sequencing required. The NTS0102 includes circuitry that disables all output ports when either VCC(A) or VCC(B) is switched off. 13.6 Enable and disable An output enable input (OE) is used to disable the device. Setting OE = LOW causes all I/Os to assume the high-impedance OFF-state. The disable time (tdis with no external load) indicates the delay between when OE goes LOW and when outputs actually become disabled. The enable time (ten) indicates the amount of time the user must allow for one one-shot circuitry to become operational after OE is taken HIGH. To ensure the high-impedance OFF-state during power-up or power-down, pin OE should be tied to GND through a pull-down resistor, the minimum value of the resistor is determined by the current-sourcing capability of the driver. 13.7 Pull-up or pull-down resistors on I/Os lines Each A port I/O has an internal 10 kΩ pull-up resistor to VCC(A), and each B port I/O has an internal 10 kΩ pull-up resistor to VCC(B). If a smaller value of pull-up resistor is required, an external resistor must be added parallel to the internal 10 kΩ, this effects the VOL level. When OE goes LOW the internal pull-ups of the NTS0102 are disabled. 13.8 GD package vs TL package Due to differences in package construction the TL package has a center pad vs no center pad for the GD package. The following section provides guidance in replacement vs new applications. NTS0102 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4.4 — 6 October 2022 © 2022 NXP B.V. All rights reserved. 15 / 38 NTS0102 NXP Semiconductors Dual supply translating transceiver; open-drain; auto direction sensing • No trace under GD package 1. Replacement of GD package: The pad is not electrically connected to the silicon (no wire bond and epoxy is not conductive) and can be left floating. It is not required to be connected to the PCB. Simply place the TL package on the same PCB traces as the existing GD package. 2. New use of the TL package: Place PCB trace for soldering of the center pad based on PCB layout recommendations for better mechanical connection and thermal conductivity. The PCB center pad can be connect to GND or left floating. • Trace under the GD package 1. Replacement of GD package: It is not best practice to have center pad over the trace but since the TL package center pad is not connected to the silicon the risk is low. If there are multiple traces there could be EMI and cross talk. In both cases the customer needs to evaluate risk. 2. New use of the TL package: Do not route traces under the package NTS0102 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4.4 — 6 October 2022 © 2022 NXP B.V. All rights reserved. 16 / 38 NTS0102 NXP Semiconductors Dual supply translating transceiver; open-drain; auto direction sensing 14 Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm D E A SOT505-2 X c HE y v M A Z 5 8 A A2 pin 1 index (A3) A1 θ Lp L 1 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(1) e HE L Lp v w y Z(1) θ mm 1.1 0.15 0.00 0.95 0.75 0.25 0.38 0.22 0.18 0.08 3.1 2.9 3.1 2.9 0.65 4.1 3.9 0.5 0.47 0.33 0.2 0.13 0.1 0.70 0.35 8° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT505-2 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 02-01-16 --- Figure 11. Package outline SOT505-2 (TSSOP8) NTS0102 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4.4 — 6 October 2022 © 2022 NXP B.V. All rights reserved. 17 / 38 NTS0102 NXP Semiconductors Dual supply translating transceiver; open-drain; auto direction sensing XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm 1 2 SOT833-1 b 4 3 4× (2) L L1 e 8 7 6 e1 5 e1 e1 8× A (2) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max A1 max b D E e e1 L L1 mm 0.5 0.04 0.25 0.17 2.0 1.9 1.05 0.95 0.6 0.5 0.35 0.27 0.40 0.32 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT833-1 --- MO-252 --- EUROPEAN PROJECTION ISSUE DATE 07-11-14 07-12-07 Figure 12. Package outline SOT833-1 (XSON8) NTS0102 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4.4 — 6 October 2022 © 2022 NXP B.V. All rights reserved. 18 / 38 NTS0102 NXP Semiconductors Dual supply translating transceiver; open-drain; auto direction sensing XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 3 x 2 x 0.5 mm D SOT996-2 B A E A A1 detail X terminal 1 index area e1 1 4 8 5 C C A B C v w b e L1 y1 C y L2 L X 0 1 2 mm scale Dimensions (mm are the original dimensions) Unit(1) mm max nom min A 0.5 A1 b D E 0.05 0.35 2.1 3.1 0.00 0.15 1.9 2.9 e e1 0.5 1.5 L L1 L2 0.5 0.15 0.6 0.3 0.05 0.4 v 0.1 w y 0.05 0.05 y1 0.1 sot996-2_po Outline version References IEC JEDEC JEITA European projection Issue date 07-12-21 12-11-20 SOT996-2 Figure 13. Package outline SOT996-2 (XSON8) NTS0102 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4.4 — 6 October 2022 © 2022 NXP B.V. All rights reserved. 19 / 38 NTS0102 NXP Semiconductors Dual supply translating transceiver; open-drain; auto direction sensing XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.35 x 1 x 0.5 mm SOT1089 E terminal 1 index area D A A1 detail X (4×)(2) e L (8×)(2) b 4 5 e1 1 terminal 1 index area 8 L1 X 0 0.5 scale Dimensions Unit mm max nom min 1 mm A(1) 0.5 A1 b D E e e1 L L1 0.04 0.20 1.40 1.05 0.35 0.40 0.15 1.35 1.00 0.55 0.35 0.30 0.35 0.12 1.30 0.95 0.27 0.32 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version SOT1089 sot1089_po References IEC JEDEC JEITA European projection Issue date 10-04-09 10-04-12 MO-252 Figure 14. Package outline SOT1089 (XSON8) NTS0102 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4.4 — 6 October 2022 © 2022 NXP B.V. All rights reserved. 20 / 38 NTS0102 NXP Semiconductors Dual supply translating transceiver; open-drain; auto direction sensing Figure 15. Package outline SOT1052-2 (XSON8) NTS0102 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4.4 — 6 October 2022 © 2022 NXP B.V. All rights reserved. 21 / 38 NTS0102 NXP Semiconductors Dual supply translating transceiver; open-drain; auto direction sensing Figure 16. Package outline SOT1052-2 (XSON8) NTS0102 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4.4 — 6 October 2022 © 2022 NXP B.V. All rights reserved. 22 / 38 NTS0102 NXP Semiconductors Dual supply translating transceiver; open-drain; auto direction sensing 15 Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 15.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 15.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 15.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 15.4 Reflow soldering Key characteristics in reflow soldering are: NTS0102 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4.4 — 6 October 2022 © 2022 NXP B.V. All rights reserved. 23 / 38 NTS0102 NXP Semiconductors Dual supply translating transceiver; open-drain; auto direction sensing • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 17) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 14 and Table 15 Table 14. SnPb eutectic process (from J-STD-020D) Package thickness (mm) Package reflow temperature (°C) Volume (mm³) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220 Table 15. Lead-free process (from J-STD-020D) Package thickness (mm) Package reflow temperature (°C) Volume (mm³) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 17. NTS0102 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4.4 — 6 October 2022 © 2022 NXP B.V. All rights reserved. 24 / 38 NTS0102 NXP Semiconductors Dual supply translating transceiver; open-drain; auto direction sensing temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Figure 17. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. NTS0102 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4.4 — 6 October 2022 © 2022 NXP B.V. All rights reserved. 25 / 38 NTS0102 NXP Semiconductors Dual supply translating transceiver; open-drain; auto direction sensing 16 Soldering: PCB footprints Footprint information for reflow soldering of TSSOP8 package SOT505-2 Hx Gx P2 (0.125) Hy Gy (0.125) By Ay C D2 (4x) D1 P1 Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 P2 Ay By C D1 D2 Gx Gy Hx Hy 0.650 0.700 4.400 2.700 0.850 0.400 0.500 2.800 3.600 3.600 4.650 sot505-2_fr Figure 18. PCB footprint for SOT505-2 (TSSOP8); reflow soldering NTS0102 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4.4 — 6 October 2022 © 2022 NXP B.V. All rights reserved. 26 / 38 NTS0102 NXP Semiconductors Dual supply translating transceiver; open-drain; auto direction sensing 2.150 pa + oa 2.100 1.150 pa + oa 1.250 2.450 1.000 0.950 (7 ×) 0.475 0.250 (4 ×) 0.500 0.300 (4 ×) 0.125 (4 ×) solder land 0.025 solder paste placement area occupied area Dimensions in mm sot833-1_fr Figure 19. PCB footprint for SOT833-1 (XSON8); reflow soldering NTS0102 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4.4 — 6 October 2022 © 2022 NXP B.V. All rights reserved. 27 / 38 NTS0102 NXP Semiconductors Dual supply translating transceiver; open-drain; auto direction sensing 2.400 pa + oa 2.000 0.500 0.500 0.250 0.025 0.025 4.250 3.400 pa + oa 2.000 4.000 0.900 solder lands placement area solder paste occupied area Dimensions in mm sot996-2_fr Figure 20. PCB footprint for SOT996-2 (XSON8U); reflow soldering NTS0102 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4.4 — 6 October 2022 © 2022 NXP B.V. All rights reserved. 28 / 38 NTS0102 NXP Semiconductors Dual supply translating transceiver; open-drain; auto direction sensing Footprint information for reflow soldering of XSON8 package 0.15 (8×) SOT1089 0.25 (8×) 0.5 (8×) 0.7 1.4 0.6 (8×) Dimensions in mm solder paste = solder land 0.35 (3×) 1.4 solder resist occupied area sot1089_fr Figure 21. PCB footprint for SOT1089 (XSON8); reflow soldering NTS0102 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4.4 — 6 October 2022 © 2022 NXP B.V. All rights reserved. 29 / 38 NTS0102 NXP Semiconductors Dual supply translating transceiver; open-drain; auto direction sensing Figure 22. PCB footprint for SOT1052-2 (XSON8); recommended solder mask opening pattern NTS0102 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4.4 — 6 October 2022 © 2022 NXP B.V. All rights reserved. 30 / 38 NTS0102 NXP Semiconductors Dual supply translating transceiver; open-drain; auto direction sensing Figure 23. PCB footprint for SOT1052-2 (XSON8); recommended I/O pads and solderable area NTS0102 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4.4 — 6 October 2022 © 2022 NXP B.V. All rights reserved. 31 / 38 NTS0102 NXP Semiconductors Dual supply translating transceiver; open-drain; auto direction sensing Figure 24. PCB footprint for SOT1052-2 (XSON8); recommended solder paste stencil NTS0102 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4.4 — 6 October 2022 © 2022 NXP B.V. All rights reserved. 32 / 38 NTS0102 NXP Semiconductors Dual supply translating transceiver; open-drain; auto direction sensing Figure 25. PCB footprint for SOT1052-2 (XSON8); notes NTS0102 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4.4 — 6 October 2022 © 2022 NXP B.V. All rights reserved. 33 / 38 NTS0102 NXP Semiconductors Dual supply translating transceiver; open-drain; auto direction sensing 17 Abbreviations Table 16. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge GPIO General Purpose Input Output HBM Human Body Model 2 I C Inter-Integrated Circuit MM Machine Model PCB Printed-circuit board PMOS Positive Metal Oxide Semiconductor SMBus System Management Bus UART Universal Asynchronous Receiver Transmitter UTLP Ultra Thin Leadless Package 18 Revision history Table 17. Revision history Document ID Release date Data sheet status Change notice Supersedes NTS0102 v.4.4 20221006 Product data sheet 202210008I NTS0102 v.4.3 Modifications: • Table 2: NTS0102TL Minimum Order Quantity corrected to 4Ku per reel NTS0102 v.4.3 20220420 Product data sheet — NTS0102 v.4.2 NTS0102 v.4.2 20220303 Product data sheet — NTS0102 v.4.1 NTS0102 v.4.1 20211112 Product data sheet — NTS0102 v.4 NTS0102 v.4 20130123 Product data sheet — NTS0102 v.3 NTS0102 v.3 20111117 Product data sheet — NTS0102 v.2 NTS0102 v.2 20110411 Product data sheet — NTS0102 v.1 NTS0102 v.1 20100921 Product data sheet — — NTS0102 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4.4 — 6 October 2022 © 2022 NXP B.V. All rights reserved. 34 / 38 NTS0102 NXP Semiconductors Dual supply translating transceiver; open-drain; auto direction sensing 19 Legal information 19.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 19.2 Definitions Draft — A draft status on a document indicates that the content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included in a draft version of a document and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 19.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. NTS0102 Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 4.4 — 6 October 2022 © 2022 NXP B.V. All rights reserved. 35 / 38 NTS0102 NXP Semiconductors Dual supply translating transceiver; open-drain; auto direction sensing Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Suitability for use in non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document, including the legal information in that document, is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. NTS0102 Product data sheet Security — Customer understands that all NXP products may be subject to unidentified vulnerabilities or may support established security standards or specifications with known limitations. Customer is responsible for the design and operation of its applications and products throughout their lifecycles to reduce the effect of these vulnerabilities on customer’s applications and products. Customer’s responsibility also extends to other open and/or proprietary technologies supported by NXP products for use in customer’s applications. NXP accepts no liability for any vulnerability. Customer should regularly check security updates from NXP and follow up appropriately. Customer shall select products with security features that best meet rules, regulations, and standards of the intended application and make the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. NXP has a Product Security Incident Response Team (PSIRT) (reachable at PSIRT@nxp.com) that manages the investigation, reporting, and solution release to security vulnerabilities of NXP products. 19.4 Trademarks Notice: All referenced brands, product names, service names, and trademarks are the property of their respective owners. NXP — wordmark and logo are trademarks of NXP B.V. All information provided in this document is subject to legal disclaimers. Rev. 4.4 — 6 October 2022 © 2022 NXP B.V. All rights reserved. 36 / 38 NTS0102 NXP Semiconductors Dual supply translating transceiver; open-drain; auto direction sensing Tables Tab. 1. Tab. 2. Tab. 3. Tab. 4. Tab. 5. Tab. 6. Tab. 7. Tab. 8. Tab. 9. Ordering information ..........................................2 Ordering options ................................................2 Pin description ...................................................4 Function table ....................................................4 Limiting values .................................................. 4 Recommended operating conditions ................. 5 Typical static characteristics ..............................5 Typical supply current ....................................... 6 Static characteristics ......................................... 6 Tab. 10. Tab. 11. Tab. 12. Tab. 13. Tab. 14. Tab. 15. Tab. 16. Tab. 17. Dynamic characteristics for temperature range -40 °C to +85 °C .....................................8 Dynamic characteristics for temperature range -40 °C to +125 °C ................................. 10 Measurement points ........................................12 Test data ..........................................................13 SnPb eutectic process (from J-STD-020D) ..... 24 Lead-free process (from J-STD-020D) ............ 24 Abbreviations ...................................................34 Revision history ...............................................34 Figures Fig. 1. Fig. 2. Fig. 3. Fig. 4. Fig. 5. Fig. 6. Fig. 7. Fig. 8. Fig. 9. Fig. 10. Fig. 11. Fig. 12. Fig. 13. Fig. 14. Fig. 15. Fig. 16. Logic symbol ..................................................... 3 Pin configuration SOT505-2 (TSSOP8) .............3 Pin configuration SOT833-1 (XSON8) and SOT1089 (XSON8) ........................................... 3 Pin configuration SOT996-2 (XSON8) ...............4 Pin configuration SOT1052-2 (XSON8) .............4 The data input (An, Bn) to data output (Bn, An) propagation delay times ........................... 12 Enable and disable times ................................12 Test circuit for measuring switching times ....... 13 Typical operating circuit ...................................14 Architecture of NTS0102 I/O cell (one channel) ...........................................................14 Package outline SOT505-2 (TSSOP8) ............17 Package outline SOT833-1 (XSON8) ..............18 Package outline SOT996-2 (XSON8) ..............19 Package outline SOT1089 (XSON8) ............... 20 Package outline SOT1052-2 (XSON8) ............21 Package outline SOT1052-2 (XSON8) ............22 NTS0102 Product data sheet Fig. 17. Fig. 18. Fig. 19. Fig. 20. Fig. 21. Fig. 22. Fig. 23. Fig. 24. Fig. 25. Temperature profiles for large and small components ..................................................... 25 PCB footprint for SOT505-2 (TSSOP8); reflow soldering ............................................... 26 PCB footprint for SOT833-1 (XSON8); reflow soldering ............................................... 27 PCB footprint for SOT996-2 (XSON8U); reflow soldering ............................................... 28 PCB footprint for SOT1089 (XSON8); reflow soldering ............................................... 29 PCB footprint for SOT1052-2 (XSON8); recommended solder mask opening pattern ... 30 PCB footprint for SOT1052-2 (XSON8); recommended I/O pads and solderable area ................................................................. 31 PCB footprint for SOT1052-2 (XSON8); recommended solder paste stencil ..................32 PCB footprint for SOT1052-2 (XSON8); notes ................................................................33 All information provided in this document is subject to legal disclaimers. Rev. 4.4 — 6 October 2022 © 2022 NXP B.V. All rights reserved. 37 / 38 NTS0102 NXP Semiconductors Dual supply translating transceiver; open-drain; auto direction sensing Contents 1 2 3 4 4.1 5 6 6.1 6.2 7 8 9 10 11 12 13 13.1 13.2 13.3 13.4 13.5 13.6 13.7 13.8 14 15 15.1 15.2 15.3 15.4 16 17 18 19 General description ............................................ 1 Features and benefits .........................................1 Applications .........................................................1 Ordering information .......................................... 2 Ordering options ................................................ 2 Functional diagram ............................................. 3 Pinning information ............................................ 3 Pinning ............................................................... 3 Pin description ................................................... 4 Functional description ........................................4 Limiting values .................................................... 4 Recommended operating conditions ................ 5 Static characteristics .......................................... 5 Dynamic characteristics .....................................8 Waveforms ......................................................... 12 Application information .................................... 13 Applications ......................................................13 Architecture ......................................................14 Input driver requirements .................................15 Output load considerations .............................. 15 Power up ......................................................... 15 Enable and disable ..........................................15 Pull-up or pull-down resistors on I/Os lines ......15 GD package vs TL package ............................ 15 Package outline .................................................17 Soldering of SMD packages .............................23 Introduction to soldering .................................. 23 Wave and reflow soldering .............................. 23 Wave soldering ................................................ 23 Reflow soldering .............................................. 23 Soldering: PCB footprints ................................ 26 Abbreviations .................................................... 34 Revision history ................................................ 34 Legal information .............................................. 35 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © 2022 NXP B.V. All rights reserved. For more information, please visit: http://www.nxp.com Date of release: 6 October 2022 Document identifier: NTS0102
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