NVT4555UKZ

NVT4555 SIM card interface level translator and supply voltage LDO Rev. 2 — 24 May 2013 Product data sheet 1. General description The NVT4555 device is built for interfacing a SIM card with a single low-voltage host side interface. The NVT4555 contains an LDO that can deliver two different voltages, 1.8 V or 2.95 V from typical mobile phone battery voltages up to 5.25 V and three level translators to convert the data, RSTn and CLKn signals between a SIM card and a host microcontroller. The NVT4555 contains one voltage select pin (CTRL) to select either 1.8 V or 2.95 V for SIM card power supply and one active HIGH enable pin (EN) to enable normal operation. The NVT4555 is compliant with all ETSI, IMT-2000 and ISO-7816 SIM/Smart card interface requirements. 2. Features and benefits           Support SIM card supply voltages 1.8 V and 2.95 V Input voltage range to LDO: 2.5 V to 5.25 V Host microcontroller operating voltage range: 1.1 V to 3.6 V Automatic level translation of I/O, RSTn and CLKn between SIM card and host side interface with capacitance isolation Low current shutdown (EN = 0) mode < 1 A Supports clock speed beyond 5 MHz clock Incorporates shutdown feature for the SIM card signals according to ISO-7816-3 8 kV IEC61000-4-2 ESD protected on all SIM card contact pins Pb-free, Restriction of Hazardous Substances (RoHS) compliant and free of halogen and antimony (Dark Green compliant) Available in 12-pin WLCSP package (1.19 mm  1.62 mm  0.56 mm (nominal), 0.4 mm pitch) 3. Applications  NVT4555 can be used with a range of SIM card attached devices including:  Mobile and personal phones  Wireless modems  SIM card terminals NVT4555 NXP Semiconductors SIM card interface level translator and supply voltage LDO 4. Ordering information Table 1. Ordering information Type number NVT4555UK Topside mark Package Name Description Version 4555 WLCSP12 wafer level chip-size package; 12 bumps; body 1.19  1.62  0.56 mm NVT4555UK 4.1 Ordering options Table 2. Ordering options Type number Orderable part number Package Packing method Minimum order quantity Temperature NVT4555UK NVT4555UKZ WLCSP12 Reel 7” Q1/T1 *special mark chips DP 3000 Tamb = 40 C to +85 C 5. Functional diagram VBAT VSIM LDO VCC RST_HOST RST_SIM CLK_HOST CLK_SIM IO_SIM IO_HOST EN CONTROL LOGIC CTRL GND 002aag074 Fig 1. NVT4555 Product data sheet Functional diagram All information provided in this document is subject to legal disclaimers. Rev. 2 — 24 May 2013 © NXP B.V. 2013. All rights reserved. 2 of 18 NVT4555 NXP Semiconductors SIM card interface level translator and supply voltage LDO 6. Pinning information bump A1 index area NVT4555UK A1 A2 A3 B1 B2 B3 C1 C2 C3 D1 D2 D3 1 2 3 A IO_HOST GND VCC B RST_HOST CTRL VBAT C CLK_HOST EN VSIM D CLK_SIM RST_SIM IO_SIM 002aag076 002aag077 Transparent top view Fig 2. Bump configuration for WLCSP12 Transparent top view Fig 3. Bump mapping for WLCSP12 6.1 Pin description Table 3. NVT4555 Product data sheet Pin description Symbol Pin Type Description EN C2 I Host controller driven enable pin. This pin should be HIGH (VCC) for normal operation, and LOW to activate a low current shutdown mode. CTRL B2 I VSIM voltage select pin. A LOW level selects VSIM = 1.8 V, while driving this pin to VCC selects VSIM = 2.95 V. VCC A3 power Supply voltage for the host controller side input/output pins (CLK_HOST, RST_HOST, IO_HOST). When VCC is below the UVLO threshold, the VSIM supply is disabled. This pin should be bypassed with a 0.1 F ceramic capacitor close to the pin. VBAT B3 power Battery voltage supply for internal LDO. This input voltage ranges from 2.5 V to 5.25 V. This pin should be bypassed with a 1.0 F ceramic capacitor close to the pin. VSIM C3 power SIM card supply voltage from internal LDO. The voltage at this pin can be selected for either 1.8 V (CTRL = 0) or 2.95 V (CTRL = 1). This pin should be bypassed with a 4.7 F ceramic capacitor close to the pin. IO_SIM D3 I/O SIM card bidirectional data input/output. The SIM card output must be on an open-drain driver. RST_SIM D2 O Reset output pin for the SIM card. GND A2 ground Ground for the SIM card and host controller. Proper grounding and bypassing are required to meet ESD specifications. CLK_SIM D1 O Clock output pin for the SIM card. CLK_HOST C1 I Clock input from host controller. RST_HOST B1 I Reset input from host controller. IO_HOST A1 I/O Host controller bidirectional data input/output. This output must be on an open-drain driver. All information provided in this document is subject to legal disclaimers. Rev. 2 — 24 May 2013 © NXP B.V. 2013. All rights reserved. 3 of 18 NVT4555 NXP Semiconductors SIM card interface level translator and supply voltage LDO 7. Functional description Refer to Figure 1 “Functional diagram”. 7.1 Function table Table 4. Function selection 0 = GND; 1 = VCC; X = don’t care. CTRL input EN input VSIM output voltage X 0 0V 0 1 1.8 V 1 1 2.95 V 7.2 Shutdown sequence of NVT4555 The ISO 7816-3 specification specifies the shutdown sequence for the SIM card signals to ensure that the card is properly disabled. Also during hot swap, the orderly shutdown of these signals helps to avoid any improper write and corruption of data. When the enable, EN, is asserted LOW, the shutdown sequence is initiated by powering down the RST_SIM channel. Once the RST_SIM channel is powered down, CLK_SIM, IO_SIM and VSIM are powered down sequentially one-by-one. An internal pull-down resistor on the SIM pins is used to pull these channels LOW. The shutdown sequence is completed in a few microseconds. It is important that EN is pulled LOW before VBAT and VCC supplies go LOW to ensure that the shutdown sequence is properly initiated. EN RST_SIM CLK_SIM IO_SIM ACTIVE DATA VSIM 002aag554 Fig 4. NVT4555 Product data sheet Shutdown sequence for RST_SIM, CLK_SIM, IO_SIM and VSIM of NVT4555 SIM card translator All information provided in this document is subject to legal disclaimers. Rev. 2 — 24 May 2013 © NXP B.V. 2013. All rights reserved. 4 of 18 NVT4555 NXP Semiconductors SIM card interface level translator and supply voltage LDO 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VESD Parameter Conditions electrostatic discharge voltage Min Max Unit SIM card side and VSIM pins; IEC 61000-4-2 [1] - 8 kV all other pins; IEC 61000-4-2 [1] - 2 kV all other pins; HBM [2] - 2 kV all other pins; CDM [3] - 500 V VCC supply voltage GND  0.5 3.6 V VBAT battery supply voltage GND  0.5 5.5 V VI(CLK_HOST) input voltage on pin CLK_HOST input signal voltage, HOST side GND  0.5 VCC + 0.5 V VI(RST_HOST) input voltage on pin RST_HOST input signal voltage, HOST side GND  0.5 VCC + 0.5 V VI(IO_HOST) input voltage on pin IO_HOST input signal voltage, HOST side GND  0.5 VCC + 0.5 V VI(CLK_SIM) input voltage on pin CLK_SIM input signal voltage, SIM side GND  0.5 VO(reg) + 0.5 V VI(RST_SIM) input voltage on pin RST_SIM input signal voltage, SIM side GND  0.5 VO(reg) + 0.5 V VI(IO_SIM) input voltage on pin IO_SIM input signal voltage, SIM side GND  0.5 VO(reg) + 0.5 V Tstg storage temperature 55 +125 C Tamb ambient temperature 40 +85 C [1] IEC 61000-4-2, level 4, contact discharge. [2] Human Body Model (HBM) according to JESD22-A-A114. [3] Charged-Device Model (CDM) according to JESD22-C101. 9. Characteristics Table 6. Supplies 2.5 V  VBAT  5.5 V; 1.1 V  VCC  3.6 V; Tamb = 40 C to +85 C; unless otherwise specified. Symbol Parameter VCC supply voltage ICC supply current VBAT battery supply voltage IBAT battery supply current Conditions Min Typ[1] Max Unit 1.1 - 3.6 V operating mode; fclk = 1 MHz - 5 10 A shutdown mode; EN = GND - - 1 A 2.5 - 5.25 V operating mode; IO_HOST = VCC; CLK_HOST = RST_HOST = GND - 20 30 A shutdown mode; EN = GND - - 1 A Vth(UVLO) undervoltage lockout threshold VCC rising; VBAT = 3.6 V voltage 0.7 - 1 V Vhys(UVLO) undervoltage lockout hysteresis voltage - 100 - mV [1] Typical values measured at 25 C. NVT4555 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 24 May 2013 © NXP B.V. 2013. All rights reserved. 5 of 18 NVT4555 NXP Semiconductors SIM card interface level translator and supply voltage LDO Table 7. Static characteristics 2.5 V  VBAT  5.5 V; 1.1 V  VCC  3.6 V; Tamb = 40 C to +85 C; unless otherwise specified. Min Typ[1] Max Unit 1.8 V  VCC  3.6 V 0.7  VCC - VCC + 0.2 V 1.1 V  VCC < 1.8 V 0.85  VCC - VCC + 0.2 V Symbol Parameter Conditions VIH HIGH-level input voltage EN/CTRL pin threshold VIL LOW-level input voltage EN/CTRL pin threshold 0.15 - 0.15  VCC V regulator output voltage VSIM pin; CTRL = EN = VCC; 3.1 V  VBAT  5.25 V; 0 mA  ISIM  50 mA 2.85 2.95 3.1 V VSIM pin; CTRL = 0 V; EN = VCC; 2.5 V  VBAT  5.25 V; 0 mA  ISIM  50 mA 1.7 1.8 1.9 V LDO VO(reg) Vdo dropout voltage IO = 50 mA; VBAT = 2.90 V - 100 150 mV IO(sc) short-circuit output current VSIM shorted to GND 90 135 170 mA tstartup start-up time VSIM = 1.8 V or 2.95 V; IO = 50 mA; Co = 1 F - - 400 s Tj(sd) shutdown junction temperature - 160 - C Tsd(hys) hysteresis of shutdown temperature - 20 - K Rpd pull-down resistance - 100 -  PSRR power supply rejection VBAT = 3.6 V; ISIM = 20 mA; ratio VSIM = 1.8 V or 2.95 V f = 1 kHz - 60 - dB f = 10 kHz - 50 - dB VSIM discharge; EN = GND; VBAT = 3.6 V; VCC = 1.2 V Level shifter VIH VIL RPU VOH HIGH-level input voltage LOW-level input voltage pull-up resistance HIGH-level output voltage NVT4555 Product data sheet IO_HOST, RST_HOST, CLK_HOST 1.8 V  VCC < 3.6 V [2] 0.7  VCC - VCC + 0.2 V 1.1 V  VCC < 1.8 V [2] 0.85  VCC - VCC + 0.2 V IO_SIM [2] 0.7  VO(reg) - VO(reg) + 0.2 V IO_HOST, RST_HOST, CLK_HOST [2] 0.15 - 0.15  VCC V IO_SIM [2] 0.15 - 0.15  VO(reg) V IO_SIM connected to VSIM [3] 4 6 8 k IO_HOST connected to VCC [3] 3.5 5 6.5 k RST_SIM, CLK_SIM; IOH = 1 mA [2] - 0.7  VO(reg) VO(reg) V IO_SIM; IOH = 10 A [2] - 0.7  VO(reg) VO(reg) V IO_HOST; IOH = 10 A [2] - 0.7  VCC V All information provided in this document is subject to legal disclaimers. Rev. 2 — 24 May 2013 VCC © NXP B.V. 2013. All rights reserved. 6 of 18 NVT4555 NXP Semiconductors SIM card interface level translator and supply voltage LDO Table 7. Static characteristics …continued 2.5 V  VBAT  5.5 V; 1.1 V  VCC  3.6 V; Tamb = 40 C to +85 C; unless otherwise specified. Symbol VOL Parameter LOW-level output voltage Rpd Min Typ[1] Max Unit RST_SIM, CLK_SIM; IOL = 1 mA [2] - 100 300 mV IO_SIM; IOL = 1 mA [2] - 100 300 mV IO_HOST; IOL = 1 mA [2] Conditions pull-down resistance CLK_HOST, RST_HOST; EN = 0 series resistance IO_SIM - 100 300 mV 70 100 130 k - 200 -  EMI filter Rs [2] - 200 -  CLK_SIM [2] - 200 -  IO_SIM [2] - 45 - pF - 45 - pF - 45 - pF RST_SIM input/output capacitance Cio RST_SIM [2] CLK_SIM [1] Typical values measured at 25 C. [2] VIL, VIH depend on the individual supply voltage per interface. [3] See Figure 8 for details. Table 8. Dynamic characteristics 2.5 V  VBAT  5.5 V; fclk = fio = 1 MHz; Tamb = 40 C to +85 C; unless otherwise specified. Refer to Figure 5. Symbol Parameter Conditions Min Typ Max Unit VCC = 1.8 V; CTRL = VCC (VSIM = 2.95 V); SIM card CL  30 pF; host CL  10 pF I/O channel; SIM card side to host side [1] - 8 15 ns all channels; host side to SIM card side [1] - 8 15 ns transition time [1] - - 10 ns output skew time [2] - 2 - ns I/O channel; SIM card side to host side [1] - 15 25 ns all channels; host side to SIM card side [1] - 15 25 ns transition time [1] - - 10 ns tsk(o) output skew time between channels; IO_SIM and CLK_SIM [2] - 2 - ns fclk clock frequency CLK_SIM - - 5 MHz propagation delay tPD tt tsk(o) between channels; IO_SIM and CLK_SIM VCC = 1.2 V; CTRL = VCC (VSIM = 1.8 V); SIM card CL  30 pF; host CL  10 pF propagation delay tPD tt [1] All dynamic measurements are done with a 50 pF load. Rise times are determined by internal pull-up resistors. [2] Skew between any two outputs of the same package switching in the same direction with the same CL. NVT4555 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 24 May 2013 © NXP B.V. 2013. All rights reserved. 7 of 18 NVT4555 NXP Semiconductors SIM card interface level translator and supply voltage LDO 9.1 Waveforms VI input VM GND tPHL output tPLH VOH 90 % VM 10 % tTHL tTLH VOL 002aag078 Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig 5. Data input to data output propagation delay times 10. Application information The application circuit for the NVT4555, which shows the typical interface with a SIM card, is shown in Figure 6. The Low-DropOut (LDO) regulator, internal to the NVT4555, is designed to supply the SIM card power with a high Power Supply Rejection Ratio (PSRR) at a very low drop-out voltage (VBAT  VO(reg)). The LDO regulator provides two levels of fixed voltage regulation at 1.8 V or 2.95 V, which are selected with the CTRL pin of the NVT4555. VCC (1.1 V to 3.6 V) VBAT (2.5 V to 5.25 V) 1 μF 100 nF LDO REGULATOR (1.8 V or 2.95 V; 50 mA max.) VSIM 4.7 μF HOST PROCESSOR NVT4555 RST_HOST CLK_HOST IO_HOST RST_SIM LEVEL TRANSLATOR SIM CARD CLK_SIM IO_SIM 002aag553 Fig 6. NVT4555 Product data sheet NVT4555 application circuit interfacing with typical SIM card All information provided in this document is subject to legal disclaimers. Rev. 2 — 24 May 2013 © NXP B.V. 2013. All rights reserved. 8 of 18 NVT4555 NXP Semiconductors SIM card interface level translator and supply voltage LDO 10.1 Input/output capacitor considerations It is recommended that a 1 F and 100 nF capacitors having low Equivalent Series Resistance (ESR) are used respectively at the battery (VBAT) and VCC input terminals of the NVT4555. X5R and X7R type multi-layer ceramic capacitors (MLCC) are preferred because they have minimal variation in value and ESR over temperature. The maximum ESR should be < 500 m(50 m typical). Also, a 4.7 F capacitor is recommended at the Low Dropout regulator (LDO) output terminal to ensure stability. X5R and X7R type are recommended for their minimal variation over temperature and low ESR over frequency which avoids stability issues at high frequencies. The maximum ESR should be < 1.0 . Furthermore, the decrease in capacitance with an increase in the bias voltage should be considered to optimize LDO stability. In addition, the trade-off in LDO stability versus the value and constraint in case size of the capacitor determined by the application must be considered. As output load capacitance decreases, the LDO stability becomes marginal. Given that a 4.7 F ceramic capacitor may drop by 80 % in capacitance depending on the effects of bias voltage and temperature, it is recommended to refer to the manufacturer’s characterization of a capacitor based on case size, bias voltage and type. Figure 7 is an example of how a 4.7 F capacitor is affected by the above parameters. 002aah650 20 ∆C/ C (%) 1206, 6.3 V −20 1206, 10 V 0805, 6.3 V 0603, 6.3 V −60 0805, 10 V 0603, 10 V 0402, 6.3 V −100 Fig 7. 0 2 4 6 8 VDC (V) 10 Variation of capacitance for a 4.7 F capacitor versus DC voltage, value, case size and type 10.2 Layout consideration The capacitors should be placed directly at the terminals and ground plane. Since the internal band gap regulator is the dominant noise source in a typical application, connections and routing of the ground is very important to improve and optimize noise performance, PSRR and transient response. It is recommended to design the PCB so that the VCC, VBAT and VSIM pins are bypassed with a capacitor with each ground returning to a common node at the GND pin of the NVT4555 such that ground loops are minimized. NVT4555 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 24 May 2013 © NXP B.V. 2013. All rights reserved. 9 of 18 NVT4555 NXP Semiconductors SIM card interface level translator and supply voltage LDO 10.3 Dropout voltage The NVT4555 uses a PMOS pass transistor to achieve a very low dropout voltage. When VBAT  VO(reg) (VSIM pin) is less than the dropout voltage, the PMOS transistor operates in the linear region and the input-to-output resistance is RDSon of the PMOS device. The dropout voltage, Vdo, will scale with the output current since the PMOS device behaves like a resistor in the input-to-output path. 10.4 Level translator stage The architecture of the NVT4555 I/O channel is shown in Figure 8. The device does not require an extra input signal to control the direction of data flow from host to SIM or from SIM to host. As a change of driving direction is just possible when both sides are in HIGH state, the control logic is recognizing the first falling edge granting it control about the other signal side. During a rising edge signal, the non-driving output is driven by a one-shot circuit to accelerate the rising edge. In case of a communication error or some other unforeseen incident that would drive both connected sides to be drivers at the same time, the internal logic automatically prevents stuck-at situation, so both I/Os will return to HIGH level once released from being driven LOW. The channels RST and CLK just contain single direction drivers without the holding mechanism of the I/O channel, as these are just driven from the host to the card side. VSIM side B supply RISING EDGE DETECT ONE SHOT pull-up IO_SIM DIRECTION CONTROL CIRCUITRY VCC side A supply pull-up ONE SHOT RISING EDGE DETECT IO_HOST 002aah743 Fig 8. Automatic direction control level translator for HIGH-level direction change interfaces NVT4555 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 24 May 2013 © NXP B.V. 2013. All rights reserved. 10 of 18 NVT4555 NXP Semiconductors SIM card interface level translator and supply voltage LDO 10.5 LDO block diagram The LDO’s block diagram is depicted in Figure 9. It contains a pull-down mechanism to avoid any uncontrolled voltage level at the VSIM pin in the disabled state. Furthermore, thermal protection as well as an overcurrent protection are integrated to disable the output in case of a permanent short that may result in excessive self-heating. VSIM VBAT EN R1 Vref GENERATOR CTRL THERMAL PROTECTION R2 OVERCURRENT PROTECTION GND Fig 9. NVT4555 Product data sheet 002aag079 LDO block diagram All information provided in this document is subject to legal disclaimers. Rev. 2 — 24 May 2013 © NXP B.V. 2013. All rights reserved. 11 of 18 NVT4555 NXP Semiconductors SIM card interface level translator and supply voltage LDO 11. Package outline :/&63ZDIHUOHYHOFKLSVFDOHSDFNDJHEDOOV[[PP $ ( 1978. % $ EDOO$ LQGH[DUHD $ $ ' GHWDLO; H H & ‘Y ‘Z E & $ % & \ =( ' H & H H % $ =( EDOO$ LQGH[DUHD  ='   ; ='  PP VFDOH 'LPHQVLRQVPPDUHWKHRULJLQDOGLPHQVLRQV 8QLW PP $ PD[  QRP  PLQ  $ $ E          ' (       H H   H  Y  Z  =( =(              \ =' =' ZOFVSBQYWXNBSR 2XWOLQH YHUVLRQ 5HIHUHQFHV ,(& -('(& -(,7$ (XURSHDQ SURMHFWLRQ ,VVXHGDWH   1978. Fig 10. Package outline NVT4555UK (WLCSP12) NVT4555 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 24 May 2013 © NXP B.V. 2013. All rights reserved. 12 of 18 NVT4555 NXP Semiconductors SIM card interface level translator and supply voltage LDO 12. Soldering of WLCSP packages 12.1 Introduction to soldering WLCSP packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering WLCSP (Wafer Level Chip-Size Packages) can be found in application note AN10439 “Wafer Level Chip Scale Package” and in application note AN10365 “Surface mount reflow soldering description”. Wave soldering is not suitable for this package. All NXP WLCSP packages are lead-free. 12.2 Board mounting Board mounting of a WLCSP requires several steps: 1. Solder paste printing on the PCB 2. Component placement with a pick and place machine 3. The reflow soldering itself 12.3 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 11) than a PbSn process, thus reducing the process window • Solder paste printing issues, such as smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature), and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic) while being low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 9. Table 9. Lead-free process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 11. NVT4555 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 24 May 2013 © NXP B.V. 2013. All rights reserved. 13 of 18 NVT4555 NXP Semiconductors SIM card interface level translator and supply voltage LDO maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 11. Temperature profiles for large and small components For further information on temperature profiles, refer to application note AN10365 “Surface mount reflow soldering description”. 12.3.1 Stand off The stand off between the substrate and the chip is determined by: • The amount of printed solder on the substrate • The size of the solder land on the substrate • The bump height on the chip The higher the stand off, the better the stresses are released due to TEC (Thermal Expansion Coefficient) differences between substrate and chip. 12.3.2 Quality of solder joint A flip-chip joint is considered to be a good joint when the entire solder land has been wetted by the solder from the bump. The surface of the joint should be smooth and the shape symmetrical. The soldered joints on a chip should be uniform. Voids in the bumps after reflow can occur during the reflow process in bumps with high ratio of bump diameter to bump height, i.e. low bumps with large diameter. No failures have been found to be related to these voids. Solder joint inspection after reflow can be done with X-ray to monitor defects such as bridging, open circuits and voids. 12.3.3 Rework In general, rework is not recommended. By rework we mean the process of removing the chip from the substrate and replacing it with a new chip. If a chip is removed from the substrate, most solder balls of the chip will be damaged. In that case it is recommended not to re-use the chip again. NVT4555 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 24 May 2013 © NXP B.V. 2013. All rights reserved. 14 of 18 NVT4555 NXP Semiconductors SIM card interface level translator and supply voltage LDO Device removal can be done when the substrate is heated until it is certain that all solder joints are molten. The chip can then be carefully removed from the substrate without damaging the tracks and solder lands on the substrate. Removing the device must be done using plastic tweezers, because metal tweezers can damage the silicon. The surface of the substrate should be carefully cleaned and all solder and flux residues and/or underfill removed. When a new chip is placed on the substrate, use the flux process instead of solder on the solder lands. Apply flux on the bumps at the chip side as well as on the solder pads on the substrate. Place and align the new chip while viewing with a microscope. To reflow the solder, use the solder profile shown in application note AN10365 “Surface mount reflow soldering description”. 12.3.4 Cleaning Cleaning can be done after reflow soldering. 13. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged-Device Model DP Dry Pack ESD ElectroStatic Discharge ESR Equivalent Series Resistance HBM Human Body Model I/O Input/Output LDO Low DropOut regulator PCB Printed-Circuit Board PMOS Positive-channel Metal-Oxide Semiconductor SIM Subscriber Identification Module 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes NVT4555 v.2 20130524 Product data sheet - NVT4555 v.1 Modifications: • Table 3 “Pin description”: – – – – description for CTRL pin corrected from “VSIM = 3 V” to “VSIM = 2.95 V” description for VSIM pin corrected from “3 V (CTRL = 1)” to “2.95 V (CTRL = 1)” description for IO_HOST pin corrected from “open-drain configuration” to “open-drain driver” deleted 4 “n.c.” rows from table (correction) • • Table 4 “Function selection”: VSIM output voltage for selection “11” corrected from “3.0 V” to “2.95 V” • Figure 8 “Automatic direction control level translator for HIGH-level direction change interfaces”: Figure 6 “NVT4555 application circuit interfacing with typical SIM card” supply voltage corrected from “VCC (1.1 V to 3.0 V)” to “VCC (1.1 V to 3.6 V)” – corrected connection for 2 (P-type channel) transistors – corrected signal name from “IO_HOST/EN” to “IO_HOST” NVT4555 v.1 NVT4555 Product data sheet 20130501 Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 2 — 24 May 2013 © NXP B.V. 2013. All rights reserved. 15 of 18 NVT4555 NXP Semiconductors SIM card interface level translator and supply voltage LDO 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 15.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. NVT4555 Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 2 — 24 May 2013 © NXP B.V. 2013. All rights reserved. 16 of 18 NVT4555 NXP Semiconductors SIM card interface level translator and supply voltage LDO Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com NVT4555 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 24 May 2013 © NXP B.V. 2013. All rights reserved. 17 of 18 NVT4555 NXP Semiconductors SIM card interface level translator and supply voltage LDO 17. Contents 1 2 3 4 4.1 5 6 6.1 7 7.1 7.2 8 9 9.1 10 10.1 10.2 10.3 10.4 10.5 11 12 12.1 12.2 12.3 12.3.1 12.3.2 12.3.3 12.3.4 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Shutdown sequence of NVT4555 . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Application information. . . . . . . . . . . . . . . . . . . 8 Input/output capacitor considerations . . . . . . . . 9 Layout consideration . . . . . . . . . . . . . . . . . . . . 9 Dropout voltage . . . . . . . . . . . . . . . . . . . . . . . 10 Level translator stage . . . . . . . . . . . . . . . . . . . 10 LDO block diagram . . . . . . . . . . . . . . . . . . . . . 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Soldering of WLCSP packages. . . . . . . . . . . . 13 Introduction to soldering WLCSP packages . . 13 Board mounting . . . . . . . . . . . . . . . . . . . . . . . 13 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 13 Stand off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Quality of solder joint . . . . . . . . . . . . . . . . . . . 14 Rework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Cleaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information. . . . . . . . . . . . . . . . . . . . . 17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2013. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 24 May 2013 Document identifier: NVT4555