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NX3L4053PW-Q100J

NX3L4053PW-Q100J

  • 厂商:

    NXP(恩智浦)

  • 封装:

    TSSOP16

  • 描述:

    IC ANALOG SWITCH SPDT 16TSSOP

  • 数据手册
  • 价格&库存
NX3L4053PW-Q100J 数据手册
NX3L4053-Q100 Triple low-ohmic single-pole double-throw analog switch Rev. 1 — 18 April 2013 Product data sheet 1. General description The NX3L4053-Q100 is a triple low-ohmic single-pole double-throw analog switch, suitable for use as an analog or digital multiplexer/demultiplexer. Each switch has a digital select input (nS), two independent inputs/outputs (nY0 and nY1) and a common input/output (nZ). All three switches share an enable input (E). A digital enable pin E is common to all switches. When E is HIGH, the switches are turned off. Schmitt trigger action at the digital inputs makes the circuit tolerant to slower input rise and fall times. Low threshold digital inputs allow this device to be driven by 1.8 V logic levels in 3.3 V applications without significant increase in supply current ICC. This makes it possible for the NX3L4053-Q100 to switch 4.3 V signals with a 1.8 V digital controller, eliminating the need for logic level translation. The NX3L4053-Q100 allows signals with amplitude up to VCC to be transmitted from nZ to nY0 or nY1; or from nY0 or nY1 to nZ. Its low ON resistance (0.5 ) and flatness (0.13 ) ensures minimal attenuation and distortion of transmitted signals. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits  Automotive product qualification in accordance with AEC-Q100 (Grade 1)  Specified from 40 C to +85 C and from 40 C to +125 C  Wide supply voltage range from 1.4 V to 4.3 V  Very low ON resistance (peak):  1.8  (typical) at VCC = 1.4 V  1.0  (typical) at VCC = 1.65 V  0.6  (typical) at VCC = 2.3 V  0.6  (typical) at VCC = 2.7 V 0.5  (typical) at VCC = 4.3 V  Break-before-make switching  High noise immunity  ESD protection:  MIL-STD-883, method 3015 Class 3A exceeds 4000 V  HBM JESD22-A114F Class 3A exceeds 4000 V  MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )  CDM AEC-Q100-011 revision B exceeds 1000 V  IEC61000-4-2 contact discharge exceeds 6000 V for switch ports  CMOS low-power consumption  Latch-up performance exceeds 100 mA per JESD 78 Class II Level A NX3L4053-Q100 NXP Semiconductors Triple low-ohmic single-pole double-throw analog switch     1.8 V control logic at VCC = 3.6 V Control input accepts voltages above supply voltage Very low supply current, even when input is below VCC High current handling capability (350 mA continuous current under 3.3 V supply) 3. Applications       Cell phone PDA Portable media player Analog multiplexing and demultiplexing Digital multiplexing and demultiplexing Signal gating 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description 40 C to +125 C HXQFN16 plastic thermal enhanced extremely thin quad flat SOT1039-2 package; no leads; 16 terminals; body 3  3  0.5 mm NX3L4053PW-Q100 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; SOT403-1 body width 4.4 mm NX3L4053HR-Q100 Version 5. Marking Table 2. Marking codes Type number Marking code NX3L4053HR-Q100 M43 NX3L4053PW-Q100 X3L4053 NX3L4053_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 18 April 2013 © NXP B.V. 2013. All rights reserved. 2 of 22 NX3L4053-Q100 NXP Semiconductors Triple low-ohmic single-pole double-throw analog switch 6. Functional diagram VCC 16 13 1S 2S 11 1S 1Y0 12 10 2S 1Y1 13 9 3S 1Z 14 2Y0 2 2Y1 1 2Z 6 E 3S 1Y1 11 10 12 9 1Y0 14 1Z 1 DECODER LOGIC 2Y1 2 2Y0 15 3Y0 5 3Y1 3 3Z 15 2Z 3 4 3Y1 001aal735 E 5 6 3Y0 4 3Z 8 GND Pin numbers are shown for TSSOP16 package only. Fig 1. Logic symbol 001aal736 Pin numbers are shown for TSSOP16 package only. Fig 2. Logic diagram 7. Pinning information 7.1 Pinning         1;/4 $"% "&'       
NX3L4053PW-Q100J 价格&库存

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