TJA1102A
100BASE-T1 dual/single PHY for automotive Ethernet
Rev. 1 — 7 June 2021
1
Product data sheet
General description
The TJA1102A is a 100BASE-T1-compliant dual-port Ethernet PHY optimized for
automotive use cases such as gateways, IP camera links, radar modules, driver
assistance systems and back-bone networks. The device provides 100 Mbit/s transmit
and receive capability over two unshielded twisted-pair cables, supporting a cable length
of up to at least 15 m. The TJA1102A has been designed for automotive robustness,
while minimizing power consumption and system costs. For added flexibility, a single
PHY version is available (TJA1102AS) in which one of the PHYs is disabled. Unless
otherwise specified, all references in this document to TJA1102A encompass both the
dual- and single-PHY variants.
The TJA1102A supports OPEN Alliance TC-10-compliant sleep and wake-up request
forwarding, with an always-on power domain connected directly to the battery supply
without the need for a dedicated voltage regulator.
2
Features and benefits
2.1 General
•
•
•
•
Dual-port 100BASE-T1 PHY; single-port operation possible
Single-port variant available
MII- and RMII-compliant interfaces
HVQFN 56-pin package (8 × 8 mm)
2.2 Optimized for automotive use cases
•
•
•
•
•
•
•
•
•
•
•
•
Transmitter optimized for capacitive coupling to unshielded twisted-pair cable
Adaptive receive equalizer optimized for automotive cable length of up to at least 15 m
Enhanced integrated PAM-3 pulse shaping for low RF emissions
EMC-optimized output driver strength for MII and RMII
MDI pins meet class IV conducted emission limit as per OPEN Alliance EMC
Specification 2.0
MDI pins protected against ESD to ±6 kV HBM and ±6 kV IEC61000-4-2
MDI pins protected against transients in automotive environment
MDI pins do not need external filtering or ESD protection
Automotive-grade temperature range from -40 °C to +125 °C
Automotive product qualification in accordance with AEC-Q100
Host-configurable MDI polarity
Automated polarity detection and correction
TJA1102A
NXP Semiconductors
100BASE-T1 dual/single PHY for automotive Ethernet
2.3 Low-power mode
• OPEN Alliance TC-10-compliant sleep and wake-up forwarding
– Robust remote wake-up detection via bus lines
– Wake-up forwarding at PHY level (supporting global system wake-up)
• Inhibit output for voltage regulator control
• Dedicated PHY enable/disable input pin to minimize power consumption
• Local wake-up pin
• Wake-up via SMI-access
2.4 Diagnosis
• Signal Quality Indicator for real-time monitoring of link stability and transmitted data
quality
• Diagnosis of cable errors (shorts and opens)
• Gap-free supply undervoltage detection with fail-silent behavior
• Internal, external and remote loopback modes
2.5 Miscellaneous
•
•
•
•
•
3
Internal reverse MII mode for repeater operation
On-chip regulators to provide 3.3 V single-supply operation
Supports optional 1.8 V external supply for digital core
On-chip termination resistors for the differential cable pair
Jumbo frame support up to 16 kB
Ordering information
Table 1. Ordering information
Type number
TJA1102AHN
Package
[1]
Name
Description
Version
HVQFN56
plastic thermal enhanced very thin quad flat package; no leads; 56
terminals; body 8 × 8 × 0.85 mm
SOT684-13
[2]
TJA1102AHN/S
[1]
[2]
Dual PHY.
Single PHY.
4
Block diagram
A block diagram of the TJA1102A is shown in Figure 1. The 100BASE-T1 sections
contain the functional blocks specified in the 100BASE-T1 standard that make up the
Physical Coding Sublayer (PCS) and the Physical Medium Attachment (PMA) layer for
both the transmit and receive signal paths. The MII/RMII interface (including the Serial
Management Interface (SMI)) conforms to IEEE 802.3 clause 22.
Additional blocks are defined for mode control, register configuration, interrupt control,
system configuration, reset control, local wake-up, remote wake-up, undervoltage
detection and configuration control. A number of power-supply-related functional blocks
are defined: an internal 1.8 V regulator for the digital core, a Very Low Power (VLP)
supply for Sleep mode, the reset circuit, supply monitoring and inhibit control.
TJA1102A
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2 / 67
TJA1102A
NXP Semiconductors
100BASE-T1 dual/single PHY for automotive Ethernet
The clock signals needed for the operation of the PHY are generated in the PLL block,
derived from an external crystal or an oscillator input signal.
Pin strapping allows a number of default PHY settings (e.g. Master or Slave
configuration) to be hardware-configured at power-up.
P0_TXER
PMA
TRANSMITTER
PCS-TX
P0_TXEN
100BASE-T1
P0_VDDA(TX)
P0_VDDA(TX)
P0_TXD[3:0]
P0_TXC
P0_RXD[3:0]
RMII/MII
LOGIC
PHY0
FRONT-END/
HYBRID
PHY CONTROL
P0_RXDV/P0_CRSDV
P0_RXER
VDDD(1V8)
VDDD(3V3)
SEL_1V8
PMA
RECEIVER
PCS-RX
P0_RXC/P0_REF_CLK
LDO 1V8 DIG AND
1.8 V/3V3 UV DETECTION
1V8 SELECT
INT_N
INT_N CONTROL
MDC
MDIO
SMI
CONFIG[7:0]
CONFIG CONTROL
RST_N
RESET CONTROL
ACTIVITY
DETECT
PHY MODE
CONTROL
TOP MODE CONTROL
AND REGISTERS
BASIC CONTROL
BASIC STATUS
MODE CONTROL
CONFIGURATION
INTERRUPT SOURCE
INTERRUPT MASK
EXTENDED STATUS
1V2
reset
UV 3V3
DETECTION
VDD(IO)
VDD(IO)
VDD(IO)
VDD(IO)
UV 3V3
DETECTION
VDDA(3V3)
VLP/RESET/
UV VBAT
VBAT
INH
INH
CLK_IN_OUT
XO
P0_TRX_M
PLL
EN
XI
P0_TRX_P
WAKE_IN_OUT
XO-OSC/
CLOCK
ACTIVITY
DETECT
PHY MODE
CONTROL
VDDD_1V8
P1_TXER
PCS-TX
P1_TXEN
PMA
TRANSMITTER
P1_TXD[3:0]
P1_TXC
P1_RXD[3:0]
RMII/MII
LOGIC
PHY1
PHY CONTROL
100BASE-T1
FRONT-END/
HYBRID
P1_RXDV/P1_CRSDV
P1_RXER
P1_RXC/P1_REF_CLK
PCS-RX
PMA
RECEIVER
P1_VDDA(TX)
P1_VDDA(TX)
P1_TRX_P
P1_TRX_M
PLL
GND
aaa-022037
Figure 1. Block diagram (PHY1 is disabled in TJA1102AS)
TJA1102A
Product data sheet
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TJA1102A
NXP Semiconductors
100BASE-T1 dual/single PHY for automotive Ethernet
5
Pinning information
5.1 TJA1102A pinning
43 P1_TXD2
44 P1_TXD1
45 P1_TXD0
46 P1_TXER
48 VDDD(3V3)
47 VDDD(1V8)
49 GND
50 XI
51 XO
53 VDD(IO)
52 VDDA(3V3)
54 CLK_IN_OUT
terminal 1
index area
55 P0_RXER/CONFIG0/P1_TXCLK
56 P0_RXDV/P0_CRSDV/CONFIG4
The pin configuration of the TJA1102A dual PHY is shown in Figure 2. Separate interface
and supply pins are provided for each PHY block. The SMI is shared between the
two PHYs. Since 100BASE-T1 allows for full-duplex bidirectional communication, the
standard MII signals COL and CRS are not needed.
P0_RXD3/CONFIG5
1
42 P1_TXD3
P0_RXD2/CONFIG6
2
41 P1_TXEN
P0_RXD1/CONFIG7
3
40 P1_TXC
P0_RXD0
4
39 VDD(IO)
P0_RXC/P0_REF_CLK
5
38 P1_RXC/P1_REF_CLK
VDD(IO)
6
37 P1_RXD0/PHYAD3
P0_TXC
7
P0_TXEN
8
P0_TXD3
9
36 P1_RXD1/PHYAD2
TJA1102A
35 P1_RXD2/PHYAD1
34 P1_RXD3/CONFIG3
P0_TXD2 10
33 P1_RXDV/P1_CRSDV/CONFIG2
P0_TXD1 11
32 P1_RXER/CONFIG1/P0_TXCLK
P0_TXD0 12
31 VDD(IO)
P0_TXER 13
30 MDC
INT_N 28
EN 27
P1_TRX_P 25
P1_VDDA(TX) 26
P1_TRX_M 24
P1_VDDA(TX) 23
INH 22
VBAT 21
WAKE_IN_OUT 20
P0_VDDA(TX) 19
P0_TRX_M 18
P0_TRX_P 17
SEL_1V8 15
29 MDIO
P0_VDDA(TX) 16
RST_N 14
aaa-039085
Figure 2. Pin configuration: TJA1102A
Table 2. TJA102A pin description
[1]
Symbol
Pin
Type
P0_RXD3
1
O
P0 MII mode: receive data output, bit 3 of RXD[3:0] nibble
CONFIG5
1
I
pin strapping configuration input 5
P0_RXD2
2
O
P0 MII mode: receive data output, bit 2 of RXD[3:0] nibble
CONFIG6
2
I
pin strapping configuration input 6
TJA1102A
Product data sheet
Description
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Rev. 1 — 7 June 2021
© NXP B.V. 2021. All rights reserved.
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TJA1102A
NXP Semiconductors
100BASE-T1 dual/single PHY for automotive Ethernet
Table 2. TJA102A pin description...continued
[1]
Symbol
Pin
Type
P0_RXD1
3
O
P0 MII mode: receive data output, bit 1 of RXD[3:0] nibble
P0 RMII mode: receive data output, bit 1 of RXD[1:0] nibble
CONFIG7
3
I
pin strapping configuration input 7
P0_RXD0
4
O
P0 MII mode: receive data output, bit 0 of RXD[3:0] nibble
P0 RMII mode: receive data output, bit 0 of RXD[1:0] nibble
P0_RXC
5
I
P0 MII reverse mode: external 25 MHz clock input
O
P0 MII mode: 25 MHz receive clock output
I
P0 RMII mode: interface reference clock input (50 MHz external oscillator)
O
P0 RMII mode: interface reference clock output (25 MHz crystal at PHY or 25 MHz clock
at input of pin CLK_IN_OUT)
6
P
3.3 V digital I/O supply voltage
7
I
P0 MII reverse mode: external 25 MHz transmit clock input
O
P0 MII mode: 25 MHz transmit clock output
P0_REF_CLK
VDD(IO)
[2]
P0_TXC
5
Description
P0_TXEN
8
I
P0 MII/RMII mode: transmit enable input (active-HIGH, weak pull-down)
P0_TXD3
9
I
P0 MII mode: transmit data input, bit 3 of TXD[3:0] nibble (weak pull-down)
P0_TXD2
10
I
P0 MII mode: transmit data input, bit 2 of TXD[3:0] nibble (weak pull-down)
P0_TXD1
11
I
P0 MII mode: transmit data input, bit 1 of TXD[3:0] nibble (weak pull-down)
P0 RMII mode: transmit data input, bit 1 of TXD[1:0] nibble (weak pull-down)
P0_TXD0
12
I
P0 MII mode: transmit data input, bit 0 of TXD[3:0] nibble (weak pull-down)
P0 RMII mode: transmit data input, bit 0 of TXD[1:0] nibble (weak pull-down)
P0_TXER
13
I
P0 MII/RMII: transmit error input (weak pull-down)
RST_N
14
I
reset input (active-LOW; weak pull-up)
SEL_1V8
15
I
1.8 V LDO mode selection (external or internal; weak pull-down)
[3]
P0_VDDA(TX)
16
P
3.3 V analog supply voltage for the P0 transmitter
P0_TRX_P
17
AIO
+ terminal for P0 transmit/receive signal
P0_TRX_M
18
AIO
- terminal for P0 transmit/receive signal
[3]
P0_VDDA(TX)
19
P
3.3 V analog supply voltage for the P0 transmitter
WAKE_IN_OUT 20
AIO
local/forwarding wake-up input/output (configurable)
VBAT
21
P
battery supply voltage
INH
22
AO
inhibit output for voltage regulator control (VBAT-related, active-HIGH)
[4]
P1_VDDA(TX)
23
P
3.3 V analog supply voltage for the P1 transmitter
P1_TRX_M
24
AIO
- terminal for P1 transmit/receive signal
P1_TRX_P
25
AIO
+ terminal for P1 transmit/receive signal
[4]
P1_VDDA(TX)
26
P
3.3 V analog supply voltage for the P1 transmitter
EN
27
I
PHY enable input (active-HIGH, weak pull-down)
INT_N
28
O
interrupt output (active-LOW, open-drain output, level-based)
MDIO
29
IO
SMI data I/O (weak pull-up)
MDC
30
I
SMI clock input (weak pull-down)
TJA1102A
Product data sheet
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TJA1102A
NXP Semiconductors
100BASE-T1 dual/single PHY for automotive Ethernet
Table 2. TJA102A pin description...continued
[1]
Symbol
Pin
Type
[2]
VDD(IO)
31
P
3.3 V digital I/O supply voltage
P1_RXER
32
O
P1 MII/RMII receive error output
CONFIG1
32
I
pin strapping configuration input 1
P0_TXCLK
32
O
P0 transmit clock output in test mode and during slave jitter test
P1_RXDV
33
O
P1 MII receive data valid output
P1_CRSDV
33
O
P1 RMII carrier sense/receive data valid output
CONFIG2
33
I
pin strapping configuration input 2
P1_RXD3
34
O
P1 MII mode: receive data output, bit 3 of RXD[3:0] nibble
CONFIG3
34
I
pin strapping configuration input 3
P1_RXD2
35
O
P1 MII mode: receive data output, bit 2 of RXD[3:0] nibble
PHYAD1
35
I
pin strapping configuration input for bit 1 of the PHY address used for the SMI address/
Cipher scrambler
P1_RXD1
36
O
P1 MII mode: receive data output, bit 1 of RXD[3:0] nibble
P1 RMII mode: receive data output, bit 1 of RXD[1:0] nibble
PHYAD2
36
I
pin strapping configuration input for bit 2 of the PHY address used for the SMI address/
Cipher scrambler
P1_RXD0
37
O
P1 MII mode: receive data output, bit 0 of RXD[3:0] nibble
P1 RMII mode: receive data output, bit 0 of RXD[1:0] nibble
PHYAD3
37
I
pin strapping configuration input for bit 3 of the PHY address used for the SMI address/
Cipher scrambler
P1_RXC
38
I
P1 MII reverse mode: external 25 MHz clock input
O
P1 MII mode: 25 MHz receive clock output
I
P1 RMII mode: interface reference clock input (50 MHz external oscillator)
O
P1 RMII mode: interface reference clock output (25 MHz crystal at PHY or 25 MHz clock
at input of pin CLK_IN_OUT)
P1_REF_CLK
38
Description
VDD(IO)
[2]
39
P
3.3 V digital I/O supply voltage
P1_TXC
40
I
P1 MII reverse mode: external 25 MHz transmit clock input
O
P1 MII mode: 25 MHz transmit clock output
P1_TXEN
41
I
P1 MII/RMII mode: transmit enable input (active-HIGH, weak pull-down)
P1_TXD3
42
I
P1 MII mode: transmit data input, bit 3 of TXD[3:0] nibble (weak pull-down)
P1_TXD2
43
I
P1 MII mode: transmit data input, bit 2 of TXD[3:0] nibble (weak pull-down)
P1_TXD1
44
I
P1 MII mode: transmit data input, bit 1 of TXD[3:0] nibble (weak pull-down)
P1 RMII mode: transmit data input, bit 1 of TXD[1:0] nibble (weak pull-down)
P1_TXD0
45
I
P1 MII mode: transmit data input, bit 0 of TXD[3:0] nibble (weak pull-down)
P1 RMII mode: transmit data input, bit 0 of TXD[1:0] nibble (weak pull-down)
P1_TXER
46
I
P1 MII/RMII: transmit error input (weak pull-down)
VDDD(1V8)
47
P
1.8 V digital supply voltage (configurable internal or external supply)
VDDD(3V3)
48
P
3.3 V digital supply voltage
49
G
ground reference
GND
[5]
TJA1102A
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TJA1102A
NXP Semiconductors
100BASE-T1 dual/single PHY for automotive Ethernet
Table 2. TJA102A pin description...continued
[1]
Symbol
Pin
Type
XI
50
AI
crystal input - used in all MII/RMII and Reverse MII modes when a 25 MHz crystal is
used
XO
51
AO
crystal feedback - used in all MII/RMII and reverse MII modes when a 25 MHz crystal is
used
VDDA(3V3)
52
P
3.3 V analog supply voltage
[2]
VDD(IO)
53
P
3.3 V digital I/O supply voltage
CLK_IN_OUT
54
IO
25 MHz reference clock input/output (configurable)
P0_RXER
55
O
P0 MII/RMII receive error output
CONFIG0
55
I
pin strapping configuration input 0
P1_TXCLK
55
O
P1 transmit clock output in test mode and during slave jitter test
P0_RXDV
56
O
P0 MII receive data valid output
P0_CRSDV
56
O
P0 RMII carrier sense/receive data valid output
CONFIG4
56
I
pin strapping configuration input 4
[1]
[2]
[3]
[4]
[5]
Description
AIO: analog input/output; AO: analog output; AI: analog input; I: digital input (VDD(IO) related);
O: digital output (VDD(IO) related); IO: digital input/output (VDD(IO) related); P: power supply; G: ground.
VDD(IO) pins are connected internally and should be connected together on the PCB (pins 6, 31, 39 and 53).
P0_VDDA(TX) pins are connected internally and should be connected together on the PCB (pins 16 and 19).
P1_VDDA(TX) pins are connected internally and should be connected together on the PCB (pins 23 and 26).
HVQFN56 package die supply ground is connected to both the GND pin and the exposed center pad. The GND pin must be soldered to board ground.
For enhanced thermal and electrical performance, it is also recommended to connect the exposed center pad to board ground.
TJA1102A
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TJA1102A
NXP Semiconductors
100BASE-T1 dual/single PHY for automotive Ethernet
5.2 TJA1102AS pinning
43 n.c.
44 n.c.
45 n.c.
46 n.c.
47 VDDD(1V8)
49 GND
48 VDDD(3V3)
50 XI
51 XO
52 VDDA(3V3)
54 CLK_IN_OUT
53 VDD(IO)
terminal 1
index area
55 P0_RXER/CONFIG0
56 P0_RXDV/P0_CRSDV/CONFIG4
The pin configuration of the TJA1102AS single PHY is shown in Figure 3.
P0_RXD3/CONFIG5
1
42 n.c.
P0_RXD2/CONFIG6
2
41 n.c.
P0_RXD1/CONFIG7
3
40 n.c.
P0_RXD0
4
39 VDD(IO)
P0_RXC/P0_REF_CLK
5
38 n.c.
VDD(IO)
6
37 PHYAD3
P0_TXC
7
P0_TXEN
8
P0_TXD3
9
34 CONFIG3
P0_TXD2 10
33 CONFIG2
P0_TXD1 11
32 CONFIG1/P0_TXCLK
P0_TXD0 12
31 VDD(IO)
P0_TXER 13
30 MDC
RST_N 14
29 MDIO
36 PHYAD2
INT_N 28
EN 27
n.c. 25
P0_VDDA(TX) 26
35 PHYAD1
n.c. 24
P0_VDDA(TX) 23
INH 22
WAKE_IN_OUT 20
VBAT 21
P0_TRX_M 18
P0_VDDA(TX) 19
P0_TRX_P 17
SEL_1V8 15
P0_VDDA(TX) 16
TJA1102AS
aaa-039094
Figure 3. Pin configuration: TJA1102AS
Table 3. TJA1102AS pin description
[1]
Symbol
Pin
Type
P0_RXD3
1
O
P0 MII mode: receive data output, bit 3 of RXD[3:0] nibble
CONFIG5
1
I
pin strapping configuration input 5
P0_RXD2
2
O
P0 MII mode: receive data output, bit 2 of RXD[3:0] nibble
CONFIG6
2
I
pin strapping configuration input 6
P0_RXD1
3
O
P0 MII mode: receive data output, bit 1 of RXD[3:0] nibble
P0 RMII mode: receive data output, bit 1 of RXD[1:0] nibble
CONFIG7
3
I
pin strapping configuration input 7
P0_RXD0
4
O
P0 MII mode: receive data output, bit 0 of RXD[3:0] nibble
P0 RMII mode: receive data output, bit 0 of RXD[1:0] nibble
TJA1102A
Product data sheet
Description
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Rev. 1 — 7 June 2021
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TJA1102A
NXP Semiconductors
100BASE-T1 dual/single PHY for automotive Ethernet
Table 3. TJA1102AS pin description...continued
[1]
Symbol
Pin
Type
P0_RXC
5
I
P0 MII reverse mode: external 25 MHz clock input
O
P0 MII mode: 25 MHz receive clock output
I
P0 RMII mode: interface reference clock input (50 MHz external oscillator)
O
P0 RMII mode: interface reference clock output (25 MHz crystal at PHY or 25 MHz clock
at input of pin CLK_IN_OUT)
P0_REF_CLK
5
Description
VDD(IO)
[2]
6
P
3.3 V digital I/O supply voltage
P0_TXC
7
I
P0 MII reverse mode: external 25 MHz transmit clock input
O
P0 MII mode: 25 MHz transmit clock output
P0_TXEN
8
I
P0 MII/RMII mode: transmit enable input (active-HIGH, weak pull-down)
P0_TXD3
9
I
P0 MII mode: transmit data input, bit 3 of TXD[3:0] nibble (weak pull-down)
P0_TXD2
10
I
P0 MII mode: transmit data input, bit 2 of TXD[3:0] nibble (weak pull-down)
P0_TXD1
11
I
P0 MII mode: transmit data input, bit 1 of TXD[3:0] nibble (weak pull-down)
P0 RMII mode: transmit data input, bit 1 of TXD[1:0] nibble (weak pull-down)
P0_TXD0
12
I
P0 MII mode: transmit data input, bit 0 of TXD[3:0] nibble (weak pull-down)
P0 RMII mode: transmit data input, bit 0 of TXD[1:0] nibble (weak pull-down)
P0_TXER
13
I
P0 MII/RMII: transmit error input (weak pull-down)
RST_N
14
I
reset input (active-LOW; weak pull-up)
SEL_1V8
15
I
1.8 V LDO mode selection (external or internal; weak pull-down)
[3]
P0_VDDA(TX)
16
P
3.3 V analog supply voltage for the P0 transmitter
P0_TRX_P
17
AIO
+ terminal for P0 transmit/receive signal
P0_TRX_M
18
AIO
- terminal for P0 transmit/receive signal
[3]
P0_VDDA(TX)
19
P
3.3 V analog supply voltage for the P0 transmitter
WAKE_IN_OUT 20
AIO
local/forwarding wake-up input/output (configurable)
VBAT
21
P
battery supply voltage
INH
22
AO
inhibit output for voltage regulator control (VBAT-related, active-HIGH)
[3]
P0_VDDA(TX)
23
P
3.3 V analog supply voltage for the P0 transmitter
n.c.
24
-
not connected; pin can be left open or shorted to GND
n.c.
25
-
not connected; pin can be left open or shorted to GND
[3]
P0_VDDA(TX)
26
P
3.3 V analog supply voltage for the P0
EN
27
I
PHY enable input (active-HIGH, weak pull-down)
INT_N
28
O
interrupt output (active-LOW, open-drain output, level-based)
MDIO
29
IO
SMI data I/O (weak pull-up)
MDC
30
I
SMI clock input (weak pull-down)
[2]
VDD(IO)
31
P
3.3 V digital I/O supply voltage
CONFIG1
32
I
pin strapping configuration input 1
P0_TXCLK
32
O
P0 transmit clock output in test mode and during slave jitter test
CONFIG2
33
I
pin strapping configuration input 2
TJA1102A
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TJA1102A
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100BASE-T1 dual/single PHY for automotive Ethernet
Table 3. TJA1102AS pin description...continued
[1]
Symbol
Pin
Type
CONFIG3
34
I
pin strapping configuration input 3
PHYAD1
35
I
pin strapping configuration input for bit 1 of the PHY address used for the SMI address/
Cipher scrambler
PHYAD2
36
I
pin strapping configuration input for bit 2 of the PHY address used for the SMI address/
Cipher scrambler
PHYAD3
37
I
pin strapping configuration input for bit 3 of the PHY address used for the SMI address/
Cipher scrambler
n.c.
38
-
not connected; pin can be left open or shorted to GND
[2]
VDD(IO)
39
P
3.3 V digital I/O supply voltage
n.c.
40
-
not connected; pin can be left open or shorted to GND
n.c.
41
-
not connected; pin can be left open or shorted to GND
n.c.
42
-
not connected; pin can be left open or shorted to GND
n.c.
43
-
not connected; pin can be left open or shorted to GND
n.c.
44
-
not connected; pin can be left open or shorted to GND
n.c.
45
-
not connected; pin can be left open or shorted to GND
n.c.
46
-
not connected; pin can be left open or shorted to GND
VDDD(1V8)
47
P
1.8 V digital supply voltage (configurable internal or external supply)
VDDD(3V3)
48
P
3.3 V digital supply voltage
49
G
ground reference
XI
50
AI
crystal input - used in all MII/RMII and Reverse MII modes when a 25 MHz crystal is
used
XO
51
AO
crystal feedback - used in all MII/RMII and reverse MII modes when a 25 MHz crystal is
used
VDDA(3V3)
52
P
3.3 V analog supply voltage
[2]
VDD(IO)
53
P
3.3 V digital I/O supply voltage
CLK_IN_OUT
54
IO
25 MHz reference clock input/output (configurable)
P0_RXER
55
O
P0 MII/RMII receive error output
CONFIG0
55
I
pin strapping configuration input 0
P0_RXDV
56
O
P0 MII receive data valid output
P0_CRSDV
56
O
P0 RMII carrier sense/receive data valid output
CONFIG4
56
I
pin strapping configuration input 4
GND
[1]
[2]
[3]
[4]
[4]
Description
AIO: analog input/output; AO: analog output; AI: analog input; I: digital input (VDD(IO) related);
O: digital output (VDD(IO) related); IO: digital input/output (VDD(IO) related); P: power supply; G: ground.
VDD(IO) pins are connected internally and should be connected together on the PCB (pins 6, 31, 39 and 53).
P0_VDDA(TX) pins are connected internally and should be connected together on the PCB (pins 16, 19, 23 and 26).
HVQFN56 package die supply ground is connected to both the GND pin and the exposed center pad. The GND pin must be soldered to board ground.
For enhanced thermal and electrical performance, it is also recommended to connect the exposed center pad to board ground.
TJA1102A
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TJA1102A
NXP Semiconductors
100BASE-T1 dual/single PHY for automotive Ethernet
6
Functional description
6.1 System configuration
The TJA1102A comprises two 100BASE-T1 compliant Ethernet PHYs, with 100 Mbit/s
transmit and receive capability over two unshielded twisted-pair cables. The TJA1102A
supports a cable length of up to at least 15 m, with a bit error rate of 1E-10 or less. It is
optimized for capacitive signal coupling to the twisted-pair lines. A common-mode choke
is typically inserted into the signal path to comply with automotive EMC requirements.
The TJA1102A is designed to provide a cost-optimized system solution for automotive
Ethernet links. It communicates with the Media Access Control (MAC) unit via the MII
or RMII interface. In combination with other devices (e.g. SJA1105 in Figure 4), it offers
a highly flexible 4-port switch solution, with two TJA1102A dual PHYs providing the
100BASE-T1 physical layer ports.
The TJA1102A can operate with a crystal or an external clock. The clock can be
forwarded to other PHYs (in the application diagram in Figure 4, the clock of one
TJA1102A is used as reference for a second TJA1102A). The clocking and power supply
schemes are independent of each other.
The TJA1102A can be powered via a single 3.3 V supply. An internal LDO generates the
required 1.8 V supply, requiring only the addition of a decoupling capacitor.
When the TJA1102A is used in a switch application with several PHY ports, it may be
more efficient to use an external SMPS to provide the 1.8 V supply. In this configuration,
the internal LDO is switched off to allow an external supply to be used.
The state of SEL_1V8 is captured and copied to bit LDO_MODE (see Table 12) when the
device is powered up. A bit value of 0 enables the internal 1.8 V LDO. If LDO_MODE =
1, the internal LDO is disabled and VDDD(1V8) must be supplied externally. The value of
LDO_MODE can be changed after power-up via register access.
Control and status information is exchanged with the host controller via the SMI interface.
The INH output can be used to switch off the external regulator when all ports are in
Sleep mode.
Note that the dual-port PHY can be configured to operate as a single PHY via pin
strapping or the SMI. Alternatively, a TJA1102AS could be used when only a single PHY
is needed.
A PCB layout based on the system diagrams shown in Section 6.1.1 and Section 6.1.2
would be able to accommodate any switch configuration comprising between one and
four ports.
TJA1102A
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TJA1102A
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100BASE-T1 dual/single PHY for automotive Ethernet
6.1.1 Clocking scheme with MII and clock provided by the switch and one of the
TJA1102A devices
switch supply
VBAT
VREG
1V8 (opt.)
3V3
CLK_IN_OUT
1V8
MDC
MDIO
SJA1105
MII (2x)
P0
EN
RST_N
INT_N1
DUAL PHY
TJA1102A
P1
MDC
MDIO
25 MHz
±100 ppm
SPI
XO
EN
RST_N
INT_N0
INT_N1
XI
(R)(G)MII
CON
MDC
MDIO
CON
XI
EN
RST_N
INT_N0
TJA1102A
3V3
P1
INH
CON
XO
MII (2x)
DUAL PHY
VBAT
P0
WAKE_IN_OUT
CON
INH
VBAT
25 MHz
±100 ppm
HOST CONTROLLER
aaa-039095
One of the TJA1102A devices could be replaced by a TJA1102AS if only three PHYs are needed.
Figure 4. Typical TJA1102A MII switch application with SJA1105
TJA1102A
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TJA1102A
NXP Semiconductors
100BASE-T1 dual/single PHY for automotive Ethernet
6.1.2 Clocking scheme with RMII and clock provided by the switch
switch supply
VBAT
VREG
1V8 (opt.)
3V3
MDC
MDIO
REF_CLK (50 MHz)
1V8
REF_CLK (50 MHz)
P0
EN
RST_N
INT_N1
DUAL PHY
TJA1102A
MDC
MDIO
SPI
(R)(G)MII
P1
EN
RST_N
INT_N0
INT_N1
CON
SJA1105
RMII (2x)
MDC
MDIO
CON
XI
EN
RST_N
INT_N0
TJA1102A
3V3
P1
INH
CON
XO
RMII (2x)
DUAL PHY
VBAT
P0
WAKE_IN_OUT
CON
INH
VBAT
25 MHz
±100 ppm
HOST CONTROLLER
aaa-039096
One of the TJA1102A devices could be replaced by a TJA1102AS if only three PHYs are needed.
Figure 5. Typical RMII switch application with SJA1105 (XTAL at SJA1105)
6.2 MII and RMII
The TJA1102A supports a number of MII modes that can be selected via pin strapping
or the SMI. The PHYs should be configured to operate in the same mode, with common
clocking. The following modes are supported:
• MII
• RMII (25 MHz XTAL or external 50 MHz via REF_CLK)
• Reverse MII (connected externally or internally to the second PHY)
Refer to the SMI register description (Section 6.11) for further configuration options.
The strength of the (R)MII output driver signals can be limited in all modes (via bit
MII_DRIVER; Table 22) to optimize EMC behavior.
TJA1102A
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TJA1102A
NXP Semiconductors
100BASE-T1 dual/single PHY for automotive Ethernet
6.2.1 MII
The connections between the PHY and the MAC are shown in more detail in Figure 6.
Data is exchanged via 4-bit wide data nibbles on TXD[3:0] and RXD[3:0]. Transmit and
receive data is synchronized with the transmit (TXC) and receive (RXC) clocks. Both
clock signals are provided by the PHY and are typically derived from an external clock or
crystal running at a nominal frequency of 25 MHz (±100 ppm). Normal data transmission
is initiated with a HIGH level on TXEN, while a HIGH level on RXDV indicates normal
data reception.
MII encoding is described in Table 4 and Table 5.
RXC
RXER
RXDV
PHY
RXC
RXER
RXDV
RXD[3:0]
RXD[3:0]
TXEN
TXD[3:0]
TXER
TXC
TXEN
TXD[3:0]
TXER
TXC
RXC
RXER
RXDV
MAC/
SWITCH
PHY
CLK_IN_OUT
XO
XI
25 MHz
RXC
RXER
RXDV
RXD[3:0]
RXD[3:0]
TXEN
TXD[3:0]
TXER
TXC
TXEN
TXD[3:0]
TXER
TXC
MAC/
SWITCH
CLK_IN_OUT
25 MHz clock to
other PHY or
switch (optional)
XO
XI
aaa-022105
a. Using external XTAL showing optional 25 MHz clock
output
25 MHz clock from
other PHY or switch
aaa-022106
b. Using external reference clock
Figure 6. MII signaling
Table 4. MII encoding of TXD[3:0], TXEN and TXER
TXEN
TXER
TXD[3:0]
Indication
0
0
0000 through 1111
normal interframe
0
1
0000 through 1111
reserved
1
0
0000 through 1111
normal data transmission
1
1
0000 through 1111
transmit error propagation
Table 5. MII encoding of RXD[3:0], RXDV and RXER
TJA1102A
Product data sheet
RXDV
RXER
RXD[3:0]
Indication
0
0
0000 through 1111
normal interframe
0
1
0000
normal interframe
0
1
0001 through 1101
reserved
0
1
1110
false carrier indication
0
1
1111
reserved
1
0
0000 through 1111
normal data transmission
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TJA1102A
NXP Semiconductors
100BASE-T1 dual/single PHY for automotive Ethernet
Table 5. MII encoding of RXD[3:0], RXDV and RXER...continued
RXDV
RXER
RXD[3:0]
Indication
1
1
0000 through 1111
data reception with errors
6.2.2 RMII
6.2.2.1 Signaling and encoding
RMII data is exchanged via 2-bit wide data nibbles on TXD[1:0] and RXD[1:0], as
illustrated in Figure 7. To achieve the same data rate as MII, the interface is clocked at
a nominal frequency of 50 MHz. A single clock signal, REF_CLK, is provided for both
transmitted and received data. This clock signal is provided by the PHY and is typically
derived from an external 25 MHz (±100 ppm) crystal (see Figure 7 (a)). Alternatively, a
50 MHz clock signal (±50 ppm) generated by an external oscillator can be connected to
pin REF_CLK (see Figure 7 (b)). A third option is to connect a 25 MHz (±100 ppm) clock
signal generated by another PHY or switch to pin CLK_IN_OUT (see Figure 7 (c)).
RMII encoding is described in Table 6 and Table 7.
Table 6. RMII encoding of TXD[1:0], TXEN
TXEN
TXD[1:0]
Indication
0
00 through 11
normal interframe
1
00 through 11
normal data transmission
Table 7. RMII encoding of RXD[1:0], CRSDV and RXER
TJA1102A
Product data sheet
CRSDV
RXER
RXD[1:0]
Indication
0
0
00 through 11
normal interframe
0
1
00
normal interframe
0
1
01 through 11
reserved
1
0
00 through 11
normal data transmission
1
1
00 through 11
data reception with errors
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TJA1102A
NXP Semiconductors
100BASE-T1 dual/single PHY for automotive Ethernet
PHY
CRSDV
CRSDV
RXD[1:0]
RXER
RXD[1:0]
RXER
TXEN
TXD[1:0]
TXEN
TXD[1:0]
REF_CLK
MAC/
SWITCH
PHY
REF_CLK
CRSDV
CRSDV
RXD[1:0]
RXER
RXD[1:0]
RXER
TXEN
TXD[1:0]
TXEN
TXD[1:0]
MAC/
SWITCH
CLK_IN_OUT
XO
REF_CLK
XI
25 MHz
25 MHz clock to
other PHYs or
switch (optional)
XO
XI
50 MHz
oscillator
aaa-022189
a. Using external XTAL showing optional 25 MHz clock
output
PHY
CRSDV
CRSDV
RXD[1:0]
RXER
RXER
TXEN
TXEN
REF_CLK
aaa-022190
b. Using external reference clock
RXD[1:0]
TXD[1:0]
REF_CLK
TXD[1:0]
MAC/
SWITCH
REF_CLK
CLK_IN_OUT
XO
XI
25 MHz clock from
other PHY or switch
aaa-022191
c. Using externally generated 25 MHz reference clock
Figure 7. RMII signaling
6.2.3 Reverse MII
In Reverse MII mode, two PHYs are connected back-to-back via the MII interface to
realize a repeater function on the physical layer. The MII signals are cross-connected: RX
output signals from one PHY are connected to the TX inputs on the other PHY. The TXC
and RXC clock signals become inputs on the PHY connected in Reverse MII mode (P0 in
Figure 8 and Figure 9). Reverse MII mode is selected by setting bits MII_MODE = 11.
Two configuration options are available on the TJA1102A. The P0 and P1 MII pins can
be connected externally on the PCB (INT_REV_MII = 0). Alternatively, the MII ports
can communicate via existing internal connections (INT_REV_MII = 1), as illustrated in
Figure 8.
TJA1102A
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TJA1102A
NXP Semiconductors
100BASE-T1 dual/single PHY for automotive Ethernet
TJA1102A
PHY P1
IN MII
P1_TXC
MDI 100BaseT1
PHY P0
IN REVERSE MII
P0_RXC
P1_TXER
P0_RXER
P1_TXEN
P0_RXDV
P1_TXD[3:0]
P1_RXDV
P1_RXD[3:0]
P1_RXER
P1_RXC
MDI 100BaseT1
P0_RXD[3:0]
P0_TXEN
P0_TXD[3:0]
P0_TXER
P0_TXC
aaa-039097
Figure 8. 100BASE-T1 repeater with TJA1102A Reverse MII
The TJA1102AS can be configured in reverse MII mode by connecting the MII pins
externally to a fast Ethernet product, is illustrated in Figure 9.
TXC
TXER
TXEN
TXD[3:0]
MDI
Fast Ethernet
PHY 100Base-TX
RXDV
RXD[3:0]
RXER
RXC
XO
XI
25 MHz
XTAL
P0_RXC
P0_RXER
P0_RXDV
P0_RXD[3:0]
TJA1102AS
(Reverse MII)
P0_TXEN
P0_TXD[3:0]
P0_TXER
P0_TXC
XI
MDI
100Base-T1
XO
25 MHz
XTAL
aaa-039099
Figure 9. Fast Ethernet to 100BASE-T1 media converter with TJA1102AS in Reverse MII
6.3 System controller
6.3.1 Operating modes
6.3.1.1 Power-off mode
Each PHY has its own dedicated power mode state machine. The TJA1102A remains
in Power-off mode as long as the voltage on pin VBAT is below the power-on reset
threshold. The analog blocks are disabled and the digital blocks are in a passive reset
state in this mode.
6.3.1.2 Standby mode
At power-on, when the voltage on pin VBAT rises above the under-voltage recovery
threshold (Vuvr(VBAT)), the TJA1102A enters Standby mode and switches on the INH
control output (pin INH HIGH). This control signal may be used to activate the supply to
TJA1102A
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TJA1102A
NXP Semiconductors
100BASE-T1 dual/single PHY for automotive Ethernet
the microcontroller in the ECU. Once the 3.3 V supply voltage is available, the internal
1.8 V regulator is activated (if selected) and the PHYs are configured according to the pin
strapping implemented on the CONFIGn and PHYADn pins. No SMI access takes place
during the power-on settling time (ts(pon)).
From an operating point of view, Standby mode corresponds to the IEEE 802.3 Powerdown mode, where the transmit and receive functions (in the PHY) are disabled. Standby
mode also acts as a fail-silent mode. The TJA1102A switches to Standby mode when an
undervoltage condition is detected on VDDA(3V3), VDDD(3V3), VDDD(1V8) or VDD(IO).
6.3.1.3 Normal mode
To establish a communication link, the TJA1102A must be switched to Normal mode,
either autonomously (AUTO_OP = 1; see Table 31) or via an SMI command from the
host (AUTO_OP = 0).
When the TJA1102A is configured for autonomous operation, the PHYs enter Normal
mode automatically and activate the link on power-on. When the TJA1102A is hostcontrolled, the PHYs must be enabled via the SMI.
When a PHY is enabled and enters Normal mode, the internal PLL starts running and
the transmit and receive functions (both PCS and PMA) are enabled. After a period of
stabilization, tinit(PHY), the PHY is ready to set up a link.
If link control is enabled (LINK_CONTROL = 1; see Table 21), a PHY configured as
Master initiates the training sequence by transmitting an idle pattern. The receiver of
a PHY configured as Slave will attempt to synchronize with the idle pattern. Once the
descrambler is synchronized (SCR_LOCKED = 1), the slave PHY itself starts sending an
idle pattern using the recovered clock signal.
The link is established (LINK_STATUS = 1) when the TJA1102A PHY and the remote
PHY indicate that their local receiver status is OK.
6.3.1.4 Disable mode
When the Ethernet interface is not in use or must be disabled for fail-safe reasons, the
PHYs can be switched off by pulling pin EN LOW. The PHYs are switched off completely
in Disable mode, minimizing power consumption. The configuration register settings are
maintained. EN must be forced HIGH to exit Disable mode and activate the PHYs. The
PHYs can also be enabled/disabled via bit PHY_EN.
6.3.1.5 Sleep mode
If the network manager decides to withdraw a node from the network because it is no
longer needed, the PHYs can be switched to Sleep mode (powering down the entire
ECU).
In Sleep mode, the transmit and receive functions are switched off and no signal is driven
onto the twisted-pair lines. Transmit requests from the MII interface are ignored and the
MII output pins are in a high-ohmic state. The only valid SMI operations in Sleep mode
are reading the POWER_MODE status bits in the Extended control register and issuing a
Standby mode command (POWER_MODE = 1100; see Table 21).
Releasing the INH output (INH LOW) allows the ECU to switch off its main power supply
unit. Typically, the entire ECU is powered-down. The TJA1102A is kept partly alive by
the permanent battery supply and can still react to activity on the Ethernet lines. Once
valid Ethernet idle pulses longer than tdet(PHY) are detected on the lines of at least one
PHY (with REMWUPHY = 1), the TJA1102A wakes up in Standby mode and switches on
TJA1102A
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TJA1102A
NXP Semiconductors
100BASE-T1 dual/single PHY for automotive Ethernet
the main power unit via the INH control signal. The TJA1102A PHYs enter Normal mode
via autonomous operation once the supply voltages are stable within their operating
ranges, or can be switched to Normal mode via an SMI command if host-controlled. The
communication link to the partner can then be re-established. Only PHY0 switches to
Normal mode in the TJA1102AS.
Sleep mode can be entered from Normal mode via the intermediate Sleep Request
mode as well as from Standby mode, as shown in Figure 10. Note that the configuration
register settings are maintained in Sleep mode.
If CLK_IN_OUT is used to provide the clock for other devices (e.g. other PHYs), the clock
signal can be configured to remain active (CLK_HOLD = 1) along with INH even when
both PHYs are in Sleep mode or disabled. When CLK_HOLD = 1, the device enters
Sleep mode automatically but remains active until a FORCE_SLEEP SMI command is
received. Note that this command forces both PHYs to Sleep mode immediately (if they
are not already in Sleep mode or disabled).
6.3.1.6 Sleep Request mode
Sleep Request mode is an intermediate state used to initiate a transition to Sleep mode.
In Sleep Request mode, the PHY transmits scrambler code with an encoded LPS
command to inform the link partner about the request to enter Sleep mode.
The PHY sleep request timer (tto(req)sleep; see Table 38) starts when the TJA1102A
enters Sleep Request mode. This timer determines the maximum length of time the PHY
remains in Sleep Request mode. The PHY switches to Sleep mode (via an intermediate
step through Silent mode) on receiving LPS confirmation of the sleep request from the
Link partner. If the timer expires before confirmation is received from the link partner,
the PHY returns to Normal mode. This process is valid when LPS_ACTIVE = 1 and
SLEEP_CONFIRM = 1.
If bit SLEEP_ACK is not set when the PHY enters Sleep Request mode, it switches back
to Normal mode if data is detected on MII or MDI (see Table 22). The DATA_DET_WU
flag in the General status register is set and a WAKEUP interrupt is generated (if
REMWUPHY = 1).
If SLEEP_ACK is set when the PHY enters Sleep Request mode, the PHY sleep
acknowledge timer (tto(ack)sleep; see Table 38) is started. While the timer is running, the
PHY switches back to Normal mode in response to a host command or wake-up request.
When the timer expires, LPS transmission begins to initiate a transition to Sleep mode.
Data detected at MII or MDI is ignored.
INH is released when both PHYs are in Sleep mode or disabled.
6.3.1.7 Silent mode
Silent mode is an intermediate state between Sleep Request mode and Sleep mode.
It is provided to allow time to switch off the transmitter after a sleep request has been
accepted before entering Sleep mode. The TJA1102A switches to Sleep mode once the
channel goes silent.
If the channel remains active for longer than tto(req)sleep, the PHY returns to Normal mode
and a SLEEP_ABORT interrupt is generated.
TJA1102A
Product data sheet
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TJA1102A
NXP Semiconductors
100BASE-T1 dual/single PHY for automotive Ethernet
6.3.1.8 Reset mode
The TJA1102A switches to Reset mode from any mode except Power-off or Sleep when
pin RST_N is held LOW for at least tdet(rst)(max), provided the voltage on VDD(IO) is above
the undervoltage threshold.
When RST_N goes HIGH again, or an undervoltage is detected on VDD(IO), the
TJA1102A switches to Standby mode. All register bits are reset to their default values in
Reset mode and the state of the pin strapping pins is captured.
6.3.2 Status of functional blocks in TJA1102A operating modes
Table 8 presents an overview of the status of TJA1102A functional blocks in each
operating mode.
Table 8. Status of functional blocks in TJA1102A operating modes
Functional block
Sleep Request Sleep
[2]
[1]
Disable
on
high-ohmic
on
high-ohmic
high-ohmic
PMA/PCS-TX
on
off
on
off
off
PMA/PCS-RX
on
off
on
off
SMI
on
Activity detection
off
on/off
[4]
LDO_1V8
on/off
[6]
RST_N input
on
EN input
on
on
on
on
off
off
on/off
[6]
on
on
off
on/off
[4]
off
on/off
[6]
off
off
off
on
on
[7]
off
off
off
[7]
on
on
on
high-ohmic
high-ohmic
INH output
on
on
on
off
on/off
Temp detection
on
on
on
off
off
[7]
[8]
on/off
on
[7]
INT_N output
[3]
[4]
[5]
[6]
on/off
[5]
on/off
[2]
on/off
on
on
on
[7]
off
[3]
WAKE_IN_OUT
[1]
Product data sheet
Standby
MII
Crystal oscillator
TJA1102A
Normal
off
[8]
The TJA1102A only switches to Sleep mode if both PHYs are in Sleep mode or disabled via SMI-access (PHY_EN = 0).
The TJA1102AS will be in Sleep mode if PHY0 is in Sleep mode (since PHY1 is disabled).
Outputs RXD[3:0], RXER and RXDV are LOW in Standby mode; the other MII pins are configured as inputs via internal
100 kΩ pull-down resistors.
Limited access to SMI registers in Sleep mode to allow mode control/wake-up via SMI. VDD(IO) must be available.
Configurable; depends on bits CLK_MODE in the Common configuration register.
The crystal will be off in Sleep mode unless bit CLK_HOLD = 1 and bits CLK_MODE = 00 or 01.
Configurable; VDDD(1V8) can be supplied internally (bit LDO_MODE in the Common configuration register LOW) or
externally (bit LDO_MODE HIGH).
Configurable.
The behavior of the INH output in Disable mode is configurable and depends on bit CONFIG_INH in the Common
configuration register.
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6.4 Mode transitions
A mode transition diagram for the TJA1102A is shown in Figure 10. Abbreviations used in
the mode transition diagram are defined in Table 9.
The following events, listed in order of priority, trigger mode transitions:
•
•
•
•
•
•
Power on/off
Undervoltage on VDD(IO)
RST_N input
EN input
Overtemperature or Undervoltage on VDDA(3V3), VDDD(3V3), VDDD(1V8)
SMI command and wake-up (local, remote or forwarding)
Table 9. State diagram legend
Transition
Abbreviation
Description
Silent to Normal
sleep request timer expired
t > tto(req)sleep
Normal to Sleep Request
Sleep Request command
POWER_MODE = 1011
autonomous power-down
no frame transmission or reception for longer than
tto(pd)autn AND AUTO_PWD = 1
LPS code group received
LPS_WUR_DIS = 0 (LPS/WUR enabled) AND
LPS_RECEIVED = 1 AND t > tto(req)sleep AND
LPS_ACTIVE = 1
no data detected on MDI or MII
pcs_rx_dv = FALSE AND TXEN = LOW
sleep acknowledge timer enabled
SLEEP_ACK = 1
Normal mode command
POWER_MODE = 0011
wake-up request
(FWDPHYREM = 1 and WAKEUP = 1) OR WUR
symbols received at the bus pins
sleep acknowledge timer disabled
SLEEP_ACK = 0
sleep acknowledge time-out time not
expired
t < tto(ack)sleep
data detected on MDI or MII
pcs_rx_dv = TRUE OR TXEN = HIGH
LPS enabled
LPS_WUR_DIS = 0
sleep request timer expired
t > tto(req)sleep
data detected on MDI or MII
pcs_rx_dv = TRUE OR TXEN = HIGH
sleep acknowledge timer disabled
SLEEP_ACK = 0
LPS disabled
LPS_WUR_DIS = 1
sleep request timer expired
t > tto(req)sleep
Sleep Request to Silent
LPS enabled
LPS_WUR_DIS = 0
Standby to Normal
autonomous operation
see Section 6.6
Sleep Request to Normal
Normal to Normal
Sleep Request to Sleep
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sleep request timer expired (t > t to(req)sleep)
Sleep Request command AND
data detected at MDI or MII AND
sleep acknowledge timer disabled
[Sleep Request command OR
autonomous power-down OR
(LPS code group received AND
(no data detected on MDI or MII OR
sleep acknowledge timer enabled))]
AND
no WUR transmitted or received
SLEEP
REQUEST
NORMAL
INH = on
PHY enabled
INH = on
PHY enabled
[(Normal mode command OR wake-up request)
AND (sleep acknowledge timer disabled OR
sleep acknowledge timer not expired)]
OR
(data detected at MDI or MII AND
sleep acknowledge timer disabled)
OR
(LPS enabled AND sleep request timer expired)
Normal mode command OR
autonomous operation OR
(FWDPHYREM = 1 AND local wake-up)
LPS enabled AND
[LPS sent AND
(SLEEP_CONFIRM = 0 OR
(SLEEP_CONFIRM = 1
AND LPS received))
OR LOC_RCVR_STATUS = 0]
SILENT
Standby command
OR UV(1)
OR Overtemperature
INH = on
PHY enabled
(SEND_Z)
Standby command
OR UV(1)
OR Overtemperature
LPS disabled AND
sleep request timer
expired (3)
DISABLE
INH = on/off(2))
PHY disabled
EN pin HIGH OR
uv_VDD(IO)
STANDBY
Sleep Request command OR
t > t to(uvd)(4)
INH = on
PHY disabled
SLEEP
INH = off
PHY disabled
local wake-up OR
activity detected OR
Standby mode command
Power-on
(no uv_VBAT)
EN pin LOW AND
RST_N HIGH AND
no uv_VDD(IO)) AND
(Normal OR Standby OR Sleep_Request)
from any
state
Power-off
(uv_VBAT)
POWER-OFF
(INH = off)
no bus activity
(PHY_EN = 0 OR
FORCE_SLEEP = 1)
AND no UV
RST_N HIGH OR uv_VDD(IO)
RST_N LOW AND (no uv_VDD(IO))
from any state other than
Power-off or Sleep
RESET
(INH =
no change)
aaa-038965
1. UV means undervoltage on one of the power supply pins VDD(IO), VDDA(3V3), VDDD(1V8), VDDD(3V3).
2. INH can be configured to be on or off.
3. The PHY will not be in Sleep mode, and cannot be woken up, until the timeout associated with the transition has
expired (after tto(req)sleep).
4. At power-on, after a transition from Power-off to Standby mode, undervoltage detection timeout is enabled once all
supply voltages are available. When an undervoltage is detected, the TJA1102A switches to Sleep mode after tto(uvd).
Figure 10. Mode transition diagram
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6.5 Sleep and wake-up forwarding concept
The sleep and wake-up forwarding concept of the TJA1102A is compliant with the
OPEN Alliance Sleep/Wake-up specification. The TJA1102A features a wake-up request
forwarding function that enables fast wake-up forwarding without the need for a switch,
MAC or μC action. The wake-up forwarding principle is illustrated in Figure 11. The wakeup request can be forwarded via non-active (gray PHYs in the figure) or active links
(white PHY). In the case of a non-active link, a wake-up pulse (WUP; duration tw(wake))
is transmitted, to be detected as activity at the link partner. For an active link, wake up
request (WUR) scrambler code groups are sent.
The wake-up behavior of the PHYs can be configured individually. This arrangement
allows WAKE_IN_OUT to be used as a local wake-up or to have a mixed system with
only some ports forwarding wake-up requests. The following configuration options are
available and are selected via the SMI Configuration register 1 (Table 22):
REMWUPHY determines whether a PHY reacts to a remote wake-up request.
FWDPHYREM determines whether a PHY forwards a wake-up request (from another
port or via WAKE_IN_OUT) to its MDI. A WUP or WUR is sent, depending on the link
status.
LOCWUPHY determines whether a PHY should be woken up in response to a local
wake-up event (forwarded from another port or via WAKE_IN_OUT)
FWDPHYLOC determines whether wake-up event should be forwarded to other ports
(i.e. should the second PHY be informed and/or the WAKE_IN_OUT signal activated).
The WAKE_IN_OUT signal features a programmable timeout to enable it to support a
number of wake-up concepts (e.g. wake-up line). It reacts on a rising edge.
The wake-up detection time, tdet(wake) (see Table 38), on pin WAKE_IN_OUT is
determined by register bit settings LOC_WU_TIM (see Table 29). The wake-up pulse
duration (tp; see Table 38) is also determined by LOC_WU_TIM.
VBAT
1.2 V
INH
WUP pulses
PHY
µCONTROLLER
WUR codes
PHY
MACs +
SWITCH
WUP pulses
WAKE_IN_OUT
3.3 V
PHY
aaa-022042
Figure 11. Wake-up request forwarding
TJA1102A
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6.6 Autonomous operation
When the TJA1102A is configured for autonomous operation (either via pin strapping,
see Section 6.10, or via bit AUTO_OP in the Common configuration register, Table 29),
it can operate and establish a link without further interaction with a host controller. On
power-on or wake-up from Sleep mode, the TJA1102A goes directly to Normal mode
once all supply voltages are available and the link-up process starts automatically.
Host configuration (e.g. for link or mode control) will not be possible until the device is
switched from autonomous to managed operation by resetting bit AUTO_OP.
6.7 Autonomous power-down
If autonomous power-down is enabled for a PHY (AUTO_PWD = 1), it goes to Sleep
Request mode automatically if no Ethernet frames have been received at the MDI and
(R)MII within the timeout time, tto(pd)autn.
6.8 Test modes
Five test modes are supported. Only test modes 1, 2, 4 and 5 are included in the
100BASE-T1 specification [1]. The test modes can be selected individually via an SMI
command in Normal mode while link control is disabled. Pin P1_RXER is used as a
reference clock output for PHY0 test modes 1 to 4; pin P0_RXER is used as a reference
clock output for PHY1 test modes 1 to 4 (the nominal P1_RXER/P0_RXER function is
disabled when test modes are active). No load should be connected when the reference
clock is being measured.
6.8.1 Test mode 1
Test mode 1 is used to test transmitter droop. In Test mode 1, the PHY transmits ‘+1’
symbols for 600 ns followed by ‘-1’ symbols for a further 600 ns. This sequence is
repeated continuously.
6.8.2 Test mode 2
Test mode 2 is used to test transmitter timing jitter in Master mode. In Test mode 2, the
PHY transmits the data symbol sequence {+1, -1} repeatedly. The transmission of the
symbols is synchronized with the local external oscillator.
6.8.3 Test mode 3
Test mode 3 is used to test transmitter timing jitter in Slave mode. In Test mode 3, the
PHY transmits the data symbol sequence {+1, -1} repeatedly. The transmission of the
symbols is synchronized with the local external oscillator.
6.8.4 Test mode 4
Test mode 4 is used to test transmitter distortion. In Test mode 4, the PHY transmits the
sequence of symbols generated by the scrambler polynomial gs1 = 1 + x9 + x11.
The bit sequence x0n, x1n is derived from the scrambler according to the following
equations:
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This stream of 3-bit nibbles is mapped to a stream of ternary symbols according to
Table 10.
Table 10. Symbol mapping in test mode 4
x1n
x0n
PAM-3 transmit symbol
0
0
0
0
1
+1
1
0
0
1
1
-1
6.8.5 Test mode 5
Test mode 5 is used to test the transmit PSD mask. In Test mode 5, the PHY transmits a
random sequence of PAM-3 symbols.
6.8.6 Slave jitter test
To enable the Slave jitter test in Normal mode, bit SLAVE_JITTER_TEST must be set
to 1 before link control is enabled (LINK_CONTROL = 1; see Table 21). During this test,
the transmitter reference clock is fed to pin P1_TXCLK for PHY1 and/or P0_TXCLK for
PHY0 of the TJA1102A. For the TJA1102AS, the transmitter reference clock is fed to pin
P0_TXCLK.
6.9 Error diagnosis
The diagnostic features described in this section are available individually for each dualPHY port, except for undervoltage detection of common supply voltages.
6.9.1 Undervoltage detection
The TJA1102A continuously monitors the status of the supply voltages. Once a supply
voltage drops below the specified minimum operating threshold, the TJA1102A enters the
fail-silent Standby mode and communication is halted. If an undervoltage is detected on
VBAT, the TJA1102A switches to Power-off mode.
At power-on, after a transition from Power-off to Standby mode, undervoltage detection
timeout is enabled once all supply voltages are available. The timeout timer is started
when an undervoltage is detected. If the undervoltage is still active when the timer
expires (after tto(uvd)), the TJA1102A switches from Standby mode to Sleep mode.
The microcontroller can determine the source of the interruption by reading the contents
of the External status register (Table 29). The under-voltage detection/recovery range
is positioned immediately next to the operating range, without a gap. Since parameters
are specified down to the minimum value of the under-voltage detection threshold, it
is guaranteed that the behavior of the TJA1102A is fully specified and defined for all
possible voltage condition on the supply pins.
TJA1102A
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6.9.2 Cabling errors
The TJA1102A can detect open and short circuits between the twisted-pair bus lines
when neither of the link partners is transmitting (link control disabled). It may make sense
to run the diagnostic before establishing the Ethernet link. When bit CABLE_TEST in
the Extended Control register (Table 21) is set to 1, test pulses are transmitted onto the
transmission medium with a repetition rate of 666.6 kHz. The TJA1102A evaluates the
reflected signals and uses impedance mismatch data along the channel to determine the
quality of the link. The results of the cable test are available in the External status register
(Table 29) within tto(cbl_tst). The tests performed and associated results are summarized in
Table 11.
Table 11. Cable tests and results
The cable bus lines are designated BI_DA+ and BI_DA-, in alignment with 100BASE-T1 [1].
BI_DA+
BI_DA-
Result
open
open
open detected
+ shorted to -
- shorted to +
short detected
shorted to VDD
open
open detected
open
shorted to VDD
open detected
shorted to VDD
shorted to VDD
short detected
shorted to GND
open
open detected
open
shorted to GND
open detected
shorted to GND
shorted to GND
short detected
connected to active link partner connected to active link partner short and open detected
(master)
(master)
6.9.3 Link stability
The Signal Quality Indicator (SQI) is the parameter used to estimate link stability. The
PMA receive function monitors the SQI. Once the value falls below a configurable
threshold (SQI_FAILLIMIT), the link status is set to FAIL and communication is
interrupted. The TJA1102A allows for adjusting the sensitivity of the PMA receive function
by configuring this threshold. The microcontroller can always check the current value of
the SQI via the SMI, allowing it to track a possible degradation in link stability.
6.9.4 Link-fail counter
High losses and/or a noisy channel may cause the link to shut down when reception
is no longer reliable. In such cases, the PHY generates a LINK_STATUS_FAIL
interrupt. Retraining of the link begins automatically provided link control is enabled
(LINK_CONTROL = 1).
Bits LOC_RCVR_COUNTER and REM_RCVR_COUNTER in the Link-fail counter
register (Table 30) are incremented after every link fail event. Both counters are reset
when this register is read.
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6.9.5 Jabber detection
The Jabber detection function prevents the PHY being locked in the DATA state of the
PCS Receive state diagram when the End-of-Stream Delimiters, ESD1 and ESD2, are
not detected.
The maximum time the PHY can reside in the DATA state is limited to tto(PCS-RX)
(rcv_max_timer in the IEEE specification [1]). After this time, the PCS-RX state machine
is reset, triggering a transition to PHY Idle state.
6.9.6 Polarity detection
A polarity error occurs when the two signal wires in the twisted pair cable connected to a
port are swapped. According to the IEEE specification [1], the polarity is always observed
to be correct by the Master PHY; only the Slave is allowed to correct the polarity. When
the TJA1102A is in Slave configuration, it can detect if the ternary symbols sent from the
Master PHY are received with the wrong polarity and will correct this error internally and
set the POLARITY_DETECT bit in the External status register (Table 29). Irrespective of
the Master or Slave mode, the host can overwrite and swap the default MDI polarity by
setting MDI_POL in Configuration Register 3 (Table 32).
6.9.7 Interleave detection
A 100BASE-T1 PHY can send two different interleave sequences of ternary symbols
(TAn, TBn) or (TBn, TAn). The receivers in the TJA1102A are able to de-interleave both
sequences. The order of the ternary symbols detected by the receiver is indicated by the
INTERLEAVE_DETECT bit in the External status register (Table 29).
6.9.8 Loopback modes
The TJA1102A supports three loopback modes:
• Internal loopback (PCS loopback in accordance with IEEE 802.3bw)
• External loopback
• Remote loopback
To run a PHY in loopback mode, the LOOPBACK control bit in the Basic control register
should be set before enabling link control.
6.9.8.1 Internal loopback
PMA
RECEIVE
MDI
MUX
In Internal loopback mode, the PCS receive function gets the ternary symbols An and
Bn directly from the PCS transmit function as shown in Figure 12. This action allows the
MAC to compare packets sent through the MII transmit function with packets received
from the MII receive function and, therefore, to validate the functionality of the 100BASET1 PCS function.
PCS
RECEIVE
MII Receive
An, Bn
PCS
TRANSMIT
MII Transmit
HYBRID
PMA
TRANSMIT
aaa-019866
Figure 12. Internal loopback
TJA1102A
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6.9.8.2 External loopback
In External loopback mode, the PMA receive function receives signals directly from the
PMA transmit function as shown in Figure 13. This external loopback test allows the MAC
to compare packets sent through the MII transmit function with packets received from the
MII receive function and, therefore, to validate the functionality of the 100BASE-T1 PCS
and PMA functions.
open
PMA
RECEIVE
PCS
RECEIVE
MII Receive
PMA
TRANSMIT
PCS
TRANSMIT
MII Transmit
HYBRID
aaa-019868
Figure 13. External loopback
6.9.8.3 Remote loopback
MII
MAC
PHY
MDI
MDI
In Remote loopback mode, the packet received by the link partner at the MDI is passed
through the PMA receive and PCS receive functions and forwarded to the PCS transmit
function, which in turn sends it back to the link partner from where it came. The PCS
receive data is made available at the MII. Remote loopback allows the MAC to compare
the packets sent to the MDI with the packets received back from the MDI and, therefore,
to validate the functionality of the physical channel, including both 100BASE-T1 PHYs.
PMA
RECEIVE
PCS
RECEIVE
MII Receive
PMA
TRANSMIT
PCS
TRANSMIT
MII Transmit
HYBRID
PHY in Remote loopback mode
aaa-019869
Figure 14. Remote loopback
6.10 Hardware configuration
A number of pins are provided to allow default values for a number of features to be
hardware-configured, without microcontroller interaction. The pull-up/down behavior
of these pins is sensed at power-up and after a reset. A pull-up behavior is coded
as logic 1, while a pull-down behavior is coded as logic 0. The results are stored in
the corresponding SMI registers. All pre-configuration settings (except for the PHY
addresses) can be overwritten via SMI commands.
Pin strapping at pins 37 (PHYAD3), 36 (PHYAD2) and 35 (PHYAD1) determines bits
3, 2 and 1, respectively, of the PHY address used for the SMI address/Cipher scrambler.
The PHY address cannot be changed once the PHY has been configured. Besides
the address configured via pin strapping, the TJA1102A can always be accessed via
address 0.
Table 12 gives an overview of the functions to be configured via hardware pins.
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Table 12. Pin strapping configuration
Symbol
Pin
MASTER_SLAVE/
PHY_EN
AUTO_OP
PHYAD[3:1]
MII_CONFIG
[1]
Value
[2]
000
P0 disabled, P1 Master
001
P0 disabled, P1 Slave
010
P0 Master, P1 disabled
011
P0 Master, P1 Master
100
P0 Master, P1 Slave
101
P0 Slave, P1 disabled
110
P0 Slave, P1 Master
111
P0 Slave, P1 Slave
0
managed operation
1
autonomous operation
37 (PHYAD3)
-
bit 3 of PHY address used for the SMI
36 (PHYAD2)
-
bit 2 of PHY address used for the SMI
35 (PHYAD1)
-
34 (CONFIG3)
33 (CONFIG2)
32 (CONFIG1)
55 (CONFIG0)
1 (CONFIG5)
56 (CONFIG4)
LDO_MODE
[1]
[2]
[3]
[4]
TJA1102A
Product data sheet
3 (CONFIG7)
2 (CONFIG6)
15 (SEL_1V8)
bit 1 of PHY address used for the SMI
00
[3]
MII mode enabled for both PHYs (bits
MII_MODE in Table 22 set to 00)
01
[4]
RMII mode enabled for both PHYs (bits
MII_MODE in Table 22 set to 01 or 10,
depending on CLK_MODE)
10
[3]
Reverse MII mode P0;
MII mode P1, internal MII
(bits MII_MODE in Table 22 set to 11 for P0
and 00 for P1; bit INT_REV_MII in Table 29
set to 1)
[3]
Reverse MII mode P0;
MII mode P1; external MII;
(bits MII_MODE in Table 22 set to 11 for P0
and 00 for P1; bit INT_REV_MII in Table 29
set to 0)
11
CLK_MODE
Description
00
25 MHz XTAL; no clock at CLK_IN_OUT
01
25 MHz XTAL; 25 MHz at CLK_IN_OUT
10
25 MHz external clock at CLK_IN_OUT
11
50 MHz input at REF_CLK; RMII mode only;
no XTAL; no clock at CLK_IN_OUT
0
internal 1.8 V LDO enabled
1
external 1.8 V supply
Pin strapping functionality relating to PHY1 is not relevant to the TJA1102AS, since P1 is permanently disabled.
Ordered from MSB to LSB; for value 011 for example, pin 34 = 0, pin 33 = 1 and pin 32 = 1. Note that PHY1 is always
disabled in the TJA1102AS, regardless of the value level of on these pins during pin strapping.
CLK_MODE = 00, 01 or 10.
All clock modes (CLK_MODE = xx).
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6.11 SMI registers
A dedicated register set is provided for each PHY. Some register bits are only valid for
block P0 and always return 0 when read from block P1. These bits are indicated in the
appropriate tables. Two shared configuration registers are provided to configure common
parameters.
Access to the register sets for both PHY blocks on the TJA1102A is provided via the
SMI. Which PHY block is selected by an SMI read/write access depends on the PHY
address in the SMI frame (read/write access to disabled block P1 is not supported on the
TJA1102AS).
6.11.1 Register mapping overview
Copies of the registers listed in Table 13 are provided for each PHY (except for the
Common configuration registers which are shared) and are accessible via SMI with the
appropriate PHY address.
Table 13. SMI register mapping
Register index (dec)
Register name
Group
0
Basic control register
Basic
1
Basic status register
Basic
2
PHY identification register 1
Extended (P0 only)
3
PHY identification register 2
Extended (P0 only)
15
Extended status register
Extended
16
PHY identification register 3
NXP specific (P0 only)
17
Extended control register
NXP specific
18
Configuration register 1
NXP specific
19
Configuration register 2
NXP specific
20
Symbol error counter register
NXP specific
21
Interrupt source register
NXP specific
22
Interrupt enable register
NXP specific
23
Communication status register
NXP specific
24
General status register
NXP specific
25
External status register
NXP specific
26
Link-fail counter register
NXP specific
27
Common configuration register
NXP specific (P0 only)
28
Configuration register 3
NXP specific
Table 14. Register notation
TJA1102A
Product data sheet
Notation
Description
R/W
Read/write
R
Read only
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Table 14. Register notation...continued
Notation
Description
LH
Latched HIGH; must be read out to reset
LL
Latched LOW; must be read out to reset
SC
Self-clearing
PS
Pin strapping
6.11.2 TJA1102A registers
Table 15. Basic control register (register 0)
Bit
Symbol
Access
15
RESET
R/W
SC
Value
software reset control:
0
[1]
1
14
LOOPBACK
[2]
loopback control:
[1]
1
SPEED_SELECT (LSB)
R/W
AUTONEG_EN
R/W
SC
11
POWER_DOWN
R/W
speed select (LSB):
10 Mbit/s if SPEED_SELECT (MSB) = 0
1000 Mbit/s if SPEED_SELECT (MSB) = 1
1
[1]
0
[1]
0
[1]
ISOLATE
100 Mbit/s if SPEED_SELECT (MSB) = 0
reserved if SPEED_SELECT (MSB) = 1
Auto negotiation not supported; always 0; a write access is
ignored.
Standby power down enable:
1
10
normal operation
loopback mode
[3]
0
12
normal operation
PHY reset
R/W
0
13
Description
normal operation (clearing this bit automatically triggers
a transition to Normal mode, provided control bits
POWER_MODE are set to 0011 Normal mode, see
Table 21)
power down and switch to Standby mode (provided
ISOLATE = 0; ignored if ISOLATE = 1 and
CONTROL_ERR interrupt generated)
PHY isolation:
R/W
0
[1]
1
normal operation
isolate PHY from MII/RMII (provided POWER_DOWN =
0; ignored if POWER_DOWN = 1 and CONTROL_ERR
interrupt generated)
9
RE_AUTONEG
R/W
SC
0
[1]
Auto negotiation not supported; always 0; a write access is
ignored.
8
DUPLEX_MODE
R/W
1
[1]
only full duplex supported; always 1; a write access is
ignored.
7
COLLISION_TEST
R/W
0
[1]
COL signal test not supported; always 0; a write access is
ignored.
6
SPEED_SELECT (MSB)
R/W
[3]
TJA1102A
Product data sheet
speed select (MSB):
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100BASE-T1 dual/single PHY for automotive Ethernet
Table 15. Basic control register (register 0)...continued
Bit
Symbol
Access
Value
0
Description
[1]
10 Mbit/s if SPEED_SELECT (LSB) = 0
100 Mbit/s if SPEED_SELECT (LSB) = 1
1
5
UNIDIRECT_EN
1000 Mbit/s if SPEED_SELECT (LSB) = 0
reserved if SPEED_SELECT (LSB) = 1
unidirectional enable when bit 12 (AUTONEG_EN) = 0 and bit
8 (DUPLEX_MODE) = 1:
R/W
0
[1]
enable transmit from MII only when the PHY has
determined that a valid link has been established
1
4:0
[1]
[2]
[3]
reserved
R/W
enable transmit from MII regardless of whether the PHY
has determined that a valid link has been established
00000
[1]
always write 00000; ignore on read
Default value.
The loopback mode is selected via bits LOOPBACK_MODE in the Extended control register (Table 21).
Speed Select: 00: 10 Mbit/s; 01: 100 Mbit/s; 10: 1000 Mbit/s; 11: reserved; a write access value other than 01 is ignored.
Table 16. Basic status register (register 1)
Bit
15
Symbol
100BASE-T4
Access
R
Value
0
[1]
1
14
100BASE-X_FD
R
0
100BASE-X_HD
R
0
10Mbps_FD
R
0
10Mbps_HD
R
0
100BASE-T2_FD
R
0
100BASE-T2_HD
R
0
EXTENDED_STATUS
R
7
UNIDIRECT_ ABILITY
R
6
MF_PREAMBLE_SUPPRESSION
TJA1102A
Product data sheet
R
no extended status information in register 15h
[1]
0
1
0
PHY not able to perform 100BASE-T2 half-duplex
PHY able to perform 100BASE-T2 half-duplex
0
1
PHY not able to perform 100BASE-T2 full-duplex
PHY able to perform 100BASE-T2 full-duplex
[1]
1
8
PHY not able to perform 10 Mbit/s half-duplex
PHY able to perform 10 Mbit/s half-duplex
[1]
1
9
PHY not able to perform 10 Mbit/s full-duplex
PHY able to perform 10 Mbit/s full-duplex
[1]
1
10
PHY not able to perform 100BASE-X half-duplex
PHY able to perform 100BASE-X half-duplex
[1]
1
11
PHY not able to perform 100BASE-X full-duplex
PHY able to perform 100BASE-X full-duplex
[1]
1
12
PHY not able to perform 100BASE-T4
PHY able to perform 100BASE-T4
[1]
1
13
Description
extended status information in register 15h
PHY able to transmit from MII only when the PHY has
determined that a valid link has been established
[1]
PHY able to transmit from MII regardless of whether the
PHY has determined that a valid link has been established
PHY will not accept management frames with preamble
suppressed
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TJA1102A
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100BASE-T1 dual/single PHY for automotive Ethernet
Table 16. Basic status register (register 1)...continued
Bit
Symbol
Access
Value
1
5
AUTONEG_COMPLETE
4
REMOTE_FAULT
3
0
R
R
LH
AUTONEG_ABILITY
[1]
Autonegotiation process not completed
1
Autonegotiation process completed
0
[1][2]
no remote fault condition detected
0
remote fault condition detected
[1]
1
2
LINK_STATUS
1
JABBER_DETECT
0
0
R
LL
EXTENDED_CAPABILITY
R
LH
0
R
0
PHY not able to perform Autonegotiation
PHY able to perform Autonegotiation
[1][2][3]
1
link is down
link is up
[1][2]
1
1
[1]
[2]
[3]
PHY will accept management frames with preamble
suppressed
[1]
1
R
Description
no jabber condition detected
jabber condition detected
basic register set capabilities only
[1]
extended register capabilities
Default value.
Reset to default value when link control is disabled (LINK_CONTROL = 0).
According to IEEE 802.3; LINK_STATUS = 1 when LOC_RCVR_STATUS = 1.
Table 17. PHY identification register 1 (register 2)
Bit
Symbol
Access
Value
15:0
PHY_ID
R
0180h
[1]
[2]
Description
[1]
[2]
bits 3 to 18 of the Organizationally Unique Identifier (OUI)
Default value (PHY0 only in dual PHY variant; returns all 0s for PHY1).
OUI = 00.60.37h (PHY0 only in dual PHY variant; returns all 0s for PHY1).
Table 18. PHY identification register 2 (register 3)
Bit
Symbol
Access
Value
Description
[1]
bits 19 to 24 of the OUI
[3]
six-bit manufacturer’s type number
15:10
PHY_ID
R
110111
9:4
TYPE_NO
R
001000
[2]
[4]
001001
3:0
[1]
[2]
[3]
[4]
REVISION_NO
R
0010
[1]
four-bit manufacturer’s revision number
Default value (PHY0 only in dual-PHY variant; returns all 0s for PHY1).
OUI = 00.60.37h (PHY0 only in dual-PHY variant; returns all 0s for PHY1).
Default value for TJA1102A dual-PHY variant (PHY0 only; returns all 0s for PHY1).
Default value for TJA1102AS.
Table 19. PHY identification register 3 (Register 16)
Bit
Symbol
Access
Value
15:8
reserved
R
-
TJA1102A
Product data sheet
Description
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100BASE-T1 dual/single PHY for automotive Ethernet
Table 19. PHY identification register 3 (Register 16)...continued
Bit
Symbol
7:0
[1]
VERSION_NO
Access
Value
Description
[1]
R
xxh
8-bit manufacturer's firmware revision number
Default value (PHY0 only in dual-PHY variant; returns all 0s for PHY1).
Table 20. Extended status register (register 15)
Bit
Symbol
15
Access Value
1000BASE-X_FD
0
R
Description
[1]
PHY not able to perform 1000BASE-X full-duplex
1
14
1000BASE-X_HD
0
R
PHY able to perform 1000BASE-X full-duplex
[1]
PHY not able to perform 1000BASE-X half-duplex
1
13
1000BASE-T_FD
0
R
PHY able to perform 1000BASE-X half-duplex
[1]
PHY not able to perform 1000BASE-T full-duplex
1
12
1000BASE-T_HD
0
R
PHY able to perform 1000BASE-T full-duplex
[1]
PHY not able to perform 1000BASE-T half-duplex
1
PHY able to perform 1000BASE-T half-duplex
11:8 reserved
R
0000
7
R
0
100BASE-T1
6
1000BASE-RTPGE
5:0
[1]
R
reserved
R
[1]
always 0000; ignore on read
PHY not able to 1-pair 100BASE-T1 100 Mbit/s
1
[1]
PHY able to 1-pair 100BASE-T1 100 Mbit/s
0
[1]
PHY not able to support RTPGE
1
PHY supports RTPGE
-
ignore on read
Default value.
Table 21. Extended control register (register 17)
Bit
15
14:11
Symbol
LINK_CONTROL
POWER_MODE
Access
Value
Description
R/W
[1]
link control enable:
R/W
0
link control disabled
1
link control enabled
[2]
operating mode select:
0000
10
[4]
SLAVE_JITTER_TEST
Product data sheet
no change
0011
Normal mode (command)
1001
Silent mode (read only)
1010
Sleep mode (read only)
1011
Sleep Request mode (command)
1100
Standby mode (command)
enable/disable Slave jitter test
R/W
0
TJA1102A
[3]
[3]
disable Slave jitter test
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100BASE-T1 dual/single PHY for automotive Ethernet
Table 21. Extended control register (register 17)...continued
Bit
Symbol
Access
Value
1
9
TRAINING_RESTART
R/W
SC
enable Slave jitter test
Autonegotiation process restart:
0
[3]
halts the training phase
1
[4]
8:6
TEST_MODE
forces a restart of the training phase
test mode selection:
R/W
[3]
5
CABLE_TEST
R/W
SC
000
no test mode
001
100BASE-T1 test mode 1
010
100BASE-T1 test mode 2
011
test mode 3
100
100BASE-T1 test mode 4
101
100BASE-T1 test mode 5
110
scrambler and descrambler bypassed
111
reserved; ignore on read
TDR-based cable test:
0
[3]
stops TDR-based cable test
1
[4][5]
4:3
LOOPBACK_MODE
forces TDR-based cable test
loopback mode select:
R/W
00
2
CONFIG_EN
R/W
[3]
external loopback
10
external loopback
11
remote loopback
[3]
[3]
1
reserved
R/W
0
WAKE_REQUEST
SC
configuration register access:
configuration register access disabled
configuration register access enabled
-
ignore on read
wake-up request configuration:
0
1
[1]
[2]
[3]
[4]
[5]
internal loopback
01
0
1
Description
[3]
no wake-up signal to be transmitted
LINK_CONTROL = 0: transmit idle symbols as bus wake-up
request
LINK_CONTROL = 1: transmit WUR symbols
Default value is 0 when AUTO_OP = 0; default value is 1 when AUTO_OP = 1.
Any other value generates a CONTROL_ERR interrupt.
Default value.
Link control must be disabled (LINK_CONTROL = 0) before entering this mode.
The selected loopback mode is enabled when bit LOOPBACK in the Basic control register (Table 15) is set to 1.
TJA1102A
Product data sheet
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100BASE-T1 dual/single PHY for automotive Ethernet
Table 22. Configuration register 1 (register 18)
Bit
15
14
Symbol
MASTER_SLAVE
FWDPHYLOC
Access
Value
Description
R/W
[1]
PHY Master/Slave configuration:
0
PHY configured as Slave
1
PHY configured as Master
R/W
[2]
0
1
13:12
11
reserved
REMWUPHY
wake-up event not forwarded locally
[3]
-
ignore on read
R/W
[2]
remote wake-up:
1
LOCWUPHY
R/W
PHY does not react to a remote wake-up
[3]
[2] [4]
0
1
9:8
7
MII_MODE
MII_DRIVER
R/W
RMII mode enabled (50 MHz input on Px_REF_CLK)
10
RMII mode enabled (25 MHz XTAL output on Px_REF_CLK)
11
Reverse MII mode
MII output driver strength:
R/W
[3]
sleep confirmation setting:
[3]
LPS/WUR setting:
R/W
[3]
sleep acknowledge:
[3]
1
2
reserved
FWDPHYREM
Product data sheet
sleep acknowledge timer disabled; auto-transition back from
Sleep Request mode to Normal mode enabled during data
transmission on MII or MDI
sleep acknowledge timer enabled; auto-transition back from
Sleep Request mode to Normal mode disabled during data
transmission on MII or MDI
R/W
-
R/W
[2]
0
TJA1102A
LPS/WUR enabled
LPS/WUR disabled
R/W
0
3
no confirmation needed from another PHY before going to
sleep
confirmation needed from another PHY before going to sleep
1
SLEEP_ACK
standard
reduced
R/W
0
4
MII mode:
01
1
LPS_WUR_DIS
PHY reacts to a local wake-up
MII mode enabled
0
5
local wake-up:
00
1
SLEEP_CONFIRM
PHY reacts to a remote wake-up
PHY does not react to a local wake-up
[3]
[1]
0
6
wake-up event forwarded locally
R/W
0
10
local wake-up forwarding:
ignore on read
[3]
remote wake-up forwarding:
remote wake-up event not forwarded
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100BASE-T1 dual/single PHY for automotive Ethernet
Table 22. Configuration register 1 (register 18)...continued
Bit
Symbol
Access
Value
Description
1
1
AUTO_PWD
remote wake-up event forwarded
autonomous power down:
R/W
0
[3]
autonomous power-down disabled
1
0
LPS_ACTIVE
autonomous power-down enabled
LPS code group reception:
R/W
0
1
[1]
[2]
[3]
[4]
automatic transition from Normal to Sleep Request when LPS
code group received disabled
[3]
automatic transition from Normal to Sleep Request when LPS
code group received enabled
Default value determined by pin strapping (see Section 6.10).
Clear bits FWDPHYLOC, REMWUPHY, LOCWUPHY and FWDPHYREM if the corresponding wake-up/forwarding feature is not being used.
Default value.
Setting LOCWUPHY has an activation time of tdet(wake). If a wake-up occurs within the activation time, it may not be detected.
Table 23. Configuration register 2 (register 19)
Bit
Symbol
Access
Value
Description
PHY address used for the SMI address and for initializing the
Cipher scrambler key:
PHYAD[4] is set to 0
PHYAD[3:1] is predetermined by the hardware configuration
straps on pins 37, 36 and 35 respectively
PHYAD[0] set to 0 for P0 and 1 for P1
Signal Quality Indicator (SQI) averaging:
15:11
PHYAD[4:0]
R
[1]
10:9
SQI_AVERAGING
R/W
[2]
00
01
8:6
SQI_WLIMIT
SQI averaged 32 symbols
[3]
SQI averaged 64 symbols
10
SQI averaged 128 symbols
11
SQI averaged 256 symbols
SQI warning limit:
R/W
000
no warning limit
[3]
5:3
SQI_FAILLIMIT
001
class A SQI warning limit
010
class B SQI warning limit
011
class C SQI warning limit
100
class D SQI warning limit
101
class E SQI warning limit
110
class F SQI warning limit
111
class G SQI warning limit
SQI fail limit:
R/W
[3]
TJA1102A
Product data sheet
000
no fail limit
001
class A SQI fail limit
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100BASE-T1 dual/single PHY for automotive Ethernet
Table 23. Configuration register 2 (register 19)...continued
Bit
Symbol
2
Access
JUMBO_ENABLE
Value
Description
010
class B SQI fail limit
011
class C SQI fail limit
100
class D SQI fail limit
101
class E SQI fail limit
110
class F SQI fail limit
111
class G SQI fail limit
Jumbo packet support:
R/W
0
1
1:0
packets up to 4 kB supported
[3]
packets up to 16 kB supported
[4]
SLEEP_REQUEST_TO R/W
sleep request/acknowledge timeout:
00
01
[1]
[2]
[3]
[4]
0.4 ms/0.2 ms
[3]
1 ms/0.5 ms
10
4 ms/2 ms
11
16 ms/8 ms
Default value determined by pin strapping (see Section 6.10).
The SQI is derived from the actual internal slicer margin and includes filtering. Averaging the SQI value itself does not, therefore, have any added value.
Default value.
The specified values are nominal settings; see parameters tto(req)sleep and tto(ack)sleep, respectively, for the limits.
Table 24. Symbol error counter register (register 20)
Bit
Symbol
15:0
[1]
Access
SYM_ERR_CNT R
Value
0000h
Description
[1]
The symbol error counter is incremented when an invalid code
symbol is received (including idle symbols). The counter is
incremented only once per packet, even when the received packet
contains more than one symbol error. This counter increments up to
16
2 . When the counter overflows, the value FFFFh is retained. The
counter is reset when the register is read.
Default value. Bits NOT reset to default value when link control is disabled (LINK_CONTROL = 0).
Table 25. Interrupt source register (register 21)
Bit
15
14
13
Symbol
PWON
WAKEUP
WUR_RECEIVED
TJA1102A
Product data sheet
Access
R
LH
R
LH
R
LH
Value
0
[1]
power-on not detected
1
0
power-on detected
[2][3]
1
0
1
Description
no local or remote wake-up detected
local or remote wake-up detected
[2]
no dedicated wake-up request detected
dedicated wake-up request detected
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100BASE-T1 dual/single PHY for automotive Ethernet
Table 25. Interrupt source register (register 21)...continued
Bit
Symbol
12
LPS_RECEIVED
11
PHY_INIT_FAIL
10
LINK_STATUS_FAIL
9
LINK_STATUS_UP
8
SYM_ERR
7
TRAINING_FAILED
6
SQI_WARNING
5
CONTROL_ERR
4
reserved
3
UV_ERR
2
UV_RECOVERY
1
TEMP_ERR
0
SLEEP_ABORT
Access
Value
0
R
LH
Description
[2]
no LPS code groups received
1
0
R
LH
LPS code groups received
[2]
no PHY initialization error detected
1
0
R
LH
PHY initialization error detected
[2][4]
link status not changed
1
0
R
LH
link status bit LINK_UP changed from ‘link OK’ to ‘link fail’
[2][4]
link status not changed
1
0
R
LH
link status bit LINK_UP changed from ‘link fail’ to ‘link OK’
[2][4]
no symbol error detected
1
0
R
LH
symbol error detected
[2]
no training phase failure detected
1
0
R
LH
training phase failure detected
[2][4]
SQI value above warning limit
1
R
LH
0
R
-
SQI value below warning limit and bit LINK_UP set
[2]
no SMI control error detected
1
R
LH
0
R
LH
0
SMI control error detected
ignore on read
[1]
no undervoltage detected
1
undervoltage detected on VDD(IO), VDDD(3V3), VDDD(1V8) or
VDDA(3V3)
[1]
no undervoltage recovery detected
1
0
R
LH
undervoltage recovery detected
[1]
no overtemperature error detected
1
0
R
LH
overtemperature error detected
[2]
no transition from Sleep Request back to Normal as a result of
the Sleep Request timer expiring
1
[1]
[2]
[3]
[4]
transition from Sleep Request back to Normal as a result of the
Sleep Request timer expiring
Default value (P0 only; always returns 0 for P1 block).
Default value.
Bit WAKEUP may be set when an undervoltage is detected on VDD(IO) in Sleep_Request mode. Ignore this bit when bit UV_VDDIO is set.
Bit WAKEUP is reset by a read operation; however wake-up detection will not be enabled again until a state transition has been completed.
Interrupts LINK_STATUS_FAIL, LINK_STATUS_UP, SYM_ERR and SQI_WARNING are cleared on entering Sleep Request mode, on entering Standby
mode due to an undervoltage and when an undervoltage is detected in Standby mode.
Table 26. Interrupt enable register (register 22)
Disabling an interrupt source disables signaling at pin INT_N for that interrupt. However, the corresponding bit in the
Interrupt source register (Table 25) remains active.
Bit
15
Symbol
PWON_EN
TJA1102A
Product data sheet
Access
R/W
Value
0
[1]
Description
PWON interrupt disabled
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100BASE-T1 dual/single PHY for automotive Ethernet
Table 26. Interrupt enable register (register 22)...continued
Disabling an interrupt source disables signaling at pin INT_N for that interrupt. However, the corresponding bit in the
Interrupt source register (Table 25) remains active.
Bit
Symbol
14
WAKEUP_EN
Access
Value
R/W
1
PWON interrupt enabled
0
[2]
WAKEUP interrupt disabled
1
13
WUR_RECEIVED_EN
0
R/W
WAKEUP interrupt enabled
[2]
1
12
LPS_RECEIVED_EN
0
R/W
PHY_INIT_FAIL_EN
0
R/W
LINK_STATUS_FAIL_EN
0
R/W
LINK_STATUS_UP_EN
0
R/W
SYM_ERR_EN
0
R/W
TRAINING_FAILED_EN
0
R/W
SQI_WARNING_EN
0
R/W
CONTROL_ERR_EN
0
R/W
reserved
3
UV_ERR_EN
R/W
R/W
UV_RECOVERY_EN
CONTROL_ERR interrupt enabled
0
always write 0; ignore on read
0
[2]
UV_ERR interrupt disabled
0
R/W
UV_ERR interrupt enabled
[2]
1
1
TEMP_ERR_EN
0
R/W
SLEEP_ABORT_EN
0
R/W
1
[1]
[2]
UV_RECOVERY interrupt disabled
UV_RECOVERY interrupt enabled
[2]
1
0
CONTROL_ERR interrupt disabled
[2]
1
2
SQI_WARNING interrupt disabled
SQI_WARNING interrupt enabled
[2]
1
4
TRAINING_FAILED interrupt disabled
TRAINING_FAILED interrupt enabled
[2]
1
5
SYM_ERR interrupt disabled
SYM_ERR interrupt enabled
[2]
1
6
LINK_STATUS_UP interrupt disabled
LINK_STATUS_UP interrupt enabled
[2]
1
7
LINK_STATUS_FAIL interrupt disabled
LINK_STATUS_FAIL interrupt enabled
[2]
1
8
PHY_INIT_FAIL interrupt disabled
PHY_INIT_FAIL interrupt enabled
[2]
1
9
LPS_RECEIVED interrupt disabled
LPS_RECEIVED interrupt enabled
[2]
1
10
WUR_RECEIVED interrupt disabled
WUR_RECEIVED interrupt enabled
[2]
1
11
Description
[1]
TEMP_ERR interrupt disabled
TEMP_ERR interrupt enabled
[2]
SLEEP_ABORT interrupt disabled
SLEEP_ABORT interrupt enabled
Default value is 1 for block P0 and 0 for block P1 (TJA1102A).
Default value.
TJA1102A
Product data sheet
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100BASE-T1 dual/single PHY for automotive Ethernet
Table 27. Communication status register (register 23)
Bit
15
Symbol
LINK_UP
Access
R
Value
0
[1][2]
link failure
1
14:13
12
11
10
TX_MODE
LOC_RCVR_STATUS
REM_RCVR_STATUS
SCR_LOCKED
R
R
LL
R
LL
R
link OK
00
[1][2]
8
7:5
4
3
2:0
SSD_ERR
ESD_ERR
SQI
RECEIVE_ERR
TRANSMIT_ERR
PHY_STATE
TJA1102A
Product data sheet
R
LH
R
LH
R
R
LH
R
LH
R
transmitter disabled
01
transmitter in SEND_N mode
10
transmitter in SEND_I mode
11
transmitter in SEND_Z mode
0
[1][2]
local receiver not OK
1
0
local receiver OK
[1][2]
remote receiver not OK
1
0
remote receiver OK
[1][2]
descrambler unlocked
1
9
Description
0
descrambler locked
[1][2]
no SSD error detected
1
0
SSD error detected
[1][2]
no ESD error detected
1
ESD error detected
[1][2]
000
worse than class A SQI (unstable link)
001
class A SQI (unstable link)
010
class B SQI (unstable link)
011
class C SQI (good link)
100
class D SQI (good link; bit error rate < 1e-10)
101
class E SQI (good link)
110
class F SQI (very good link)
111
class G SQI (very good link)
0
[1][2]
no receive error detected
0
0
receive error detected since register last read
[1][2]
no transmit error detected
1
transmit error detected since register last read
[1]
000
PHY Idle
001
PHY Initializing
010
PHY Configured
011
PHY Offline
100
PHY Active
101
PHY Isolate
110
PHY Cable test
111
PHY Test mode
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100BASE-T1 dual/single PHY for automotive Ethernet
[1]
[2]
Default value.
Reset to default value when link control is disabled (LINK_CONTROL = 0).
Table 28. General status register (register 24)
Bit
Symbol
15
INT_STATUS
Access
Value
0
R
Description
[1]
all interrupts cleared
1
14
PLL_LOCKED
13
LOCAL_WU
12
REMOTE_WU
11
DATA_DET_WU
0
R
LL
unmasked interrupt pending
[1]
PLL unstable and not locked
1
0
R
LH
PLL stable and locked
[1][2]
no local wake-up detected
1
0
R
LH
local wake-up detected
[1][2]
no remote wake-up detected
1
0
R
LH
remote wake-up detected
[1][3]
no 100BASE-T1 data detected at MDI or MII in Sleep
Request mode
1
10
EN_STATUS
9
RESET_STATUS
8
reserved
0
R
LH
100BASE-T1 data detected at MDI (pcs_rx_dv = TRUE; see
[1]) or MII (TXEN = 1) in Sleep Request mode
[4]
1
R
LH
0
R
-
EN switched LOW since register last read
[4]
no hardware reset detected
1
hardware reset detected since register last read
ignore on read
7:3
LINKFAIL_CNT
R
00000
2:0
reserved
R
-
[1]
[2]
[3]
[4]
[5]
EN HIGH
[1][5]
number of link fails since register last read
ignore on read
Default value.
Status bit is cleared by a read operation; however wake-up detection will not be enabled again until a state transition has been completed.
Bit DATA_DET_WU may be set when an undervoltage is detected on VDD(IO) in Sleep_Request mode. Ignore this bit when bit UV_VDDIO is set.
Default value (P0 only; always returns 0 for P1 block).
Bits NOT reset to default value when link control is disabled (LINK_CONTROL = 0).
Table 29. External status register (register 25)
Bit
15
14
13
12
11
Symbol
UV_VDDD_3V3
UV_VDDA_3V3
UV_VDDD_1V8
reserved
UV_VDDIO
TJA1102A
Product data sheet
Access
R
LH
R
LH
Value
0
1
0
0
R
1
no undervoltage detected on pin VDDD(3V3)
no undervoltage detected on pin VDDA(3V3)
undervoltage detected on pin VDDA(3V3)
[1]
1
0
Description
undervoltage detected on pin VDDD(3V3)
[1]
1
R
LH
R
LH
[1]
no undervoltage detected on pin VDDD(1V8)
undervoltage detected on pin VDDD(1V8)
ignore on read
[1]
no undervoltage detected on pin VDD(IO)
undervoltage detected on pin VDD(IO)
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100BASE-T1 dual/single PHY for automotive Ethernet
Table 29. External status register (register 25)...continued
Bit
Symbol
10
Access
TEMP_HIGH
9
6
0
0
temperature above high level
[1]
temperature below warning level
temperature above warning level
[2]
no short circuit detected
1
0
R
LH
POLARITY_DETECT
temperature below high level
1
R
LH
OPEN_DETECT
Description
[1]
1
R
LH
SHORT_DETECT
7
0
R
LH
TEMP_WARN
8
Value
short circuit detected since register last read
[2]
no open circuit detected
1
0
R
open circuit detected since register last read
[2]
no polarity inversion detected at MDI
1
5
4:0
[1]
[2]
0
INTERLEAVE_DETECT R
reserved
R
polarity inversion detected at MDI
[2]
interleave order of detected ternary symbols: TAn, TBn
1
interleave order of detected ternary symbols: TBn, TAn
-
ignore on read
Default value (P0 only; always returns 0 for P1 block).
Default value; bit NOT reset to default value when link control is disabled (LINK_CONTROL = 0).
Table 30. Link fail counter register (register 26)
Bit
Symbol
Access
Value
The counter is incremented when local receiver is NOT_OK;
when the counter overflows, the value FFh is retained. The
counter is reset when the register is read.
[1][2]
The counter is incremented when remote receiver is NOT_OK;
when the counter overflows, the value FFh is retained. The
counter is reset when the register is read.
15:8
LOC_RCVR_CNT
R
00h
7:0
REM_RCVR_CNT
R
00h
[1]
[2]
Description
[1][2]
Default value.
Bits NOT reset to default value when link control is disabled (LINK_CONTROL = 0).
[1]
Table 31. Common configuration register (register 27)
Bit
15
14
13:12
Symbol
AUTO_OP
INT_REV_MII
CLK_MODE
TJA1102A
Product data sheet
Access
Value
Description
R/W
[2]
managed/autonomous operation:
R/W
R/W
0
managed operation
1
autonomous operation
[2]
PHY Master/Slave configuration (P0 in Reverse MII mode; P1 in
MII mode)
0
P1 must be connected externally to P0 (external PHY must be
connected to P0 in the TJA1102AS)
1
P1 connected internally to P0 (TJA1102A)
[2]
clock mode:
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100BASE-T1 dual/single PHY for automotive Ethernet
[1]
...continued
Table 31. Common configuration register (register 27)
Bit
Symbol
11
LDO_MODE
10
CLK_DRIVER
Access
R/W
Value
00
25 MHz XTAL; no clock at CLK_IN_OUT
01
25 MHz XTAL; 25 MHz output at CLK_IN_OUT
10
25 MHz external clock at CLK_IN_OUT
11
50 MHz input at REF_CLK; RMII mode only; no XTAL; no
clock at CLK_IN_OUT
[2]
LDO mode:
0
internal 1.8 V LDO enabled
1
external 1.8 V supply
output driver strength on CLK_IN_OUT:
R/W
0
[3]
1
9
CLK_HOLD
local wake-up:
[3]
1
LOC_WU_TIM
CONFIG_WAKE
local wake-up timer:
R/W
[3]
CONFIG_INH
long (250 μs to 500 μs)
10
short (100 μs to 200 μs)
11
shortest (10 μs to 40 μs)
local wake configuration:
R/W
absolute input threshold
1
[3]
0
[3]
[1]
[2]
[3]
reserved
R/W
ratiometric input threshold (VDD(IO))
INH configuration:
R/W
1
4:0
longest (10 ms to 20 ms)
01
0
5
XTAL and CLK_IN_OUT output switched off when not needed
by P0 and P1
XTAL and CLK_IN_OUT output remain active until device
switched to Sleep mode via SMI
00
6
standard output driver strength at output of CLK_IN_OUT
reduced output driver strength at output of CLK_IN_OUT
R/W
0
8:7
Description
-
INH switched off in Disable mode
INH switched on in Disable mode
ignore on read
Read/write operations valid for P0 only (read operation always returns 0 for P1 block).
Default value determined by pin strapping (see Section 6.10).
Default value.
Table 32. Configuration register 3 (register 28)
Bit
Symbol
Access
Value
15:3
reserved
R/W
-
TJA1102A
Product data sheet
Description
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100BASE-T1 dual/single PHY for automotive Ethernet
Table 32. Configuration register 3 (register 28)...continued
Bit
Symbol
Access
2
MDI_POL
R/W
Value
Description
MDI polarity:
0
[1]
regular polarity:
pin 17 = P0_TRX_P; pin 18 = P0_TRX_M
pin 25 = P1_TRX_P; pin 24 = P1_TRX_M
1
1
FORCE_SLEEP
R/W
SC
swapped polarity:
pin 17 = P0_TRX_M; pin 18 = P0_TRX_P
pin 25 = P1_TRX_M; pin 24 = P1_TRX_P
forced sleep operation:
0
[2]
forced sleep inactive
1
0
[1]
[2]
[3]
PHY_EN
R/W
force both PHYs to Sleep mode and device to system sleep
[3]
PHY enable:
0
PHY disabled
1
PHY enabled
Default value.
Default value (P0 only; always returns 0 for P1 block).
Default value determined by pin strapping (see Section 6.10).
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Product data sheet
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100BASE-T1 dual/single PHY for automotive Ethernet
7
Limiting values
Table 33. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are referenced to GND.
Symbol Parameter
[1]
Vx
voltage on pin x
IO(INH)
Vtrt
Conditions
Min
Max
Unit
on pin VBAT
-0.3
+40
V
on pin INH
-0.3
VBAT + 0.3
V
on pin WAKE_IN_OUT
-36
+42
V
on pins VDDA(3V3), P0_VDDA(TX), P1_VDDA(TX),
VDDD(3V3), VDD(IO), P0_TRX_P, P0_TRX_M,
P1_TRX_P, P1_TRX_M
-0.3
+4.6
V
on pins VDDD(1V8), XI, XO
-0.3
+2.5
V
on input pins MDC, MDIO, RST_N, INT_N, EN,
CLK_IN_OUT, SEL_1V8 and MII digital input
pins
-0.3
min(VDD(IO) + V
0.3, +4.6)
on digital output pins
-0.3
VDD(IO) + 0.3
V
-2
-
mA
pulse 1
-100
-
V
pulse 2a
-
75
V
pulse 3a
-150
-
V
-
100
V
output current on pin INH
transient voltage
on pins WAKE_IN_OUT, VBAT, P0_TRX_P,
P0_TRX_M, P1_TRX_P, P1_TRX_M
[2]
pulse 3b
VESD
electrostatic discharge
voltage
IEC 61000-4-2; 150 pF, 330 Ω
[3]
on pins P0_TRX_P, P0_TRX_M, P1_TRX_P,
P1_TRX_M
[4]
-8.0
+8.0
kV
on pin WAKE_IN_OUT
[5]
-8.0
+8.0
kV
on pin VBAT to GND
[6]
-8.0
+8.0
kV
[7]
-2.0
+2.0
kV
-6.0
+6.0
kV
Human Body Model (HBM)
on any pin
on pins P0_TRX_P, P0_TRX_M, P1_TRX_P,
P1_TRX_M
on pin WAKE_IN_OUT
[8]
-6.0
+6.0
kV
on pin VBAT
[9]
-6.0
+6.0
kV
[10]
-500
+500
V
Charged Device Model (CDM)
on any pin
Tamb
ambient temperature
-40
+125
°C
Tstg
storage temperature
-55
+150
°C
[1]
[2]
[3]
[4]
The device can sustain voltages up to the specified values over the product lifetime, provided applied voltages (including transients) never exceed these
values.
Verified by an external test house according to IEC TS 62228, Section 4.2.4; parameters for standard pulses defined in ISO7637.
Verified by an external test house according to IEC TS 62228, Section 4.3.
Tested with a common mode choke and 100 nF coupling capacitors.
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100BASE-T1 dual/single PHY for automotive Ethernet
[5]
[6]
[7]
[8]
[9]
[10]
Tested with 10 nF capacitor to GND and 10 kΩ in series between the capacitor and the WAKE_IN_OUT pin.
Tested with 100 nF capacitor from VBAT to GND.
According to AEC-Q100-002.
With 10 nF capacitor to GND and 10 kΩ in series between the capacitor and the WAKE_IN_OUT pin.
With 100 nF from VBAT to GND.
According to AEC-Q100-011.
8
Thermal characteristics
Table 34. Thermal characteristics
Symbol
Rth(j-a)
Rth(j-c)
Ψj-top
[1]
[2]
Parameter
Conditions
thermal resistance from junction to ambient
[1]
[2]
thermal resistance from junction to case
thermal characterization parameter from
junction to top of package
[1]
Typ
Unit
LDO disabled (LDO_MODE = 1)
26
K/W
LDO enabled (LDO_MODE = 0)
31
K/W
LDO disabled (LDO_MODE = 1)
3
K/W
LDO enabled (LDO_MODE = 0)
8
K/W
LDO disabled (LDO_MODE = 1)
1
K/W
LDO enabled (LDO_MODE = 0)
6
K/W
HVQFN56 package; in free air
HVQFN56 package; in free air
HVQFN36 package; in free air
According to JEDEC JESD51-2, JESD51-5 and JESD51-7 at natural convection on 2s2p board. Board with two inner copper layers( thickness: 35 μm)
and thermal via array under the exposed pad connected to the first inner copper layer.
Determined using an isothermal cold plate.
9
Static characteristics
Table 35. Supply characteristics
Tvj = -40 °C to +150 °C; VDD(IO) = 2.9 V to 3.5 V; VBAT = 2.8 V to 40 V; VDDA(3V3) = VDDA(TX) = VDDD(3V3) = 2.9 V to 3.5 V; all
voltages are defined with respect to ground unless otherwise specified; positive currents flow into the IC.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
operating range
3.1
-
36
V
Battery supply: pin VBAT
VBAT
battery supply voltage
Vuvd
undervoltage detection voltage
2.8
-
-
V
Vuvr
undervoltage recovery voltage
-
-
3.1
V
Vuvhys
undervoltage hysteresis voltage
15
100
-
mV
IBAT
battery supply current
TJA1102A; all modes except
Sleep; VBAT < 36 V; IINH = 0 μA
-
-
2.7
mA
TJA1102AS; all modes except
Sleep; VBAT < 36 V; IINH = 0 μA
-
-
1.7
mA
Sleep mode; Tvj ≤ 85 °C;
VBAT < 7.4 V
-
150
300
μA
Sleep mode; Tvj ≤ 85 °C;
7.4 V < VBAT < 30 V
-
45
100
μA
VBAT < 40 V; IINH = 0 μA
-
-
6.5
mA
TJA1102A
Product data sheet
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Table 35. Supply characteristics...continued
Tvj = -40 °C to +150 °C; VDD(IO) = 2.9 V to 3.5 V; VBAT = 2.8 V to 40 V; VDDA(3V3) = VDDA(TX) = VDDD(3V3) = 2.9 V to 3.5 V; all
voltages are defined with respect to ground unless otherwise specified; positive currents flow into the IC.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
operating range
3.1
3.3
3.5
V
3.3 V analog supply: pin VDDA(3V3)
VDDA(3V3)
analog supply voltage (3.3 V)
Vuvd
undervoltage detection voltage
2.9
-
-
V
Vuvr
undervoltage recovery voltage
-
-
3.1
V
Vuvhys
undervoltage hysteresis voltage
50
80
-
mV
IDDA(3V3)
analog supply current (3.3 V)
TJA1102A; Normal/Sleep
Request modes
-
43
55
mA
TJA1102AS; Normal/Sleep
Request modes
-
22
27
mA
Standby mode
-
130
250
μA
Disable/Reset modes
-
4
50
μA
operating range
3.1
3.3
3.5
V
3.3 V digital supply: pin VDDD(3V3)
VDDD(3V3)
digital supply voltage (3.3 V)
Vuvd
undervoltage detection voltage
2.9
-
-
V
Vuvr
undervoltage recovery voltage
-
-
3.1
V
Vuvhys
undervoltage hysteresis voltage
50
80
-
mV
IDDD(3V3)
digital supply current (3.3 V)
TJA1102A: Normal/Sleep
Request modes; LDO_MODE = 0
-
100
120
mA
TJA1102AS: Normal/Sleep
Request modes; LDO_MODE = 0
-
51
61
mA
TJA1102A; Normal/Sleep
Request modes; LDO_MODE = 1
-
5
8
mA
TJA1102AS; Normal/Sleep
Request modes; LDO_MODE = 1
-
2.5
4
mA
Standby mode; LDO_MODE = 0
-
0.2
10
mA
Disable/Reset modes
-
1
50
μA
1.8 V digital supply: pin VDDD(1V8)
VDDD(1V8)
digital supply voltage (1.8 V)
operating range; LDO_MODE = 1
1.745
1.84
1.95
V
Vuvd
undervoltage detection voltage
LDO_MODE = 1
1.65
-
-
V
Vuvr
undervoltage recovery voltage
LDO_MODE = 1
-
-
1.745
V
Vuvhys
undervoltage hysteresis voltage
LDO_MODE = 1
IDDD(1V8)
digital supply current (1.8 V)
20
35
-
mV
TJA1102A; Normal/Sleep
Request modes; LDO_MODE = 1
[1]
-
95
115
mA
TJA1102AS; Normal/Sleep
Request modes; LDO_MODE = 1
[1]
-
48
57
mA
3.1
3.3
3.5
V
Transmitter analog supply: pins P0_VDDA(TX) and P1_VDDA(TX)
VDDA(TX)
transmitter analog supply voltage
TJA1102A
Product data sheet
operating range
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100BASE-T1 dual/single PHY for automotive Ethernet
Table 35. Supply characteristics...continued
Tvj = -40 °C to +150 °C; VDD(IO) = 2.9 V to 3.5 V; VBAT = 2.8 V to 40 V; VDDA(3V3) = VDDA(TX) = VDDD(3V3) = 2.9 V to 3.5 V; all
voltages are defined with respect to ground unless otherwise specified; positive currents flow into the IC.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IDDA(TX)
transmitter analog supply current
Normal/Sleep Request modes
-
27
33
mA
Standby/Disable/Reset modes
-
0
50
μA
operating range
3.1
3.3
3.5
V
Input/output supply: pin VDD(IO)
VDD(IO)
input/output supply voltage
Vuvd
undervoltage detection voltage
2.9
-
-
V
Vuvr
undervoltage recovery voltage
-
-
3.1
V
Vuvhys
undervoltage hysteresis voltage
50
80
-
mV
-
10
15
mA
TJA1102AS; Normal/Sleep
Request modes; Cload on MII pins
= 15 pF
-
5
7.5
mA
Standby/Disable modes;
no currents in pull-up resistors on
digital inputs
-
3
40
μA
-
35
80
μA
TJA1102A; Normal/Sleep
Request modes; LDO_MODE = 0
-
700
900
mW
TJA1102AS; Normal/Sleep
Request modes; LDO_MODE = 0
-
360
480
mW
TJA1102A; Normal/Sleep
Request modes; LDO_MODE = 1
-
560
760
mW
TJA1102AS; Normal/Sleep
Request modes; LDO_MODE = 1
-
290
400
mW
IDD(IO)
input/output supply current
TJA1102A; Normal/Sleep
Request modes; Cload on MII pins
= 15 pF
Reset mode; no currents in pullup resistors on digital inputs
[1]
[1]
Power consumption
P
[1]
power dissipation
Not measured in production; guaranteed by design.
Table 36. xMI interfaces characteristics
Tvj = -40 °C to +150 °C; VDD(IO) = 2.9 V to 3.5 V; VBAT = 2.8 V to 40 V; VDDA(3V3) = VDDA(TX) = VDDD(3V3) = 2.9 V to 3.5 V; all
voltages are defined with respect to ground unless otherwise specified; positive currents flow into the IC.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
2
-
-
V
SMI interface: pins MDC and MDIO
VIH
HIGH-level input voltage
VIL
LOW-level input voltage
Ci
input capacitance
TJA1102A
Product data sheet
-
-
0.8
V
pin MDC
[1]
-
-
8
pF
pin MDIO
[1]
-
-
10
pF
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100BASE-T1 dual/single PHY for automotive Ethernet
Table 36. xMI interfaces characteristics...continued
Tvj = -40 °C to +150 °C; VDD(IO) = 2.9 V to 3.5 V; VBAT = 2.8 V to 40 V; VDDA(3V3) = VDDA(TX) = VDDD(3V3) = 2.9 V to 3.5 V; all
voltages are defined with respect to ground unless otherwise specified; positive currents flow into the IC.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VOH
HIGH-level output voltage
pin MDIO; IOH = -4 mA
VDD(IO)
- 0.4
-
-
V
VOL
LOW-level output voltage
pin MDIO; IOL = 4 mA
-
-
0.4
V
IIH
HIGH-level input current
VIH = VDD(IO)
-
-
20
μA
IIL
LOW-level input current
pin MDC; VIL = 0 V
-20
-
-
μA
pin MDIO; Vi = 0 V
-100
-
-20
μA
Rpd
pull-down resistance
on pin MDC
262.5
500
-
kΩ
Rpu
pull-up resistance
on pin MDIO
70
100
130
kΩ
(R)MII interface: pins P0_TXER, P0_TXEN, P0_TXDx, P0_TXC, P0_RXDx, P0_RXDV, P0_RXER, P0_RXC, P1_TXER,
[2]
P1_TXEN, P1_TXDx, P1_TXC, P1_RXDx, P1_RXDV, P1_RXER, P1_RXC
VIH
HIGH-level input voltage
VIL
LOW-level input voltage
[1]
2
-
-
V
-
-
0.8
V
-
-
8
pF
Ci
input capacitance
VOH
HIGH-level output voltage
IOH = -4 mA
VDD(IO)
- 0.4
-
-
V
VOL
LOW-level output voltage
IOL = 4 mA
-
-
0.4
V
IIH
HIGH-level input current
VIH = VDD(IO)
-
-
200
μA
IIL
LOW-level input current
VIL = 0 V
-20
-
-
μA
Rpd
pull-down resistance
on pins P0_TXER, P0_TXEN,
P0_TXDx, P1_TXER, P1_TXEN,
P1_TXDx
70
100
130
kΩ
on pins P0_TXC and P1_TXC;
Reverse MII mode
70
100
130
kΩ
[1]
[2]
Not measured in production; guaranteed by design.
Pins P1_xxx only valid for TJA1102A.
Table 37. General electrical characteristics
Tvj = -40 °C to +150 °C; VDD(IO) = 2.9 V to 3.5 V; VBAT = 2.8 V to 40 V; VDDA(3V3) = VDDA(TX) = VDDD(3V3) = 2.9 V to 3.5 V; all
voltages are defined with respect to ground unless otherwise specified; positive currents flow into the IC.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
pins RST_N, EN
VIH
HIGH-level input voltage
2
-
-
V
VIL
LOW-level input voltage
-
-
0.8
V
Vhys(i)
input hysteresis voltage
0.36
0.5
-
V
-
-
8
pF
[1]
Ci
input capacitance
IIH
HIGH-level input current
at pin RST_N; VIH = VDD(IO)
-
-
20
μA
IIL
LOW-level input current
at pin EN; VIL = 0 V
-20
-
-
μA
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TJA1102A
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100BASE-T1 dual/single PHY for automotive Ethernet
Table 37. General electrical characteristics...continued
Tvj = -40 °C to +150 °C; VDD(IO) = 2.9 V to 3.5 V; VBAT = 2.8 V to 40 V; VDDA(3V3) = VDDA(TX) = VDDD(3V3) = 2.9 V to 3.5 V; all
voltages are defined with respect to ground unless otherwise specified; positive currents flow into the IC.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Rpd
pull-down resistance
on pin EN
70
100
130
kΩ
Rpu
pull-up resistance
on pin RST_N
70
100
130
kΩ
LOW-level output voltage
IOL = 2 mA
-
-
0.4
V
V
pin INT_N
VOL
pin SEL_1V8
VIH
HIGH-level input voltage
0.7 ×
VDD(IO)
-
-
VIL
LOW-level input voltage
-
-
0.3 ×
V
VDD(IO)
Vhys(i)
input hysteresis voltage
0.1 ×
VDD(IO)
-
-
V
IIL
LOW-level input current
VIL = 0 V
-5
-
+5
μA
Rpd
pull-down resistance
on pin SEL_1V8
70
100
130
kΩ
V
pin CLK_IN_OUT
VIH
HIGH-level input voltage
0.7 ×
VDD(IO)
-
-
VIL
LOW-level input voltage
-
-
0.3 ×
V
VDD(IO)
Vhys(i)
input hysteresis voltage
0.1 ×
VDD(IO)
-
-
V
VOH
HIGH-level output voltage
CLK_MODE = 01; IOH = -4 mA
VDD(IO)
- 0.4
-
-
V
VOL
LOW-level output voltage
CLK_MODE = 01; IOL = 4 mA
-
-
0.4
V
IIL
LOW-level input current
CLK_MODE = 00 or 11; VIL = 0 V
-5
-
+5
μA
Rpd
pull-down resistance
CLK_MODE = 00 or 11
70
100
130
kΩ
[2]
pins P0_RXD[3:0], P0_RXER, P0_RXDV, P1_RXD[3:0], P1_RXER, P1_RXDV during pin strapping
VIH
HIGH-level input voltage
2
-
-
V
VIL
LOW-level input voltage
-
-
0.8
V
CONFIG_WAKE = 0 (see Table
29)
2.8
-
4.1
V
CONFIG_WAKE = 1
0.44 ×
VDD(IO)
-
0.64 × V
VDD(IO)
CONFIG_WAKE = 0
2.4
-
3.75
CONFIG_WAKE = 1
0.38 ×
VDD(IO)
-
0.55 × V
VDD(IO)
CONFIG_WAKE = 0
0.25
-
0.8
pin WAKE_IN_OUT
VIH
VIL
Vhys(i)
HIGH-level input voltage
LOW-level input voltage
input hysteresis voltage
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TJA1102A
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100BASE-T1 dual/single PHY for automotive Ethernet
Table 37. General electrical characteristics...continued
Tvj = -40 °C to +150 °C; VDD(IO) = 2.9 V to 3.5 V; VBAT = 2.8 V to 40 V; VDDA(3V3) = VDDA(TX) = VDDD(3V3) = 2.9 V to 3.5 V; all
voltages are defined with respect to ground unless otherwise specified; positive currents flow into the IC.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
CONFIG_WAKE = 1
0.025 × VDD(IO)
0.2 ×
V
VDD(IO)
-5
-
+5
μA
Ii
input current
VOH
HIGH-level output voltage
all modes except Sleep and
Power-off; IWAKE_IN_OUT = 0 mA
VBAT 0.8
-
VBAT
V
IOL
LOW-level output current
all modes except Sleep, Poweroff; VWAKE_IN_OUT = 0 V
-30
-
-
mA
VOH
HIGH-level output voltage
all modes except Sleep, Poweroff; IINH = -1 mA
VBAT - 1 -
VBAT
V
IOL
LOW-level output current
all modes except Sleep, Poweroff; VINH = 0 V
-15
-7
-2
mA
IL
leakage current
Sleep, Power-off modes
-5
-
+5
μA
input capacitance
pin XI
[1]
-
3.5
-
pF
pin XO
[1]
-
2
-
pF
13.3
25
47
mA/V
pin INH
pins XI, XO
Ci
gm(DC)
DC transconductance
Normal, Sleep Request modes;
MII_MODE = 00, 01 or 11
Transmitter test results: pins P0_TRX_M, P0_TRX_P, P1_TRX_M, P1_TRX_P
[3]
Vdroop/VM
droop voltage to peak voltage
ratio
100BASE-T1 test mode 1; with
respect to initial peak value
[1]
-45
-
+45
%
Vdist(M)
peak distortion voltage
100BASE-T1 test mode 4
[1]
-
-
15
mV
100BASE-T1 test mode 5
[1]
f = 1 MHz
-70.9
-
-63.3
dBm/
Hz
f = 20 MHz
-75.8
-
-64.8
dBm/
Hz
f = 40 MHz
-89.2
-
-68.5
dBm/
Hz
f = 57 MHz to 200 MHz
-
-
-76.5
dBm/
Hz
-
1
-
V
47.5
50
52.5
Ω
180
-
200
°C
PSDM
power spectral density mask
Transmitter output amplitude: pins P0_TRX_M, P0_TRX_P, P1_TRX_M, P1_TRX_P
VoM(TX)
Rterm
[2][3]
transmitter peak output voltage
termination resistance
on each pin; Normal, Sleep
Request modes; LINK_
CONTROL = 1
[4]
Temperature protection
Tj(sd)
shutdown junction temperature
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TJA1102A
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100BASE-T1 dual/single PHY for automotive Ethernet
Table 37. General electrical characteristics...continued
Tvj = -40 °C to +150 °C; VDD(IO) = 2.9 V to 3.5 V; VBAT = 2.8 V to 40 V; VDDA(3V3) = VDDA(TX) = VDDD(3V3) = 2.9 V to 3.5 V; all
voltages are defined with respect to ground unless otherwise specified; positive currents flow into the IC.
Symbol
Parameter
Tj(sd)rel
Min
Typ
Max
Unit
release shutdown junction
temperature
147
-
167
°C
Tj(warn)
warning junction temperature
155
-
175
°C
Tj(warn)rel
release warning junction
temperature
147
-
167
°C
Tj(warn)hys
warning junction temperature
hysteresis
2
8
-
°C
[1]
[2]
[3]
[4]
Conditions
Not measured in production; guaranteed by design.
Pins P1_xxx only valid for TJA1102A.
Test carried out with external common mode choke and coupling capacitors connected.
Includes the influence of the nominal series resistance of an external common mode choke and 1 kΩ parallel resistors of the common-mode termination
circuit.
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TJA1102A
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100BASE-T1 dual/single PHY for automotive Ethernet
10 Dynamic characteristics
Table 38. Dynamic characteristics
Tvj = -40 °C to +150 °C; VDD(IO) = 2.9 V to 3.5 V; VBAT = 2.8 V to 40 V; VDDA(3V3) = VDDA(TX) = VDDD(3V3) = 2.9 V to 3.5 V; all
voltages are defined with respect to ground unless otherwise specified; positive currents flow into the IC.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
[1]
MII transmit timing (see Figure 15); MII_DRIVER = 0 (standard output driver strength)
Tclk
clock period
pin TXC
-
40
-
ns
δ
duty cycle
pin TXC
35
-
65
%
tWH
pulse width HIGH
pin TXC
14
20
-
ns
tWL
pulse width LOW
pin TXC
14
20
-
ns
tsu
set-up time
TXC to TXD[3:0], TXER, TXEN
MII
10
-
-
ns
Reverse MII
10
-
-
ns
0
-
-
ns
10
-
-
ns
th
hold time
TXC to TXD[3:0], TXEN, TXER
MII
Reverse MII
MII receive timing (see Figure 16); MII_DRIVER = 0 (standard output driver strength)
[1]
Tclk
clock period
pin RXC
-
40
-
ns
δ
duty cycle
pin RXC
35
-
65
%
tWH
pulse width HIGH
pin RXC
14
20
-
ns
tWL
pulse width LOW
pin RXC
14
20
-
ns
td
delay time
RXC to RXD[3:0], RXDV, RXER
MII
15
-
25
ns
Reverse MII
0
-
25
RMII transmit and receive timing (see Figure 17 and Figure 18); MII_DRIVER = 0 (standard output driver strength)
ns
[1]
Tclk
clock period
pin REF_CLK
-
20
-
ns
δ
duty cycle
pin REF_CLK
35
-
65
%
tWH
pulse width HIGH
pin REF_CLK
7
10
-
ns
tWL
pulse width LOW
pin REF_CLK
7
10
-
ns
tsu
set-up time
REF_CLK to TXD[1:0], TXEN, TXER
4
-
-
ns
th
hold time
REF_CLK to TXD[1:0], TXEN, TXER
2
-
-
ns
td
delay time
REF_CLK to RXD[1:0], RXER, CRSDV
4
-
13
ns
MII_DRIVER = 0; CL = 15 pF
1.3
-
5
ns
MII_DRIVER = 1; CL = 7.5 pF
2
-
7.7
ns
1.3
-
5
ns
(R)MII interface timing
tf
fall time
[1]
[2]
MII: RXD[3:0], RXDV, RXER
MII: TXC, RXC; CL = 15 pF
RMII: RXD[1:0], CRSDV, RXER
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TJA1102A
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100BASE-T1 dual/single PHY for automotive Ethernet
Table 38. Dynamic characteristics...continued
Tvj = -40 °C to +150 °C; VDD(IO) = 2.9 V to 3.5 V; VBAT = 2.8 V to 40 V; VDDA(3V3) = VDDA(TX) = VDDD(3V3) = 2.9 V to 3.5 V; all
voltages are defined with respect to ground unless otherwise specified; positive currents flow into the IC.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
MII_DRIVER = 0; CL = 15 pF
0.7
-
2.5
ns
MII_DRIVER = 1; CL = 7.5 pF
0.9
-
3.4
ns
0.7
-
2.5
ns
MII_DRIVER = 0; CL = 15 pF
1.3
-
5
ns
MII_DRIVER = 1; CL = 7.5 pF
2
-
7.7
ns
1.3
-
5
ns
MII_DRIVER = 0; CL = 15 pF
0.7
-
2.5
ns
MII_DRIVER = 1; CL = 7.5 pF
0.9
-
3.4
ns
0.7
-
2.5
ns
RMII: REF_CLK; CL = 15 pF
tr
rise time
[3]
MII: RXD[3:0], RXDV, RXER
MII: TXC, RXC; CL = 15 pF
RMII: RXD[1:0], CRSDV, RXER
RMII: REF_CLK; CL = 15 pF
SMI timing (see Figure 19)
[1]
Tclk(MDC)
MDC clock period
400
-
-
ns
tWH(MDC)
MDC pulse width HIGH
160
-
-
ns
tWL(MDC)
MDC pulse width LOW
160
-
-
ns
tsu(MDIO)
MDIO set-up time
to rising edge on MDC
10
-
-
ns
th(MDIO)
MDIO hold time
from rising edge on MDC
10
-
-
ns
td(MDC-MDIO)
delay time from MDC to MDIO
from rising edge on MDC; read from
PHY
0
-
300
ns
LOC_WU_TIM = 00
10
-
20
ms
LOC_WU_TIM = 01
250
-
500
μs
LOC_WU_TIM = 10
100
-
200
μs
LOC_WU_TIM = 11
20
-
40
μs
LOC_WU_TIM = 00
20
-
40
ms
LOC_WU_TIM = 01
500
-
1000
μs
LOC_WU_TIM = 10
200
-
400
μs
LOC_WU_TIM = 11
40
-
80
μs
[1]
WAKE timing; pin WAKE_IN_OUT
tdet(wake)
wake-up detection time
tp
pulse duration
ton
turn-on time
RL = 100 kΩ; CL = 50 pF; VWAKE_IN_OUT
=2V
0
2
50
μs
toff
turn-off time
RL = 100 kΩ; CL = 50 pF; VWAKE_IN_OUT
=2V
5
50
65
μs
[1]
INH timing ; pin INH
ton
turn-on time
RL = 100 kΩ; CL = 50 pF; Vth(INH) = 2 V
0
2
50
μs
toff
turn-off time
RL = 100 kΩ; CL = 50 pF; Vth(INH) = 2 V
5
50
65
μs
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TJA1102A
NXP Semiconductors
100BASE-T1 dual/single PHY for automotive Ethernet
Table 38. Dynamic characteristics...continued
Tvj = -40 °C to +150 °C; VDD(IO) = 2.9 V to 3.5 V; VBAT = 2.8 V to 40 V; VDDA(3V3) = VDDA(TX) = VDDD(3V3) = 2.9 V to 3.5 V; all
voltages are defined with respect to ground unless otherwise specified; positive currents flow into the IC.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
[1]
interrupt timing ; pin INT_N
ton
turn-on time
Rpu = 10 kΩ; CL = 15 pF
8
-
20
μs
toff
turn-off time
Rpu = 10 kΩ; CL = 15 pF
8
-
20
μs
JUMBO_ENABLE = 0
-
1.1
-
ms
JUMBO_ENABLE = 1
-
2.2
-
ms
Normal mode; CABLE_TEST = 1
-
100
-
μs
PCS-RX timeout timing
[4]
tto(PCS-RX)
Normal and Sleep Request modes
PCS-RX time-out time
Cable test timing
tto(cbl_tst)
cable test time-out time
[1]
pins RST_N, EN
tdet(rst)
reset detection time
on pin RSTN;
Vuvd(VDDIO) < VDD(IO) ≤ 3.5 V
5
-
20
μs
tdet(EN)
detection time on pin EN
Vuvd(VDDIO) < VDD(IO) ≤ 3.5 V
5
-
20
μs
-
-
50
ps
-
-
150
ps
on pin VBAT; VBAT = 2.7 V
0
-
30
μs
on pin VDDA(3V3); VDDA(3V3) = 2.8 V
2
-
30
μs
on pin VDDD(3V3); VDDD(3V3) = 2.8 V
2
-
30
μs
on pin VDDD(1V8)
2
-
30
μs
VDD(IO) = 2.8 V
2
-
30
μs
on pin VDDA(3V3); VDDA(3V3) = 3.2 V
2
-
30
μs
on pin VDDD(3V3); VDDD(3V3) = 3.2 V
2
-
30
μs
on pin VDDD(1V8)
2
-
30
μs
on pin VDD(IO); VDD(IO) = 3.2 V
2
-
30
μs
for transition from Standby to Sleep
mode (see Section 6.9.1)
300
-
670
ms
Transmitter test results
tjit(RMS)
Master mode
RMS jitter time
Slave mode (with link); SLAVE_
JITTER_TEST = 1
Undervoltage detection
tdet(uv)
trec(uv)
tto(uvd)
[1]
[5]
[1]
undervoltage detection time
undervoltage recovery time
undervoltage detection time-out
time
[1]
General timing parameters
ts(pon)
power-on settling time
from power-on to Standby mode
-
-
2
ms
tinit(PHY)
PHY initialization time
from Standby mode to Normal mode
-
-
2
ms
tto(req)sleep
sleep request time-out time
SLEEP_REQUEST_TO = 00
360
-
500
μs
SLEEP_REQUEST_TO = 01
900
-
1150
μs
SLEEP_REQUEST_TO = 10
3.6
-
4.4
ms
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TJA1102A
NXP Semiconductors
100BASE-T1 dual/single PHY for automotive Ethernet
Table 38. Dynamic characteristics...continued
Tvj = -40 °C to +150 °C; VDD(IO) = 2.9 V to 3.5 V; VBAT = 2.8 V to 40 V; VDDA(3V3) = VDDA(TX) = VDDD(3V3) = 2.9 V to 3.5 V; all
voltages are defined with respect to ground unless otherwise specified; positive currents flow into the IC.
Symbol
tto(ack)sleep
Parameter
sleep acknowledge time-out time
Conditions
Min
Typ
Max
Unit
SLEEP_REQUEST_TO = 11
14.4
-
17.6
ms
SLEEP_REQUEST_TO = 00
180
-
250
μs
SLEEP_REQUEST_TO = 01
450
-
575
μs
SLEEP_REQUEST_TO = 10
1.8
-
2.2
ms
7.2
-
8.8
ms
-
-
0.7
ms
SLEEP_REQUEST_TO = 11
[6]
tdet(PHY)
PHY detection time
on bus pins P0_TRX_P, P0_TRX_M,
P1_TRX_P and P1_TRX_M
tto(pd)autn
autonomous power-down time-out
time
Normal mode; AUTO_PWD = 1
1
-
2
s
tPD
propagation delay
from MII to MDI; Normal mode
140
-
300
ns
from MDI to MII; Normal mode
760
-
920
ns
from RMII to MDI; Normal mode
190
-
540
ns
from MDI to RMII; Normal mode
700
-
1070
ns
Normal mode; no active link; wake-up
forwarding
0.7
1.0
1.3
ms
tw(wake)
[1]
[2]
[3]
[4]
[5]
[6]
wake-up pulse width
Not measured in production; guaranteed by design.
From 2 V to 0.8 V.
From 0.8 V to 2 V.
rcv_max_timer in the IEEE specificatio [1].
Measured at the P0_RXER pin, representing the transmit clock (TX_CLK) of P1, or measured at the P1_RXER pin, representing the transmit clock of P0.
Pins P1_xxx only valid for TJA1102A.
Tclk(TXC)
tWH(TXC)
tWL(TXC)
TXC
tsu(MII)
tsu(MII)
th(MII)
th(MII)
TXEN
TXD[3:0]
TXER
aaa-038936
Figure 15. MII transmit timing diagram
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TJA1102A
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100BASE-T1 dual/single PHY for automotive Ethernet
Tclk(RXC)
tWH(RXC)
tWL(RXC)
RXC
td(MIIrx)
td(MIIrx)
RXDV
td(MIIrx)
td(MIIrx)
RXD[3:0]
RXER
aaa-038937
Figure 16. MII receive timing diagram
tWH(REF_CLK) tWL(REF_CLK)
Tclk(REF_CLK)
REF_CLK
tsu(RMII)
th(RMII)
tsu(RMII)
th(RMII)
TXEN
TXD[1:0]
aaa-038938
Figure 17. RMII transmit timing diagram
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TJA1102A
NXP Semiconductors
100BASE-T1 dual/single PHY for automotive Ethernet
Tclk(REF_CLK)
REF_CLK
td(RMIIrx)
td(RMIIrx)
CRSDV
RXER
RXD[1:0]
aaa-038939
Figure 18. RMII receive timing diagram
tWH(MDC)
Tclk(MDC)
tWL(MDC)
MDC
td(MDC-MDIO)
td(MDC-MDIO)
MDIO
(Data-out)
tsu(MDIO) th(MDIO)
MDIO
(Data-in)
aaa-038940
Figure 19. SMI timing diagram
11 Application information
The MDI circuit used for each PHY port is shown in Figure 20. The common mode
termination depends on OEM requirements and might vary, depending on the application.
The common mode choke is expected to be compliant with the OPEN Alliance CMC
specification. The 100 nF coupling capacitors should have a voltage range ≥ 50 V with
10 % (max) tolerance.
The TJA1102A provides an ESD robustness of ±6 kV according to IEC61000-4-2 and
HBM at the IC pins. With CMC and coupling capacitors, it is able to withstand ≥ ±8 kV for
IEC 61000-4-2 on the connector pins.
TJA1102A
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TJA1102A
NXP Semiconductors
100BASE-T1 dual/single PHY for automotive Ethernet
common
mode choke
TRX_P
PHY
100 nF
BI_DA+
TRX_M
200 µH
according to
OPEN Alliance CMC Spec
BI_DA100 nF
1 kΩ
100 kΩ
1 kΩ
4.7 nF
optional
according to OPEN Alliance
System Implementation Spec
aaa-022043
Figure 20. MDI circuit diagram
Further information can be found in the TJA1102A application hints [2].
12 Package information
The TJA1102A comes in the HVQFN-56 package as shown in Figure 21. Measuring
2
just 64 mm with a pitch of 0.5 mm, it is particularly suited to PCB space-constrained
applications, such as an integrated IP camera module. The package features wettable
sides/flanks to allow for optical inspection of the soldering process. The exposed die pad
shown in the package diagram must be connected to ground.
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13 Package outline
HVQFN56: plastic thermal enhanced very thin quad flat package; no leads;
56 terminals; body 8 x 8 x 0.85 mm
D
B
SOT684-13
A
terminal 1
index area
E
A
A1
c
detail X
e1
e
L
v
w
b
1/2 e
C
y1 C
b1
15
y
28
29
14
K
C A B
C
e
Eh
e2
1/2 e
1
terminal 1
index area
42
56
43
K
X
Dh
0
5
Dimensions (mm are the original dimensions)
Unit
mm
A(1)
A1
b
b1
max 1.00 0.05 0.30 0.32
nom 0.85 0.02 0.25 0.27
min 0.80 0.00 0.20 0.22
10 mm
scale
c
D(1)
Dh
E(1)
Eh
e
e1
e2
L
K
0.2
8.1
8.0
7.9
5.15
5.00
4.85
8.1
8.0
7.9
5.15
5.00
4.85
0.5
6.5
6.5
0.6
0.5
0.4
0.8
v
0.1
w
y
0.05 0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
Outline
version
SOT684-13
References
IEC
JEDEC
JEITA
y1
0.1
sot684-13_po
European
projection
Issue date
15-05-29
15-07-13
---
Figure 21. Package outline SOT684-13 (HVQFN56)
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14 Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
14.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached
to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides
both the mechanical and the electrical connection. There is no single soldering method
that is ideal for all IC packages. Wave soldering is often preferred when through-hole
and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is
not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
14.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming
from a standing wave of liquid solder. The wave soldering process is suitable for the
following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
14.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
14.4 Reflow soldering
Key characteristics in reflow soldering are:
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100BASE-T1 dual/single PHY for automotive Ethernet
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads
to higher minimum peak temperatures (see Figure 22) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board
is heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder
paste characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 39 and Table 40
Table 39. SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm³)
< 350
≥ 350
< 2.5
235
220
≥ 2.5
220
220
Table 40. Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm³)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 22.
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100BASE-T1 dual/single PHY for automotive Ethernet
temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Figure 22. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
15 References
[1] IEEE 802.3bw-2015 — IEEE Standard for Ethernet Amendment 1: Physical Layer Specifications and Management
Parameters for 100 Mb/s Operation over a Single Balanced Twisted Pair Cable (100BASET1)
[2] AN13171
— Application note for TJA1102A 100BASE-T1 dual/single PHY for automotive Ethernet, NXP
Semiconductors
16 Revision history
Table 41. Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
TJA1102A v.1
20210607
Product data sheet
-
-
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17 Legal information
17.1 Data sheet status
Document status
[1][2]
Product status
[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
17.2 Definitions
Draft — A draft status on a document indicates that the content is still
under internal review and subject to formal approval, which may result
in modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included in a draft version of a document and shall have no
liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the
relevant full data sheet, which is available on request via the local NXP
Semiconductors sales office. In case of any inconsistency or conflict with the
short data sheet, the full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product
is deemed to offer functions and qualities beyond those described in the
Product data sheet.
17.3 Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, NXP Semiconductors does not
give any representations or warranties, expressed or implied, as to the
accuracy or completeness of such information and shall have no liability
for the consequences of use of such information. NXP Semiconductors
takes no responsibility for the content in this document if provided by an
information source outside of NXP Semiconductors. In no event shall NXP
Semiconductors be liable for any indirect, incidental, punitive, special or
consequential damages (including - without limitation - lost profits, lost
savings, business interruption, costs related to the removal or replacement
of any products or rework charges) whether or not such damages are based
on tort (including negligence), warranty, breach of contract or any other
legal theory. Notwithstanding any damages that customer might incur for
any reason whatsoever, NXP Semiconductors’ aggregate and cumulative
liability towards customer for the products described herein shall be limited
in accordance with the Terms and conditions of commercial sale of NXP
Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
TJA1102A
Product data sheet
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes
no representation or warranty that such applications will be suitable
for the specified use without further testing or modification. Customers
are responsible for the design and operation of their applications and
products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications
and products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with
their applications and products. NXP Semiconductors does not accept any
liability related to any default, damage, costs or problem which is based
on any weakness or default in the customer’s applications or products, or
the application or use by customer’s third party customer(s). Customer is
responsible for doing all necessary testing for the customer’s applications
and products using NXP Semiconductors products in order to avoid a
default of the applications and the products or of the application or use by
customer’s third party customer(s). NXP does not accept any liability in this
respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or
the grant, conveyance or implication of any license under any copyrights,
patents or other industrial or intellectual property rights.
Suitability for use in automotive applications — This NXP product has
been qualified for use in automotive applications. If this product is used
by customer in the development of, or for incorporation into, products or
services (a) used in safety critical applications or (b) in which failure could
lead to death, personal injury, or severe physical or environmental damage
(such products and services hereinafter referred to as “Critical Applications”),
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then customer makes the ultimate design decisions regarding its products
and is solely responsible for compliance with all legal, regulatory, safety,
and security related requirements concerning its products, regardless of
any information or support that may be provided by NXP. As such, customer
assumes all risk related to use of any products in Critical Applications and
NXP and its suppliers shall not be liable for any such use by customer.
Accordingly, customer will indemnify and hold NXP harmless from any
claims, liabilities, damages and associated costs and expenses (including
attorneys’ fees) that NXP may incur related to customer’s incorporation of
any product in a Critical Application.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Security — Customer understands that all NXP products may be subject
to unidentified or documented vulnerabilities. Customer is responsible
for the design and operation of its applications and products throughout
TJA1102A
Product data sheet
their lifecycles to reduce the effect of these vulnerabilities on customer’s
applications and products. Customer’s responsibility also extends to other
open and/or proprietary technologies supported by NXP products for use
in customer’s applications. NXP accepts no liability for any vulnerability.
Customer should regularly check security updates from NXP and follow up
appropriately. Customer shall select products with security features that best
meet rules, regulations, and standards of the intended application and make
the ultimate design decisions regarding its products and is solely responsible
for compliance with all legal, regulatory, and security related requirements
concerning its products, regardless of any information or support that may
be provided by NXP. NXP has a Product Security Incident Response Team
(PSIRT) (reachable at PSIRT@nxp.com) that manages the investigation,
reporting, and solution release to security vulnerabilities of NXP products.
17.4 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
NXP — wordmark and logo are trademarks of NXP B.V.
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Contents
1
2
2.1
2.2
2.3
2.4
2.5
3
4
5
5.1
5.2
6
6.1
6.1.1
6.1.2
6.2
6.2.1
6.2.2
6.2.2.1
6.2.3
6.3
6.3.1
6.3.1.1
6.3.1.2
6.3.1.3
6.3.1.4
6.3.1.5
6.3.1.6
6.3.1.7
6.3.1.8
6.3.2
6.4
6.5
6.6
6.7
6.8
6.8.1
6.8.2
6.8.3
6.8.4
6.8.5
6.8.6
6.9
6.9.1
6.9.2
6.9.3
6.9.4
6.9.5
General description ............................................ 1
Features and benefits .........................................1
General .............................................................. 1
Optimized for automotive use cases ..................1
Low-power mode ............................................... 2
Diagnosis ........................................................... 2
Miscellaneous .................................................... 2
Ordering information .......................................... 2
Block diagram ..................................................... 2
Pinning information ............................................ 4
TJA1102A pinning ..............................................4
TJA1102AS pinning ........................................... 8
Functional description ......................................11
System configuration ....................................... 11
Clocking scheme with MII and clock
provided by the switch and one of the
TJA1102A devices ........................................... 12
Clocking scheme with RMII and clock
provided by the switch .....................................13
MII and RMII ....................................................13
MII .................................................................... 14
RMII ................................................................. 15
Signaling and encoding ................................... 15
Reverse MII ..................................................... 16
System controller ............................................. 17
Operating modes ............................................. 17
Power-off mode ............................................... 17
Standby mode ................................................. 17
Normal mode ................................................... 18
Disable mode ...................................................18
Sleep mode ..................................................... 18
Sleep Request mode ....................................... 19
Silent mode ......................................................19
Reset mode ..................................................... 20
Status of functional blocks in TJA1102A
operating modes .............................................. 20
Mode transitions .............................................. 21
Sleep and wake-up forwarding concept ...........23
Autonomous operation .....................................24
Autonomous power-down ................................ 24
Test modes ...................................................... 24
Test mode 1 .....................................................24
Test mode 2 .....................................................24
Test mode 3 .....................................................24
Test mode 4 .....................................................24
Test mode 5 .....................................................25
Slave jitter test .................................................25
Error diagnosis ................................................ 25
Undervoltage detection ....................................25
Cabling errors .................................................. 26
Link stability ..................................................... 26
Link-fail counter ............................................... 26
Jabber detection .............................................. 27
6.9.6
6.9.7
6.9.8
6.9.8.1
6.9.8.2
6.9.8.3
6.10
6.11
6.11.1
6.11.2
7
8
9
10
11
12
13
14
14.1
14.2
14.3
14.4
15
16
17
Polarity detection ............................................. 27
Interleave detection ......................................... 27
Loopback modes ............................................. 27
Internal loopback ............................................. 27
External loopback ............................................ 28
Remote loopback .............................................28
Hardware configuration ....................................28
SMI registers ................................................... 30
Register mapping overview ............................. 30
TJA1102A registers ......................................... 31
Limiting values .................................................. 46
Thermal characteristics ....................................47
Static characteristics ........................................ 47
Dynamic characteristics ...................................54
Application information .................................... 59
Package information .........................................60
Package outline .................................................61
Soldering of SMD packages .............................62
Introduction to soldering .............................
Wave and reflow soldering .........................
Wave soldering ...........................................
Reflow soldering .........................................
References ......................................................... 64
Revision history ................................................ 64
Legal information .............................................. 65
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.
© NXP B.V. 2021.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 7 June 2021
Document identifier: TJA1102A
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