CAT24C128HU4IGT3

EEPROM Serial 128-Kb I2C CAT24C128 Description The CAT24C128 is a EEPROM Serial 128−Kb I2C internally organized as 16,384 words of 8 bits each. It features a 64−byte page write buffer and supports both the Standard (100 kHz), Fast (400 kHz) and Fast−Plus (1 MHz) I2C protocol. Write operations can be inhibited by taking the WP pin High (this protects the entire memory). On−Chip ECC (Error Correction Code) makes the device suitable for high reliability applications.* www.onsemi.com UDFN−8 HU4 SUFFIX CASE 517AZ Features • • • • • • • • • • Supports Standard, Fast and Fast−Plus I2C Protocol 1.8 V to 5.5 V Supply Voltage Range 64−Byte Page Write Buffer Hardware Write Protection for Entire Memory Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs (SCL and SDA) Low Power CMOS Technology 1,000,000 Program/Erase Cycles 100 Year Data Retention Industrial and Extended Temperature Range This Device is Pb−Free, Halogen Free/BFR Free and RoHS Compliant** TSSOP−8 Y SUFFIX CASE 948AL SOIC−8 WIDE X SUFFIX CASE 751BE SOIC−8 W SUFFIX CASE 751BD PIN CONFIGURATION 1 VCC A0 VCC A1 WP A2 SCL VSS SDA SOIC (W), TSSOP (Y), UDFN (HU4) SCL CAT24C128 A2, A1, A0 For the location of Pin 1, please consult the corresponding package drawing. SDA WP PIN FUNCTION Pin Name† A0, A1, A2 VSS Figure 1. Functional Symbol ** For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Function Device Address Inputs SDA Serial Data Input/Output SCL Serial Clock Input WP Write Protect Input VCC Power Supply VSS Ground †The exposed pad for the TDFN/UDFN packages can be left floating or connected to Ground. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. © Semiconductor Components Industries, LLC, 2013 July, 2020 − Rev. 17 1 Publication Order Number: CAT24C128/D CAT24C128 Table 1. ABSOLUTE MAXIMUM RATINGS Parameter Rating Units Storage Temperature −65 to +150 °C Voltage on Any Pin with Respect to Ground (Note 1) −0.5 to +6.5 V Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns. Table 2. RELIABILITY CHARACTERISTICS (Note 2) Symbol NEND (Notes 3, 4) TDR Parameter Endurance Data Retention Min Units 1,000,000 Program / Erase Cycles 100 Years 2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100 and JEDEC test methods. 3. Page Mode, VCC = 5 V, 25°C 4. The new product revision (C) uses ECC (Error Correction Code) logic with 6 ECC bits to correct one bit error in 4 data bytes. Therefore, when a single byte has to be written, 4 bytes (including the ECC bits) are re−programmed. It is recommended to write by multiple of 4 bytes in order to benefit from the maximum number of write cycles. www.onsemi.com 2 CAT24C128 Table 3. D.C. OPERATING CHARACTERISTICS (VCC = 1.8 V to 5.5 V, TA = −40°C to +85°C and VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.) Symbol Parameter ICCR Read Current ICCW Write Current ISB IL Standby Current Test Conditions Min Max Units 1 mA 3 mA TA = −40°C to +85°C 2 mA TA = −40°C to +125°C 5 TA = −40°C to +85°C 1 Read, fSCL = 400 kHz/1 MHz All I/O Pins at GND or VCC I/O Pin Leakage Pin at GND or VCC VIL1 Input Low Voltage 2.5 V ≤ VCC ≤ 5.5 V −0.5 0.3 VCC V VIL2 Input Low Voltage 1.8 V ≤ VCC < 2.5 V −0.5 0.25 VCC V VIH1 Input High Voltage 2.5 V ≤ VCC ≤ 5.5 V 0.7 VCC VCC + 0.5 V VIH2 Input High Voltage 1.8 V ≤ VCC < 2.5 V 0.75 VCC VCC + 0.5 V VOL1 Output Low Voltage VCC ≥ 2.5 V, IOL = 3.0 mA 0.4 V VOL2 Output Low Voltage VCC < 2.5 V, IOL = 1.0 mA 0.2 V TA = −40°C to +125°C mA 2 Table 4. PIN IMPEDANCE CHARACTERISTICS (VCC = 1.8 V to 5.5 V, TA = −40°C to +85°C and VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.) Symbol Parameter Conditions Max Units 8 pF CIN (Note 5) SDA I/O Pin Capacitance VIN = 0 V CIN (Note 5) Input Capacitance (other pins) VIN = 0 V 6 pF WP Input Current, Address Input Current (A0, A1, A2) VIN < VIH, VCC = 5.5 V 75 mA VIN < VIH, VCC = 3.3 V 50 VIN < VIH, VCC = 1.8 V 25 VIN > VIH 2 IWP, IA (Note 6) 5. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100 and JEDEC test methods. 6. When not driven, the WP, A0, A1, A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively strong; therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power, as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull−down reverts to a weak current source. www.onsemi.com 3 CAT24C128 Table 5. A.C. CHARACTERISTICS (VCC = 1.8 V to 5.5 V, TA = −40°C to +85°C and VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C) (Note 7) Standard VCC = 1.8 V − 5.5 V Parameter Symbol FSCL tHD:STA Min Max Clock Frequency Fast VCC = 1.8 V − 5.5 V Min 100 START Condition Hold Time Max Fast−Plus (Note 10) VCC = 2.5 V − 5.5 V TA = −405C to +855C Min 400 Max Units 1,000 kHz 4 0.6 0.25 ms tLOW Low Period of SCL Clock 4.7 1.3 0.45 ms tHIGH High Period of SCL Clock 4 0.6 0.40 ms 4.7 0.6 0.25 ms tSU:STA START Condition Setup Time tHD:DAT Data In Hold Time 0 0 0 ms tSU:DAT Data In Setup Time 250 100 50 ns tR (Note 8) SDA and SCL Rise Time 1,000 300 100 ns tF (Note 8) SDA and SCL Fall Time 300 300 100 ns tSU:STO STOP Condition Setup Time tBUF Bus Free Time Between STOP and START tAA SCL Low to Data Out Valid tDH Data Out Hold Time Ti (Note 8) 4 0.6 0.25 ms 4.7 1.3 0.5 ms 3.5 100 0.9 100 Noise Pulse Filtered at SCL and SDA Inputs 100 0.40 50 100 ms ns 50 ns tSU:WP WP Setup Time 0 0 0 ms tHD:WP WP Hold Time 2.5 2.5 1 ms tWR tPU (Notes 8, 9) Write Cycle Time 5 5 Power-up to Ready Mode 1 1 0.1 5 ms 1 ms 7. Test conditions according to “A.C. Test Conditions” table. 8. Tested initially and after a design or process change that affects this parameter. 9. tPU is the delay between the time VCC is stable and the device is ready to accept commands. 10. Fast−Plus (1 MHz) speed class available for new product revision “C”. The die revision “C” is identified by letter “C” or a dedicated marking code on top of the package. Table 6. A.C. TEST CONDITIONS Input Levels 0.2 x VCC to 0.8 x VCC Input Rise and Fall Times v 50 ns Input Reference Levels 0.3 x VCC, 0.7 x VCC Output Reference Levels 0.5 x VCC Output Load Current Source: IOL = 3 mA (VCC ≥ 2.5 V); IOL = 1 mA (VCC < 2.5 V); CL = 100 pF www.onsemi.com 4 CAT24C128 Power−On Reset (POR) The CAT24C128 incorporates Power−On Reset (POR) circuitry which protects the device against powering up in the wrong state. The CAT24C128 will power up into Standby mode after VCC exceeds the POR trigger level and will power down into Reset mode when VCC drops below the POR trigger level. This bi−directional POR feature protects the device against ‘brown−out’ failure following a temporary loss of power. resistors. Master and Slave devices connect to the 2−wire bus via their respective SCL and SDA pins. The transmitting device pulls down the SDA line to ‘transmit’ a ‘0’ and releases it to ‘transmit’ a ‘1’. Data transfer may be initiated only when the bus is not busy (see A.C. Characteristics). During data transfer, the SDA line must remain stable while the SCL line is HIGH. An SDA transition while SCL is HIGH will be interpreted as a START or STOP condition (Figure 2). The START condition precedes all commands. It consists of a HIGH to LOW transition on SDA while SCL is HIGH. The START acts as a ‘wake−up’ call to all receivers. Absent a START, a Slave will not respond to commands. The STOP condition completes all commands. It consists of a LOW to HIGH transition on SDA while SCL is HIGH. Pin Description SCL: The Serial Clock input pin accepts the Serial Clock generated by the Master. SDA: The Serial Data I/O pin receives input data and transmits data stored in EEPROM. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and is delivered on the negative edge of SCL. A0, A1 and A2: The Address pins accept the device address. When not driven, these pins are pulled LOW internally. WP: The Write Protect input pin inhibits all write operations, when pulled HIGH. When not driven, this pin is pulled LOW internally. Device Addressing The Master initiates data transfer by creating a START condition on the bus. The Master then broadcasts an 8−bit serial Slave address. The first 4 bits of the Slave address are set to 1010, for normal Read/Write operations (Figure 3). The next 3 bits, A2, A1 and A0, select one of 8 possible Slave devices and must match the state of the external address pins. The last bit, R/W, specifies whether a Read (1) or Write (0) operation is to be performed. Functional Description The CAT24C128 supports the Inter−Integrated Circuit (I2C) Bus data transmission protocol, which defines a device that sends data to the bus as a transmitter and a device receiving data as a receiver. Data flow is controlled by a Master device, which generates the serial clock and all START and STOP conditions. The CAT24C128 acts as a Slave device. Master and Slave alternate as either transmitter or receiver. Up to 8 devices may be connected to the bus as determined by the device address inputs A0, A1, and A2. Acknowledge After processing the Slave address, the Slave responds with an acknowledge (ACK) by pulling down the SDA line during the 9th clock cycle (Figure 4). The Slave will also acknowledge all address bytes and every data byte presented in Write mode. In Read mode the Slave shifts out a data byte, and then releases the SDA line during the 9th clock cycle. As long as the Master acknowledges the data, the Slave will continue transmitting. The Master terminates the session by not acknowledging the last data byte (NoACK) and by issuing a STOP condition. Bus timing is illustrated in Figure 5. I2C Bus Protocol The I2C bus consists of two ‘wires’, SCL and SDA. The two wires are connected to the VCC supply via pull−up www.onsemi.com 5 CAT24C128 SCL SDA START CONDITION STOP CONDITION Figure 2. START/STOP Conditions DEVICE ADDRESS 1 0 1 A2 0 A1 A0 R/W Figure 3. Slave Address Bits BUS RELEASE DELAY (TRANSMITTER) SCL FROM MASTER 1 BUS RELEASE DELAY (RECEIVER) 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START ACK SETUP (≥ tSU:DAT) ACK DELAY (≤ tAA) Figure 4. Acknowledge Timing tF tHIGH tLOW tR tLOW SCL tSU:STA tHD:DAT tHD:STA tSU:DAT tSU:STO SDA IN tAA tDH SDA OUT Figure 5. Bus Timing www.onsemi.com 6 tBUF CAT24C128 Write Operations latched and the address count automatically increments to and then wraps−around at the page boundary. Previously loaded data can thus be overwritten by new data. What is eventually written to memory reflects the latest Page Write Buffer contents. Only data loaded within the most recent Page Write sequence will be written to memory. Byte Write Upon receiving a Slave address with the R/W bit set to ‘0’, the CAT24C128 will interpret the next two bytes as address bytes. These bytes are used to initialize the internal address counter; the 2 most significant bits are ‘don’t care’, the next 8 point to one of 256 available pages and the last 6 point to a location within a 64 byte page. A byte following the address bytes will be interpreted as data. The data will be loaded into the Page Write Buffer and will eventually be written to memory at the address specified by the 14 active address bits provided earlier. The CAT24C128 will acknowledge the Slave address, address bytes and data byte. The Master then starts the internal Write cycle by issuing a STOP condition (Figure 6). During the internal Write cycle (tWR), the SDA output will be tri−stated and additional Read or Write requests will be ignored (Figure 7). Acknowledge Polling The ready/busy status of the CAT24C128 can be ascertained by sending Read or Write requests immediately following the STOP condition that initiated the internal Write cycle. As long as internal Write is in progress, the CAT24C128 will not acknowledge the Slave address. Hardware Write Protection With the WP pin held HIGH, the entire memory is protected against Write operations. If the WP pin is left floating or is grounded, it has no impact on the operation of the CAT24C128. The state of the WP pin is strobed on the last falling edge of SCL immediately preceding the first data byte (Figure 9). If the WP pin is HIGH during the strobe interval, the CAT24C128 will not acknowledge the data byte and the Write request will be rejected. Page Write By continuing to load data into the Page Write Buffer after the 1st data byte and before issuing the STOP condition, up to 64 bytes can be written simultaneously during one internal Write cycle (Figure 8). If more data bytes are loaded than locations available to the end of page, then loading will continue from the beginning of page, i.e. the page address is BUS ACTIVITY: MASTER S T A R T Delivery State The CAT24C128 is shipped erased, i.e., all bytes are FFh. ADDRESS BYTE a7−a0 ADDRESS BYTE a13−a8 SLAVE ADDRESS S S T O P DATA BYTE P * * A C K SLAVE A C K A C K A C K * = Don’t Care Bit Figure 6. Byte Write Sequence SCL SDA 8th Bit ACK Byte n tWR STOP CONDITION Figure 7. Write Cycle Timing www.onsemi.com 7 START CONDITION ADDRESS CAT24C128 BUS ACTIVITY: S T A MASTER R T ADDRESS BYTE a13−a8 SLAVE ADDRESS S DATA BYTE n ADDRESS BYTE a7−a0 DATA BYTE n+1 DATA BYTE n+P S T O P P * * A C K SLAVE * = Don’t Care Bit P v 63 A C K A C K A C K A C K A C K A C K Figure 8. Page Write Sequence ADDRESS BYTE DATA BYTE 1 8 9 a7 a0 1 8 d7 d0 SCL SDA tSU:WP WP tHD:WP Figure 9. WP Timing Read Operations with data, the Master instead follows up with an Immediate Read sequence, then the CAT24C128 will use the 14 active address bits to initialize the internal address counter and will shift out data residing at the corresponding location. If the Master does not acknowledge the data (NoACK) and then follows up with a STOP condition (Figure 11), the CAT24C128 returns to Standby mode. Immediate Read Upon receiving a Slave address with the R/W bit set to ‘1’, the CAT24C128 will interpret this as a request for data residing at the current byte address in memory. The CAT24C128 will acknowledge the Slave address, will immediately shift out the data residing at the current address, and will then wait for the Master to respond. If the Master does not acknowledge the data (NoACK) and then follows up with a STOP condition (Figure 10), the CAT24C128 returns to Standby mode. Sequential Read If during a Read session the Master acknowledges the 1st data byte, then the CAT24C128 will continue transmitting data residing at subsequent locations until the Master responds with a NoACK, followed by a STOP (Figure 12). In contrast to Page Write, during Sequential Read the address count will automatically increment to and then wrap−around at end of memory (rather than end of page). Selective Read To read data residing at a specific location, the internal address counter must first be initialized as described under Byte Write. If rather than following up the two address bytes www.onsemi.com 8 CAT24C128 BUS ACTIVITY: MASTER S T A R T N O A C K SLAVE ADDRESS P S A C K SLAVE SCL DATA BYTE 8 SDA S T O P 9 8th Bit DATA OUT NO ACK STOP Figure 10. Immediate Read Sequence and Timing BUS ACTIVITY: MASTER S T A R T ADDRESS BYTE a13−a8 SLAVE ADDRESS S S T A R T ADDRESS BYTE a7−a0 S * * A C K SLAVE N O A C K SLAVE ADDRESS A C K S T O P P A C K A C K DATA BYTE * = Don’t Care Bit Figure 11. Selective Read Sequence N O A C K BUS ACTIVITY: MASTER SLAVE ADDRESS S T O P P SLAVE A C K DATA BYTE n A C K DATA BYTE n+1 A C K DATA BYTE n+2 Figure 12. Sequential Read Sequence www.onsemi.com 9 A C K DATA BYTE n+x CAT24C128 ORDERING INFORMATION (Notes 11 thru 14) Device Order Number Specific Device Marking* CAT24C128WI−GT3 Package Type Temperature Range Lead Finish Shipping† 24128C SOIC−8, JEDEC I = Industrial (−40°C to +85°C) NiPdAu Tape & Reel, 3,000 Units / Reel CAT24C128YI−GT3 C28C TSSOP−8 I = Industrial (−40°C to +85°C) NiPdAu Tape & Reel, 3,000 Units / Reel CAT24C128HU4IGT3 C7U UDFN−8 I = Industrial (−40°C to +85°C) NiPdAu Tape & Reel, 3,000 Units / Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 11. All packages are RoHS−compliant (Lead−free, Halogen−free). 12. The standard lead finish is NiPdAu. 13. For additional package and temperature options, please contact your nearest ON Semiconductor Sales office. 14. For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device Nomenclature document, TND310/D, available at www.onsemi.com ON Semiconductor is licensed by the Philips Corporation to carry the I2C bus protocol. www.onsemi.com 10 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS UDFN8, 2x3 EXTENDED PAD CASE 517AZ ISSUE A 1 SCALE 2:1 PIN ONE REFERENCE 0.10 C B A D L1 ÇÇ ÇÇ ÇÇ DETAIL A ALTERNATE CONSTRUCTIONS E EXPOSED Cu DETAIL B A 0.10 C 0.08 C 1 D2 ÉÉ ÉÉ ÇÇ C MOLD CMPD ÉÉÉ ÉÉÉ ÇÇÇ A3 A1 ALTERNATE CONSTRUCTIONS 1 L 4 5 8X e XXXXX A WL Y W G BOTTOM VIEW b 0.10 M C A B 0.05 M C MILLIMETERS MIN MAX 0.45 0.55 0.00 0.05 0.13 REF 0.20 0.30 2.00 BSC 1.35 1.45 3.00 BSC 1.25 1.35 0.50 BSC 0.25 0.35 −−− 0.15 GENERIC MARKING DIAGRAM* SEATING PLANE E2 8 DIM A A1 A3 b D D2 E E2 e L L1 DETAIL B A3 A1 SIDE VIEW DETAIL A NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.25MM FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L L 0.10 C TOP VIEW NOTE 4 DATE 23 MAR 2015 XXXXX AWLYWG = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. NOTE 3 RECOMMENDED SOLDERING FOOTPRINT* 1.56 8X 0.68 1.45 3.40 1 8X 0.30 0.50 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON42552E Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. UDFN8, 2X3 EXTENDED PAD PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC 8, 150 mils CASE 751BD−01 ISSUE O E1 DATE 19 DEC 2008 E SYMBOL MIN A 1.35 1.75 A1 0.10 0.25 b 0.33 0.51 c 0.19 0.25 D 4.80 5.00 E 5.80 6.20 E1 3.80 4.00 MAX 1.27 BSC e PIN # 1 IDENTIFICATION NOM h 0.25 0.50 L 0.40 1.27 θ 0º 8º TOP VIEW D h A1 A θ c e b SIDE VIEW L END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. DOCUMENT NUMBER: DESCRIPTION: 98AON34272E SOIC 8, 150 MILS Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSSOP8, 4.4x3.0, 0.65P CASE 948AL ISSUE A DATE 20 MAY 2022 q q GENERIC MARKING DIAGRAM* XXX YWW AG XXX Y WW A G = Specific Device Code = Year = Work Week = Assembly Location = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98AON34428E TSSOP8, 4.4X3.0, 0.65P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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