EFC2K103NUZTDG

MOSFET - Power for 1-Cell Lithium-ion Battery Protection EFC2K103NUZ 12 V, 1.8 mW, 40 A, Dual N-Channel www.onsemi.com This power MOSFET features a low on−state resistance. This device is suitable for applications such as power switches of portable machines. Best suited for 1−cell lithium−ion battery applications. Features • • • • VSSS RSS(ON) MAX IS MAX 12 V 1.8 mW @ 4.5 V 40 A 1.9 mW @ 3.8 V 2.5 V drive Common−Drain type ESD Diode−Protected Gate Pb−Free, Halogen Free and RoHS Compliance 2.6 mW @ 3.1 V 4.2 mW @ 2.5 V ELECTRICAL CONNECTION N−Channel Typical Applications • 1−Cell Lithium−ion Battery Charging and Discharging Switch 6, 7, 9, 10 SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS at TA = 25°C Parameter 1 : Source1 2 : Source1 3 : Gate1 4 : Source1 5 : Source1 6 : Source2 7 : Source2 8 : Gate2 9 : Source2 10 : Source2 Rg Symbol Value Unit Source to Source Voltage VSSS 12 V Gate to Source Voltage VGSS ±8 V Source Current (DC) IS 40 A Source Current (Pulse) PW ≤ 10 mS, Duty Cycle ≤ 1% ISP 140 A Total Dissipation (Note 1) PT 3.3 W Junction Temperature TJ 150 °C Storage Temperature Tstg −55 to +150 °C 8 Rg 3 Rg = 300 W Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. PIN ASSIGNMENT 3 1 Parameter Symbol Value Unit Junction to Ambient (Note 1) RqJA 37 °C/W 4 2 5 9 6 7 8 10 THERMAL RESISTANCE MAXIMUM RATINGS 1, 2, 4, 5 MARKING DIAGRAM PB AYWZZ 1. Surface mounted on ceramic substrate (5000 mm2 × 0.8 mm) WLCSP10 3.54x1.77x0.140 CASE 567XB PB A Y W ZZ = Specific Device Code = Assembly Location = Year = Work Week = Assembly Lot ORDERING INFORMATION See detailed ordering, marking and shipping information in the package dimensions section on page 2 of this data sheet. © Semiconductor Components Industries, LLC, 2017 September, 2019 − Rev. 1 1 Publication Order Number: EFC2K103NUZ/D EFC2K103NUZ ELECTRICAL CHARACTERISTICS at TA = 25°C Value Conditions Min Typ Max Unit Parameter Symbol Source to Source Breakdown Voltage V(BR)SSS IS = 1 mA, VGS = 0 V Test Circuit 1 12 − − V Zero Gate Voltage Source Current ISSS VSS = 10 V, VGS = 0 V Test Circuit 1 − − 1 mA Gate to Source Leakage Current IGSS VGS = ±8 V, VSS = 0 V Test Circuit 2 − − ±1 mA 0.4 − 1.3 V Gate Threshold Voltage VGS(th) VSS = 6 V, IS = 1 mA Test Circuit 3 Static Source to Source On−State Resistance RSS(on) IS = 5 A, VGS = 4.5 V Test Circuit 4 0.8 1.25 1.8 mW IS = 5 A, VGS = 3.8 V Test Circuit 4 0.85 1.35 1.9 mW IS = 5 A, VGS = 3.1 V Test Circuit 4 1.0 1.7 2.6 mW IS = 5 A, VGS = 2.5 V Test Circuit 4 1.2 2.1 4.2 mW − 25 − ms − 100 − ms td(off) − 165 − ms tf − 148 − ms VSS = 6 V, VGS = 3.8 V, IS = 5 A Test Circuit 6 − 62 − nC IS = 3 A, VGS = 0 V − 0.75 1.2 V Turn−ON Delay Time Rise Time td(on) tr Turn−OFF Delay Time Fall Time Total Gate Charge Forward Source to Source Voltage Qg VF(S−S) VSS = 6 V, VGS = 3.8 V, IS = 5 A, RG = 10 kW Test Circuit 5 Test Circuit 7 Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. ORDERING INFORMATION Device Marking Package Shipping (Qty / Packing)† EFC2K103NUZTDG PB WLCSP10, 3.54 × 1.77 × 0.140 (Pb−Free / Halogen Free) 5,000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 2 EFC2K103NUZ TYPICAL CHARACTERISTICS 10 4.5 V 3.8 V 5 2.5 V 4 3 2 TA = 25°C Single Pulse 1 8 7 TA = 75°C 6 TA = 25°C 5 TA = −25°C 4 3 2 1 0 0 0.0000 0.0050 0.0100 0.0150 0.0200 0 0.3 0.6 0.9 1.2 1.5 Source-to-Source Voltage, VSS (V) Gate-to-Source Voltage, VGS (V) Figure 1. IS − VSS Figure 2. IS − VGS 5 1.8 5 Static Source-to-Source On-State Resistance, RSS(on) (mW) Static Source-to-Source On-State Resistance, RSS(on) (mW) VSS = 6 V Single Pulse 9 3.1 V Source Current, IS (A) Source Current, IS (A) 6 IS = 5 A Single Pulse 4.5 4 3.5 3 TA = 75°C 2.5 TA = 25°C 2 TA = −25°C 1.5 1 0.5 1 2 3 4 5 6 7 IS = 5 A Single Pulse 4.5 4 3.5 3 2.5 VGS = 2.5 V 2 1.5 1 0.5 −60 −40 −20 8 0 20 VGS = 3.1 V VGS = 3.8 V VGS = 4.5 V 40 60 80 100 120 140 160 Gate-to-Source Voltage, VGS (V) Ambient Temperature, TA (5C) Figure 3. RSS(on) − VGS Figure 4. RSS(on) − TA 10 Switching Time, S/W (ms) Source Current, IS (A) VGS = 0 V Single Pulse 1 TA = 75°C TA = 25°C TA = −25°C 0.1 0.01 td(off) 100 tf tr 10 td(on) TA = 25°C VSS = 6 V VGS = 3.8 V IS = 5 A Single Pulse 1 0 0.2 0.4 0.6 0.8 1.0 1.2 Forward Source-to-Source Voltage, VF(S-S) (V) 1 10 Gate Resistance, RG (kW) Figure 5. IS − VF(S-S) Figure 6. SW Time − RG www.onsemi.com 3 EFC2K103NUZ TYPICAL CHARACTERISTICS (Continued) 3.5 TA = 25°C VSS = 6 V IS = 5 A 3.5 3 Total Dissipation, PT (W) Gate-to-Source Voltage, VGS (V) 4 2.5 2 1.5 1 0.5 Surface mounted on ceramic substrate (5000 mm2 × 0.8 mm) 3 2.5 2 1.5 1 0.5 0 0 0 10 20 30 40 50 60 0 25 Total Gate Charge, QG (nC) 50 75 100 125 150 Ambient Temperature, TA (5C) Figure 7. VGS − QG Figure 8. PT − TA 1000 Source Current, IS (A) ISP = 140 A (PW ≤ 10 ms) 100 10 ms IS = 40 A 100 ms 10 1 ms Operation in this area is limited by RSS(on) 1 10 ms 100 ms DC Operation TA = 25°C Single pulse When mounted on ceramic substrate (5000 mm2 x 0.8 mm) 0.1 0.01 0.01 0.1 0 10 Source-to-Source Voltage, VSS (V) Figure 9. Safe Operating Area Thermal Resistance, RqJA (5C/W) 100 Duty Cycle = 0.5 10 0.2 0.1 0.05 1 0.02 0.01 Single Pulse 0.1 0.00001 0.0001 0.001 0.01 0.1 Pulse Time, PT (s) Figure 10. Thermal Response www.onsemi.com 4 1 10 175 EFC2K103NUZ TEST CIRCUITS ARE EXAMPLES OF MEASURING FET1 SIDE V(BR)SSS / ISSS IGSS S2 S2 G2 G2 A G1 G1 VSS A S1 S1 VGS Figure 12. Test Circuit 2 Figure 11. Test Circuit 1 VGS(th) RSS(on) S2 S2 G2 IS G2 A When FET1 is measured, Gate and Source of FET2 are short−circuited. V G1 G1 VSS S1 VGS S1 VGS Figure 13. Test Circuit 3 Figure 14. Test Circuit 4 td(on), tr, td(off), tf Qg S2 S2 RL G2 A G2 When FET1 is measured, Gate and Source of FET2 are short−circuited. Rg When FET1 is measured, Gate and Source of FET2 are short−circuited. V IG = 1 mA G1 RL G1 S1 S1 VSS VSS PG Figure 15. Test Circuit 5 Figure 16. Test Circuit 6 www.onsemi.com 5 When FET1 is measured, Gate and Source of FET2 are short−circuited. EFC2K103NUZ VF(S−S) S2 IS G2 VGS = 0 V V G1 S1 When FET1 is measured, + 4.5 V is added to VGS of FET2. Figure 17. Test Circuit 7 NOTE: When FET2 is measured, the position of FET1 and FET2 is switched. NOTE: Since the EFC2K103NUZ is a MOSFET product, please avoid using this device in the vicinity of highly charged objects. Please contact sales for use except the designated application. www.onsemi.com 6 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS WLCSP10, 3.54x1.77x0.14 CASE 567XB ISSUE O 5 4 6 7 1 9 10 2 GENERIC MARKING DIAGRAM* XXXXXG AYWZZG DESCRIPTION: 9 10 8 4 XXXX A Y W ZZ G = Specific Device Code = Assembly Location = Year = Work Week = Assembly Lot Code = Pb−Free Package (Note: Microdot may be in either location) DOCUMENT NUMBER: 2 3 8 3 1 DATE 09 OCT 2018 98AON98952G WLCSP10, 3.54x1.77x0.14 5 6 7 *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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