FAN53528
3.0 A, 2.4 MHz, Digitally
Programmable Buck
Regulator
Descriptions
The FAN53528 is a step−down switching voltage regulator that
delivers a digitally programmable output from an input voltage supply
of 2.5 V to 5.5 V. The output voltage is programmed through an I2C
interface capable of operating up to 3.4 MHz.
Using a proprietary architecture with synchronous rectification, the
FAN53528 is capable of delivering 3.0 A continuous at over 80%
efficiency, maintaining that efficiency at load currents as low as
10 mA. The regulator operates at a nominal fixed frequency of
2.4 MHz, which reduces the value of the external components.
Additional output capacitance can be added to improve regulation
during load transients without affecting stability.
At moderate and light−loads, Pulse Frequency Modulation (PFM) is
used to operate in Power−Save Mode with a typical quiescent current
of 50 mA at room temperature. Even with such a low quiescent
current, the part exhibits excellent transient response during large load
swings. At higher loads, the system automatically switches to
fixed−frequency control, operating at 2.4 MHz. In Shutdown Mode,
the supply current drops below 1 mA, reducing power consumption.
PFM Mode can be disabled if fixed frequency is desired. The
FAN53528 is available in a 15−bump, 1.310 mm × 2.015 mm, 0.4 mm
ball pitch WLCSP.
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WLCSP−15
CASE 567QS
MARKING DIAGRAM
Pin−1
Mark
1, 2
KK
.
X
Y
Z
1
2
K
K
X
Y
Z
= Two Alphanumeric Characters
for Device Mark
= Two Alphanumeric Characters
for Lot Rune Code Mark
= Pin 1 Indicator
= Alphabetical Year Code
= 2−weeks Date Code
= Assembly Plant Code
Features
•
•
•
•
•
•
•
•
•
•
•
•
Fixed−Frequency Operation: 2.4 MHz
Best−in−Class Load Transient
Continuous Output Current Capability: 3.0 A
2.5 V to 5.5 V Input Voltage Range
Digitally Programmable Output Voltage:
♦ 0.35 V to 1.14375 V in 6.25 mV Steps
Programmable Slew Rate for Voltage Transitions
I2C−Compatible Interface Up to 3.4 Mbps
PFM Mode for High Efficiency in Light-Load
Quiescent Current in PFM Mode: 50 mA (Typical)
Input Under−Voltage Lockout (UVLO)
Thermal Shutdown and Overload Protection
15−Bump Wafer−Level Chip Scale Package (WLCSP)
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
Applications
• Application, Graphic, and DSP Processors
ARMt, Tegrat, OMAPt, NovaThort,
ARMADAt, Kraitt, etc.
Hard Disk Drives, LPDDR3, LPDDR4
Tablets, Netbooks, Ultra−Mobile PCs
Smart Phones
Gaming Devices
♦
•
•
•
•
© Semiconductor Components Industries, LLC, 2016
February, 2019 − Rev. 2
1
Publication Order Number:
FAN53528/D
FAN53528
VIN
C BY
C IN
EN
VOUT
SDA
L1
SW
FAN 53528
SCL
VSEL
PGND
COUT1,2
LOAD
AGND
Figure 1. Typical Application
PACKAGE MARKING AND ORDERING INFORMATION
Power−Up
Defaults
Part Number
VSEL0
VSEL1
EN Delay
Temperature
Range
Package
Packing
Method
Device
Marking
FAN53528BUC08X
0.4
0.6
No
−40 to 85_C
WLCSP
Tape & Reel
FX
FAN53528DUC40X
0.6
0.9
No
FY
FAN53528GUC48X
0.65
0.7
No
FZ
FAN53528EUC48X
0.65
0.7
5 ms
FW
*FAN53528DUC1204X
1.1
0.9
No
TBD
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This device is not released yet.
RECOMMENDED EXTERNAL COMPONENTS
Table 1. RECOMMENDED EXTERNAL COMPONENTS FOR 3.0 A MAXIMUM LOAD CURRENT
Component
Description
Vendor
L1
330 nH, 2016 Case Size
L1 Alternative (Note 1)
470 nH 2016 Case Size
COUT1, COUT2
22 mF, 6.3 V, X5R, 0603
Parameter
Typ.
Unit
22
mF
See Table 2
C1608X5R0J226M080AC (TDK)
C
CIN
1 Piece; 4.7 mF, 10 V, X5R, 0603
C1608X5R1A475K (TDK)
C
4.7
CBY (Note 1)
1 Piece; 100 nF, 6.3V, X5R, 0201
GRM033R60J104KE19D (Murata)
C
100
nF
1. L1 Alternative can be used if not following reference design. CBY is recommended to reduce any high frequency component on VIN bus.
CBY is optional and used to filter any high frequency component on VIN bus.
Table 2. RECOMMENDED INDUCTORS
Component Dimensions
Manufacturer
Part #
L (nH)
DCR
(mW Typ.)
Toko
DFE201610E−R33N
330
21
6.1
2.0
1.6
1.0
Toko
DFE201610E−R47N
470
26
5.3
2.0
1.6
1.0
2. ISAT where the dc current drops the inductance by 30%.
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2
ISAT
(Note 2)
L
W
H
FAN53528
PIN CONFIGURATION
VIN
SW
PGND
A1
A2
A3
B1
B2
B3
PGND
AGND
C2
C3
VSEL
EN
SDA
D1
D2
D3
AGND
SCL
VOUT
E1
E2
E3
C1
Top View
A3
A2
A1
B3
B2
B1
C3
C2
C1
D3
D2
D1
E3
E2
E1
Bottom View
Figure 2. Pin Configuration
Table 3. PIN DEFINITIONS
Pin #
Name
Description
D1
VSEL
Voltage Select. When this pin is LOW, VOUT is set by the VSEL0 register. When this pin is HIGH,
VOUT is set by the VSEL1 register. Polarity of pin in conjunction with the MODE bits in the Control
register 02h, will select Forced PWM or Auto PFM/PWM mode of operation. VSEL0 = Auto PFM,
and VSEL1 = FPWM. The VSEL pin has an internal pull−down resistor (250 kW), which is only
activated with a logic low.
D2
EN
Enable. The device is in Shutdown Mode when this pin is LOW. Device keeps register content
when EN pin is LOW. The EN Pin has an internal pull−down resistor (250 kW), which is only activated with a logic low.
E2
SCL
I2C Serial Clock
D3
SDA
I2C Serial Data
E3
VOUT
VOUT. Sense pin for VOUT. Connect to COUT.
A3, B3, C2
PGND
Power Ground. The low−side MOSFET is referenced to this pin. CIN and COUT should be returned
with a minimal path to these pins.
C3, E1
AGND
Analog Ground. All signals are referenced to this pin. Avoid routing high di/dt AC currents through
this pin.
A1, B1, C1
VIN
Power Input Voltage. Connect to the input power source. Connect to CIN with minimal path.
A2, B2
SW
Switching Node. Connect to the inductor.
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3
FAN53528
Table 4. ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
VIN
Parameter
Voltage on SW, VIN Pins
Min
Max
Unit
IC Not Switching
−0.3
7.0
V
IC Switching
−0.3
6.5
−0.3
VIN
(Note 3)
−0.3
VIN
(Note 3)
Voltage on EN Pin
Voltage on All Other Pins
VOUT
IC Not Switching
Voltage on VOUT Pin
VINOV_SLEW
ESD
−0.3
Maximum Slew Rate of VIN > 6.5V, PWM Switching
Human Body Model, ANSI/ESDA/JEDEC JS−001−2012
2000
Charged Device Model per JESD22−C101
1000
6.5
V
100
V/ms
V
TJ
Junction Temperature
−40
+150
°C
TSTG
Storage Temperature
−65
+150
°C
+260
°C
TL
Lead Soldering Temperature, 10 Seconds
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
3. Lesser of 7V or VIN + 0.3 V.
Table 5. RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VIN
Supply Voltage Range
IOUT
Output Current
Min.
Typ.
Max.
Unit
2.5
5.5
V
0
3.0
A
TA
Operating Ambient Temperature
−40
+85
°C
TJ
Operating Junction Temperature
−40
+125
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
Table 6. THERMAL PROPERTIES
Symbol
Parameter
θJA
Junction−to−Ambient Thermal Resistance (Note 4)
Min.
Typ.
42
Max.
Unit
°C/W
4. Junction−to−ambient thermal resistance is a function of application and board layout. This data is simulated with four−layer 2s2p boards with
vias in accordance to JESD51− JEDEC standard. Special attention must be paid not to exceed the junction temperature
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4
FAN53528
Table 7. ELECTRICAL CHARACTERISTICS
Minimum and maximum values are at VIN = 3.6 V, TA = −40°C to +85°C, unless otherwise noted.
Typical values are at TA = 25°C, VIN = 3.6 V, VOUT = 0.4 V and EN = 1.8 V.
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
POWER SUPPLIES
Quiescent Current
ILOAD = 0
50
H/W Shutdown Supply Current
EN = GND
0.1
3.0
mA
S/W Shutdown Supply Current
EN = 1.8 V, BUCK_ENx = 0,
2.5 V ≤ VIN ≤ 5.5 V
2
12
mA
VUVLO
Under−Voltage Lockout Threshold
VIN Rising
2.32
2.45
V
VUVHYST
Under−Voltage Lockout Hysteresis
IQ
I SD
mA
350
mV
EN, VSEL, SDA, SCL
VIH
HIGH−Level Input Voltage
2.5 V ≤ VIN ≤ 5.5 V
VIL
LOW−Level Input Voltage
2.5 V ≤ VIN ≤ 5.5 V
IIN
Input Bias Current
Input Tied to GND or VIN
1.1
V
0.4
V
1.00
mA
−3
+5
%
−1.5
+1.5
−4
+6
0.01
VOUT REGULATION
VREG
VOUT DC Accuracy
2.8 V ≤ VIN ≤ 4.8 V, VOUT = 0.4 V,
IOUT(DC) = 0 A, Auto Mode
2.8 V ≤ VIN ≤ 4.8 V, VOUT = 0.4 V,
IOUT(DC) = 0 A, Forced PWM Mode
2.8 V ≤ VIN ≤ 4.8 V, VOUT from
Minimum to Maximum,
IOUT(DC) = 0 to 3.0 A, Auto Mode
POWER SWITCH/PROTECTION
ILIMPK
P−MOS Peak Current Limit
TLIMIT
Thermal Shutdown
THYST
Thermal Shutdown Hysteresis
VSDWN
Input OVP Shutdown
4.00
Rising Threshold
Falling Threshold
4.75
5.50
A
150
°C
17
°C
6.15
V
5.50
5.73
2.05
2.40
FREQUENCY CONTROL
fSW
Oscillator Frequency
2.75
MHz
0.5
LSB
DAC
Resolution
7
Differential Nonlinearity (Note 5)
Bits
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Monotonicity assured by design.
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5
FAN53528
Table 8. SYSTEM CHARACTERISTICS
The following system characteristics are guaranteed by design and are not performed in production testing. Recommended operating
conditions, unless otherwise noted, VIN =2.5 V to 5.5 V, TA = −40°C to +85°C, VOUT =0.4 V.
Typical values are given at TA = 25°C, VIN =3.6 V. System characteristics are based on circuit per Figure 1.
L = 0.33 mH, DFE201610E−R33M (TOKO), CIN = 1 × 4.7 mF, 10 V, 0603 (1608 metric), C1608X5R1A475K (TDK) and COUT = 2 × 22 mF
(6.3 V, 0603, TDK C1608X5R0J226M080AC) + 4 × 100 mF (6.3 V, 0201, Murata GRM033R60J104KE19D) + 1 × 4.7 mF (6.3 V, 0402, TDK
C1005X5R0J475M050BC).
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
LOADREG
Load Regulation
IOUT = 0 A to 3 A, Forced PWM Mode
0.05
%/A
LINEREG
Line Regulation
2.5 V ≤ VIN ≤ 5.5 V, IOUT =1.5 A
0.09
%/V
VOUT_RIPPLE
Ripple Voltage
IOUT = 20 mA, PFM Mode
16
mV
IOUT = 700 mA, PFM Mode
5
Load Transient
mV
IOUT = 10 mA ⇔ 700 mA,
tR = tF = 200 ns, VOUT = 0.4 V, Auto Mode
±20
IOUT = 0 mA ⇔ 800 mA,
tR = tF = 0.9 ms, VIN = 3.2 V, VOUT = 1.125 V,
Auto Mode
±13
IOUT = 0 mA ⇔ 800 mA,
tR = tF = 0.9 ms, VIN = 3.8 V, VOUT = 1.125 V,
Auto Mode
±15
Line Transient
VIN = 3.0 V ⇔ 3.6 V,
tR = tF = 10 ms, IOUT = 100 mA, Forced PWM Mode
±11
mV
tss
Soft−Start
EN High to 95% of Target_VOUT (0.4 V),
IOUT = 200 mA; FAN53528BUC08X
85
ms
tdelay
EN Delay
EN High to VOUT Start−to−Rise,
VOUT = 0.65 V, IOUT = 0 A; FAN53528EUC48X
5
ms
DVOUT_LOAD
DVOUT_LINE
Table 9. I2C TIMING SPECIFICATIONS
Guaranteed by design.
Symbol
fSCL
tBUF
tHD;STA
tLOW
Parameter
SCL Clock Frequency
Bus−Free Time between STOP and
START Conditions
START or REPEATED START
Hold Time
SCL LOW Period
Condition
Min.
Typ.
Max.
Unit
Standard Mode
100
kHz
Fast Mode
400
kHz
Fast Mode Plus
1000
High−Speed Mode, CB ≤ 100 pF
3400
High−Speed Mode, CB ≤ 400 pF
1700
Standard Mode
4.7
Fast Mode
1.3
Fast Mode Plus
0.5
Standard Mode
4
ms
Fast Mode
600
ns
Fast Mode Plus
260
High−Speed Mode
160
Standard Mode
4.7
Fast Mode
1.3
Fast Mode Plus
0.5
High−Speed Mode, CB ≤ 100 pF
160
High−Speed Mode, CB ≤ 400 pF
320
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6
ms
ms
ns
FAN53528
Table 9. I2C TIMING SPECIFICATIONS (continued)
Guaranteed by design.
Symbol
tHIGH
tSU;STA
tSU;DAT
tHD;DAT
tRCL
tFCL
tRCL1
tRDA
Parameter
SCL HIGH Period
Repeated START Setup Time
Data Setup Time
Data Hold Time
SCL Rise Time
SCL Fall Time
Condition
Min.
Standard Mode
Typ.
Max.
Unit
4
ms
Fast Mode
600
ns
Fast Mode Plus
260
High−Speed Mode, CB ≤ 100 pF
60
High−Speed Mode, CB ≤ 400 pF
120
Standard Mode
4.7
ms
Fast Mode
600
ns
Fast Mode Plus
260
High−Speed Mode
160
Standard Mode
250
Fast Mode
100
Fast Mode Plus
50
High−Speed Mode
10
ns
Standard Mode
0
3.45
ms
Fast Mode
0
900
ns
Fast Mode Plus
0
450
High−Speed Mode, CB ≤ 100 pF
0
70
High−Speed Mode, CB ≤ 400 pF
0
150
Standard Mode
20+0.1CB
1000
Fast Mode
20+0.1CB
300
Fast Mode Plus
20+0.1CB
120
High−Speed Mode, CB ≤ 100 pF
10
80
High−Speed Mode, CB ≤ 400 pF
20
160
Standard Mode
20+0.1CB
300
Fast Mode
20+0.1CB
300
Fast Mode Plus
20+0.1CB
120
High−Speed Mode, CB ≤ 100 pF
10
40
High−Speed Mode, CB ≤ 400 pF
20
80
Rise Time of SCL After a
REPEATED START Condition and
After ACK Bit
High−Speed Mode, CB ≤ 100 pF
10
80
High−Speed Mode, CB ≤ 400 pF
20
160
SDA Rise Time
Standard Mode
20+0.1CB
1000
Fast Mode
20+0.1CB
300
Fast Mode Plus
20+0.1CB
120
High−Speed Mode, CB ≤ 100 pF
10
80
High−Speed Mode, CB ≤ 400 pF
20
160
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7
ns
ns
ns
ns
FAN53528
Table 9. I2C TIMING SPECIFICATIONS (continued)
Guaranteed by design.
Parameter
Symbol
tFDA
Condition
SDA Fall Time
tSU;STO
Stop Condition Setup Time
CB
20+0.1CB
300
Fast Mode Plus
20+0.1CB
120
High−Speed Mode, CB ≤ 100 pF
10
80
High−Speed Mode, CB ≤ 400 pF
20
160
Standard Mode
4
ms
Fast Mode
600
ns
Fast Mode Plus
120
High−Speed Mode
160
400
ÑÑ
ÑÑ
ÑÑ
ÑÑ
ÑÑ
ÑÑ
ÓÓÓ
ÓÓÓ
TSU;DAT
tHIGH
tLOW
tHD;STA
tHD;DAT
tHD;STO
REPEATED
START
Figure 3.
tFDA
STOP
Interface Timing for Fast Plus, Fast, and Slow Modes
tRDA
REPEATED
START
tSU;DAT
SDAH
tSU;STA
tRCL1
SCLH
tFCL
tRCL
tSU;STO
tHIGH
tLOW
tHD;STA
tHD;DAT
REPEATED
START
note A
= MCS Current Source Pull−up
= RP Resistor Pull−up
Note A: First rising edge of SCLH after Repeated Start and after each ACK bit.
Figure 4. I2C Interface Timing for High−Speed Mode
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8
ÌÌ
ÎÎ
ÌÌÎÎ
ÌÌ
ÎÎ
ÌÌÎÎ
ÌÌ
ÎÎ
ÌÌÎÎ
ÌÌÎÎ
ÒÒ
ÏÏ
tBUF
tHD;STA
START
I2C
ns
Fast Mode
tSU;STA
tR
Unit
300
Capacitive Load for SDA and SCL
ÔÔ
ÔÔ
ÔÔ
ÔÔ
ÔÔ
ÔÔ
ÔÔ
ÖÖ
Max.
20+0.1CB
tF
SCL
Typ.
Standard Mode
Timing Diagrams
SDA
Min.
STOP
START
pF
FAN53528
TYPICAL CHARACTERISTICS
Unless otherwise specified, VIN = 3.6 V, VOUT = 0.4 V, Auto Mode, TA = 25°C; circuit and components according to Figure 1 and Table 1.
Figure 5. Efficiency vs. Load Current and Input
Voltage, VOUT = 0,4 V, Auto Mode
Figure 6. Efficiency vs. Load Current and
Temperature, VIN = 3.6 V, VOUT = 0.4 V, Auto Mode
Figure 7. Output Regulation vs. Load Current and
Input Voltage, VOUT = 0.4 V, Auto Mode
Figure 8. Frequency vs. Load Current and Input
Voltage, VOUT = 0.65 V, Auto Mode
Figure 9. Quiescent Current vs. Input Voltage
and Temperature VOUT = 0.4 V, Auto Mode
Figure 10. Shutdown Current vs. Input Voltage
and Temperature
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FAN53528
TYPICAL CHARACTERISTICS (continued)
Unless otherwise specified, VIN = 3.6 V, VOUT = 0.4 V, Auto Mode, TA = 25°C; circuit and components according to Figure 1 and Table 1.
Figure 11. Output Ripple, VIN = 3.6 V, VOUT = 0.65 V,
20 mA Load
Figure 12. Output Ripple, VIN = 3.6 V, VOUT = 0.65 V,
770 mA Load
Figure 13. Line Transient, VIN = 3.0 V @ 3.6 V, VOUT = 0.4 V,
10 ms Edge, 100 mA Load, Forced PWM Mode
Figure 14. Load Transient, VIN = 3.6 V, VOUT = 0.4 V,
10 mA @ 700 mA, 200 ns Edge, Auto Mode
Figure 15. Load Transient, VIN = 3.2 V, VOUT = 1.125 V,
0 mA @ 800 mA, 900 ns Edge, Auto Mode
Figure 16. Load Transient, VIN = 3.8 V, VOUT = 1.125 V,
0 mA @ 800 mA, 900 ns Edge, Auto Mode
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FAN53528
TYPICAL CHARACTERISTICS (continued)
Unless otherwise specified, VIN = 3.6 V, VOUT = 0.4 V, Auto Mode, TA = 25°C; circuit and components according to Figure 1 and Table 1.
Figure 17. Startup, VIN = 3.6 V, VOUT = 0.65 V, 200 mA Load,
with 5 ms EN Delay, Auto Mode
OPERATING DESCRIPTION
The FAN53528 is a step−down switching voltage
regulator that delivers a programmable output voltage from
an input voltage supply of 2.5 V to 5.5 V. Using a proprietary
architecture with synchronous rectification, the FAN53528
is capable of delivering 3.0 A at over 80% efficiency. The
regulator operates at a nominal frequency of 2.4 MHz at full
load, which reduces the value of the external components to
330 nH or 470 nH for the output inductor and 44 mF for the
output capacitor. High efficiency is maintained at light load
with single−pulse PFM.
An I2C−compatible interface allows transfers up to
3.4 Mbps. This communication interface can be used to:
• Dynamically re−program the output voltage in 6.25 mV
increments;
• Reprogram the mode to enable or disable PFM;
• Control voltage transition slew rate; or
• Enable/disable the regulator.
For very light−loads, the FAN53528 operates in
Discontinuous Current Mode (DCM) single−pulse PFM,
which produces low output ripple compared with other PFM
architectures. Transition between PWM and PFM is
relatively seamless, providing a smooth transition between
DCM and CCM Modes.
PFM can be disabled by programming the MODE bits in
the CONTROL register in combination with the state of the
VSEL pin. See table in the Control Register 02h.
Enable and Soft−Start
When the EN pin is LOW; the IC is shut down, all internal
circuits are off, and the part draws very little current. In this
state, I2C can be written to or read from as long as input
voltage is above the UVLO. The registers keep the content
when the EN pin is LOW. The registers are reset to default
values during a Power On Reset (POR). When the
OUTPUT_DISCHARGE bit in the Control register is
enabled (logic HIGH) and the EN pin is LOW or the
BUCK_ENx bit is LOW, an 11 W load is connected from
VOUT to GND to discharge the output capacitors.
Raising EN while the BUCK_ENx bit is HIGH activates
the part and begins the soft−start cycle. For option EUC48X,
there is 5 ms delay time from EN HIGH to VOUT start
soft−start. And for options FAN53528BUC08X,
FAN53528GUC48X and FAN53528DUC40X, there is no
EN Delay. During soft−start, the modulator’s internal
reference is ramped slowly to minimize surge currents on the
input and prevent overshoot of the output voltage.
Synchronous rectification is inhibited, allowing the IC to
start into a pre−charged capacitive load.
Control Scheme
The FAN53528 uses a proprietary non−linear,
fixed−frequency PWM modulator to deliver a fast load
transient response, while maintaining a constant switching
frequency over a wide range of operating conditions. The
regulator performance is independent of the output
capacitor ESR, allowing for the use of ceramic output
capacitors. Although this type of operation normally results
in a switching frequency that varies with input voltage and
load current, an internal frequency loop holds the switching
frequency constant over a large range of input voltages and
load currents.
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11
FAN53528
1.8 V
Table 11. TRANSITION SLEW RATE
Decimal
Bin
0
000
64.00
mV/ms
1
001
32.00
mV/ms
2
010
16.00
mV/ms
3
011
8.00
mV/ms
4
100
4.00
mV/ms
Figure 18. EN Delay
5
101
2.00
mV/ms
If large values of output capacitance are used, the
regulator may fail to start. The maximum COUT capacitance
for starting with a heavy constant−current load is
approximately:
6
110
1.00
mV/ms
7
111
0.50
mV/ms
EN
0V
EN_Delay
VOUT
0V
C OUTMAX [ (I LMPK * I LOAD)
320m
Transitions from high to low voltage rely on the output
load to discharge VOUT to the new set point. Once the
high−to−low transition begins, the IC stops switching until
VOUT has reached the new set point.
(eq. 1)
V OUT
where COUTMAX is expressed in μF and ILOAD is the load
current during soft−start, expressed in A.
Under−Voltage Lockout (UVLO)
When EN is HIGH, the under−voltage lockout keeps the
part from operating until the input supply voltage rises
HIGH enough to properly operate. This ensures proper
operation of the regulator during startup or shutdown.
If the regulator is at its current limit for 16 consecutive
current limit cycles, the regulator shuts down and enters
tri−state before reattempting soft−start 1700 ms later. This
limits the duty cycle of full output current during soft−start
to prevent excessive heating.
The IC allows for software enable of the regulator, when
EN is HIGH, through the BUCK_EN bits. BUCK_EN0 and
BUCK_EN1 are both initialized HIGH. These options start
after a POR, regardless of the state of the VSEL pin.
Input Over−Voltage Protection (OVP)
When VIN exceeds VSDWN (~ 6.2 V), the IC stops
switching to protect the circuitry from internal spikes above
6.5 V. An internal filter prevents the circuit from shutting
down due to noise spikes.
Current Limiting
Table 10. HARDWARE AND SOFTWARE ENABLE
Pins
A heavy load or short circuit on the output causes the
current in the inductor to increase until a maximum current
threshold is reached in the high−side switch. Upon reaching
this point, the high−side switch turns off, preventing high
currents from causing damage. 16 consecutive current limit
cycles in current limit, cause the regulator to shut down and
stay off for about 1700 ms before attempting a restart.
BITS
EN
VSEL
BUCK_EN0
BUCK_EN1
Output
Mode
0
X
X
X
OFF
Shutdown
1
0
0
X
OFF
Shutdown
1
0
1
X
ON
Auto
1
1
X
0
OFF
Shutdown
1
1
X
1
ON
FPWM
Thermal Shutdown
When the die temperature increases, due to a high load
condition and/or high ambient temperature, the output
switching is disabled until the die temperature falls
sufficiently. The junction temperature at which the thermal
shutdown activates is nominally 150°C with a 17°C
hysteresis.
VSEL Pin and I2C Programming Output Voltage
The output voltage is set by the NSELx control bits in
VSEL0 and VSEL1 registers. The output is given as:
V OUT + 0.35 V ) NSELx
6.25 mV
Slew Rate
(eq. 2)
For example, if NSEL =1010000 (80 decimal), then
VOUT = 0.35 + 0.5 = 0.85 V.
Output voltage can also be controlled by toggling the
VSEL pin LOW or HIGH. VSEL LOW corresponds to
VSEL0 and VSEL HIGH corresponds to VSEL1. Upon
POR, VSEL0 and VSEL1 are reset to their default voltages.
Monitor Register (Reg05)
The Monitor register indicates of the regulation state of
the IC. If the IC is enabled and is regulating, its value is
(1000 0001).
I2C Interface
The serial interface is compatible with Standard, Fast,
Fast Plus, and HS Mode I2C BusR specifications. The SCL
line is an input and its SDA line is a bi−directional
open−drain output; it can only pull down the bus when
Transition Slew Rate Limiting
When transitioning from a low to high voltage, the IC can
be programmed for one of eight possible slew rates using the
SLEW bits in the Control register, as shown in Table 11.
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12
FAN53528
Slave Releases
active. The SDA line only pulls LOW during data reads and
when signaling ACK. All data is shifted in MSB (bit 7) first.
In hex notation, the slave address assumes a 0 LS Bit. The
hex slave address is A0 for FAN53528BUCxxX and A4 for
FAN53528DUCxxX,
FAN53528EUCxxX,
and
FAN53528GUCxxX.
SCL
Figure 21. STOP Bit
During a read from the FAN53528, the master issues a
REPEATED START after sending the register address and
before resending the slave address. The REPEATED
START is a 1 to 0 transition on SDA while SCL is HIGH, as
shown in Figure 22.
Table 12. I2C SLAVE ADDRESS
Bits
Option
Hex
7
6
5
4
3
2
1
0
BUCxx
A0
1
0
1
0
0
0
0
R/W
DUCxx,
EUCxx,
GUCxx
A4
1
0
1
0
0
1
0
R/W
Slave Releases
High−Speed (HS) Mode
The protocols for High−Speed (HS), Low−Speed (LS),
and Fast−Speed (FS) Modes are identical; except the bus
speed for HS Mode is 3.4 MHz. HS Mode is entered when
the bus master sends the HS master code 00001XXX after
a START condition (Figure 20). The master code is sent in
Fast or Fast−Plus Mode (less than 1 MHz clock); slaves do
not ACK this transmission.
The master generates a REPEATED START condition
(Figure 22) that causes all slaves on the bus to switch to HS
Mode. The master then sends I2C packets, as described
above, using the HS Mode clock rate and timing.
The bus remains in HS Mode until a STOP bit (Figure 21)
is sent by the master. While in HS Mode, packets are
separated by REPEATED START conditions (Figure 22).
Data change allowed
tH
t SU
Figure 19. Data Transfer Timing
Each bus transaction begins and ends with SDA and SCL
HIGH. A transaction begins with a START condition, which
is defined as SDA transitioning from 1 to 0 with SCL HIGH,
as shown in Figure 20.
SDA
tHD;STA
SLADDR
MS Bit
Figure 22. REPEATED START Timing
As shown in Figure 19 data is normally transferred when
SCL is LOW. Data is clocked in on the rising edge of SCL.
Typically, data transitions shortly at or after the falling edge
of SCL to allow sufficient time for the data to set up before
the next SCL rising edge.
SCL
t HD;STA
SCL
Bus Timing
ÜÜÜ
ÎÎÎ
ÎÎÎ
ÜÜÜ
ÎÎÎ
ÜÜÜ
t SU;STA
ACK(0) or
NACK(1)
SDA
Other slave addresses can be assigned. Contact an
ON Semiconductor representative.
SDA
tHD;STO
ACK(0) or
NACK(1)
SDA
I2C Slave Address
Master Drives
Read and Write Transactions
The following figures outline the sequences for data read
and write. Bus control is signified by the shading of the
packet, defined as:
•
•
Slave Address
MS Bit
Master Drives Bus
and
Slave Drives Bus
All addresses and data are MSB first.
SCL
Table 13. I2C BIT DEFINITIONS FOR FIGURE 23 AND
FIGURE 24
Figure 20. START Bit
A transaction ends with a STOP condition, defined as
SDA transitioning from 0 to 1 with SCL high, as shown in
Figure 21.
Symbol
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13
Definition
S
START, see Figure 20
P
STOP, see Figure 21
A
ACK. The slave drives SDA to 0
to acknowledge the preceding packet.
A
NACK. The slave sends a 1 to NACK the preceding packet.
R
REPEATED START, see Figure 22
FAN53528
7 bits
S
Slave Address
0
0
8 bits
0
8 bits
0
A
Reg Addr
A
Data
A
P
Figure 23. Write Transaction
7 bits
S
Slave Address
0
0
8 bits
0
A
Reg Addr
A
7 bits
R
Slave Address
1
0
8 bits
1
A
Data
A
P
Figure 24. Write Transaction Followed by a Read Transaction
REGISTER DESCRIPTION
Table 14. REGISTER MAP
Hex
Address
Name
00
VSEL0
01
VSEL1
02
CONTROL
03
ID1
04
ID2
05
MONITOR
Function
Binary
Hex
Controls VOUT settings when VSEL pin = LOW
1XXXXXXX
XX
Controls VOUT settings when VSEL pin = HIGH
1XXXXXXX
XX
10000010
82
Read−only register identifies vendor and chip type
10000001
81
Read−only register identifies die revision
00001000
08
Indicates device status
00000000
00
Determines whether VOUT output discharge is enabled and also the slew rate
of positive transitions
Table 15. BIT DEFINITIONS
The following table defines the operation or each register bit. Bold indicates power−on default values.
Bit
Name
Type
Value
Description
VSEL0
Register Address: 00
Software buck enable. When EN pin is LOW, the regulator is off. When EN
pin is HIGH, BUCK_EN bit takes precedent.
7
BUCK_EN0
R/W
1
6:0
NSEL0
R/W
XXX XXXX
VSEL1
Sets VOUT value from 0.35 to 1.14375 V (see eq. 2).
Register Address: 01
Software buck enable. When EN pin is LOW, the regulator is off. When EN
pin is HIGH, BUCK_EN bit takes precedent.
7
BUCK_EN1
R/W
1
6:0
NSEL1
R/W
XXX XXXX
CONTROL
Sets VOUT value from 0.35 to 1.14375 V (see eq. 2).
Register Address: 02
OUTPUT_
DISCHARGE
0
When the regulator is disabled, VOUT is not discharged.
7
R/W
1
When the regulator is disabled, VOUT discharges through an internal pull−
down.
6:4
SLEW
R/W
000 –111
3
Reserved
2
RESET
1:0
MODE
R/W
R/W
Sets the slew rate for positive voltage transitions (see Table 11)
0
Always reads back 0.
0
Setting to 1 resets all registers to default values. Always reads back 0.
10
In combination with the VSEL pin, these two bits set the operation of the
buck to be either in Auto−PFM/PWM Mode during light load or Forced
PWM mode. See table below.
Mode of Operation
VSEL Pin Binary Operation
Low
Low
High
High
X0
X1
0X
1X
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14
Auto PFM/PWM
Forced PWM
Auto PFM/PWM
Forced PWM
FAN53528
Table 15. BIT DEFINITIONS (continued)
The following table defines the operation or each register bit. Bold indicates power−on default values.
Bit
Name
Type
Value
7:5
VENDOR
R
100
4
Reserved
R
0
3:0
DIE_ID
R
0001
ID1
Description
Register Address: 03
ID2
Signifies ON Semiconductor as the IC vendor.
Always reads back 0.
DIE ID
Register Address: 04
7:4
Reserved
R
0000
Always reads back 0000.
3:0
DIE_REV
R
1000
FAN53528 Die Revision
7
PGOOD
R
0
1: Buck is enabled and soft−start is completed.
6
UVLO
R
0
1: Signifies the VIN is less than the UVLO threshold.
5
OVP
R
0
1: Signifies the VIN is greater than the OVP threshold.
4
POS
R
0
1: Signifies a positive voltage transition is in progress and the output
voltage has not yet reached its new setpoint. This bit is also set during IC
soft−start.
3
NEG
R
0
1: Signifies a negative voltage transition is in progress and the output
voltage has not yet reached its new setpoint.
2
RESET_STAT
R
0
1: Indicates that a register reset was performed. This bit is cleared after
register 5 is read.
1
OT
R
0
1: Signifies the thermal shutdown is active.
0
BUCK_STATUS
R
0
1: Buck enabled; 0: buck disabled.
MONITOR
Register Address: 05
APPLICATION INFORMATION
Selecting the Inductor
The increased RMS current produces higher losses
through the RDS(ON) of the IC MOSFETs and the inductor
ESR.
Increasing the inductor value produces lower RMS
currents, but degrades transient response. For a given
physical inductor size, increased inductance usually results
in an inductor with lower saturation current.
The output inductor must meet both the required
inductance and the energy−handling capability of the
application. The inductor value affects the average current
limit, the output voltage ripple, and the efficiency.
The ripple current (ΔI) of the regulator is:
DI [
V OUT
V IN
ǒ
V IN*V OUT
L
f SW
Ǔ
Table 16. EFFECTS OF INDUCTOR VALUE (FROM
330 nH RECOMMENDED) ON REGULATOR
PERFORMANCE
(eq. 3)
The maximum average load current, IMAX(LOAD), is
related to the peak current limit, ILIM(PK), by the ripple
current such that:
I MAX(LOAD) + I LIM(PK)*
DI
2
(eq. 4)
ǸI
OUT(DC)
2
)
DI 2
12
DVOUT (eq. 7)
Transient Response
Increase
Decrease
Degraded
Inductor Current Rating
The FAN53528 is optimized for operation with
L=330 nH, but is stable with inductances up to 1.0 μH
(nominal). The inductor should be rated to maintain at least
80% of its value at ILIM(PK). Failure to do so decreases the
amount of DC current the IC can deliver.
Efficiency is affected by the inductor DCR and inductance
value. Decreasing the inductor value for a given physical
size typically decreases the DCR; but since ΔI increases, the
RMS current increases, as do core and skin−effect losses:
I RMS +
IMAX(LOAD)
The current−limit circuit can allow substantial peak
currents to flow through L1 under worst−case conditions. If
it is possible for the load to draw such currents, the inductor
should be capable of sustaining the current or failing in a safe
manner.
For space−constrained applications, a lower current rating
for L1 can be used. The FAN53528 may still protect these
inductors in the event of a short circuit, but may not be able
to protect the inductor from failure if the load is able to draw
higher currents than the DC rating of the inductor. Refer to
Table 2 for the recommended inductors.
(eq. 5)
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15
FAN53528
Output Capacitor and VOUT Ripple
Thermal Considerations
Heat is removed from the IC through the solder bumps to
the PCB copper. The junction−to−ambient thermal
resistance (θJA) is largely a function of the PCB layout (size,
copper weight, and trace width) and the temperature rise
from junction to ambient (ΔT).
For the FAN53528, θJA is 42°C/W when mounted on its
four−layer with vias evaluation board in still air with 2 oz.
outer layer copper weight and 1 oz. inner layer.
For long−term reliable operation, the junction
temperature (TJ) should be maintained below 125°C.
To calculate maximum operating temperature (
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