FAN7383M

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This literature is subject to all applicable copyright laws and is not for resale in any manner. FAN7383 Half-Bridge Gate-Drive IC Features Description „ Floating Channel Designed for Bootstrap Operation to The FAN7383 is a half-bridge gate-drive IC with shutdown and programmable dead-time control functions for driving MOSFETs and IGBTs that operate up to +600V. „ „ „ „ „ „ „ +600V. Typically 350mA/650mA Sourcing/Sinking Current Driving Capability for Both Channels Extended Allowable Negative VS Swing to -9.8V for Signal Propagation at VDD=VBS=15V High-Side Output in Phase of IN Signal Built-in UVLO Functions for Both Channels Built-in Common-Mode dv/dt Noise Canceling Circuit Typically Internal 330ns Minimum Dead-Time Programmable Turn-On Delay Time Control (Dead-Time) Fairchild’s high voltage process and common-mode noise canceling technique give stable operation of highside drivers under high-dv/dt noise circumstances. An advanced level-shift circuit allows high-side gate driver operation up to VS= -9.8V (typical) for VBS=15V. The UVLO circuits for both channels prevent malfunction when VDD and VBS are lower than the specified threshold voltage. Output drivers typically source/sink 350mA/650mA, respectively, which is suitable for all kinds of half and full bridge inverter. Applications „ SMPS „ Motor Drive Inverter 14-SOP „ Fluorescent Lamp Ballast „ HID Ballast 1 Ordering Information Part Number FAN7383M Package Pb-Free 14-SOP Yes Operating Temperature Range Packing Method (1) FAN7383MX(1) -40°C ~ 125°C Tube Tape & Reel Note: 1. These devices passed wave soldering test by JESD22A-111. © 2006 Fairchild Semiconductor Corporation FAN7383 Rev. 1.0.3 www.fairchildsemi.com FAN7383 Half-Bridge Gate-Drive IC February 2007 FAN7383 Half-Bridge Gate-Drive IC Typical Application Circuit RBOOT VDC DBOOT VDD PWM PWM IC Shutdown Control 1 IN 2 VB 14 SD HO1 13 3 DT HO2 12 4 VDD VS 11 5 LO1 NC 10 6 LO2 NC 9 7 GND NC 8 RHON RHOFF CBOOT RDT RLOFF RLON FAN7383 Rev.01 Figure 1. Application Circuit for Half-Bridge Switching Power Supply VDC VCC VDD PHA VDD VB VB HO1 HO1 HO2 HO2 IN VS VS PHB Forward IN M SD SD DC Motor Controller SD FAN7383 FAN7383 LO1 DT Reverse LO1 DT LO2 GND LO2 GND FAN7383 Rev.01 Figure 2. Application Circuit for Full-Bridge DC Motor Driver © 2006 Fairchild Semiconductor Corporation FAN7383 Rev. 1.0.3 www.fairchildsemi.com 2 14 VB 13 HO1 12 HO2 11 VS 4 VDD 5 LO1 6 LO2 7 GND UVLO 1 SD 2 SHOOT THOUGH PREVENTION DT 3 DEAD-TIME { DTMIN=330nsec } R DRIVER PULSE GENERATOR SCHMITT TRIGGER INPUT IN NOISE CANCELLER R S Q HS(ON/OFF) UVLO DELAY DRIVER LS(ON/OFF) FAN7383 Rev:01 Figure 3. Functional Block Diagram of FAN7383 © 2006 Fairchild Semiconductor Corporation FAN7383 Rev. 1.0.3 www.fairchildsemi.com 3 FAN7383 Half-Bridge Gate-Drive IC Internal Block Diagram FAN7383 Half-Bridge Gate-Drive IC Pin Configuration 1 14 VB SD 2 13 HO1 DT 3 12 HO2 VDD 4 11 VS LO1 5 10 NC LO2 6 9 NC GND 7 8 NC FAN7383 IN FAN7383 Rev:00 Figure 4. Pin Configuration (Top View) Pin Definitions Pin # Name Description 1 IN 2 SD Logic Input for Shutdown (Active Low) 3 DT Programmable Dead-Time Control with External Resistor 4 VDD Low-Side Supply Voltage 5 LO1 Low-Side Driver Source Output 6 LO2 Low-Side Driver Sink Output 7 GND Ground 8 N.C. Not connected 9 N.C. Not connected 10 N.C. 11 VS 12 HO2 High-Side Driver Sink Output 13 HO1 High-Side Driver Source Output 14 VB Logic Input for Gate Driver Not connected High-Side Floating Supply Return High-Side Floating Supply © 2006 Fairchild Semiconductor Corporation FAN7383 Rev. 1.0.3 www.fairchildsemi.com 4 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. TA = 25°C unless otherwise specified. Symbol Parameter VS High-side offset voltage VB High-side floating supply voltage Min. Max. Unit VB-25 VB+0.3 V -0.3 625 V VHO High-side floating output voltage HO1, HO2 VS-0.3 VB+0.3 V VDD Low-side and logic fixed supply voltage -0.3 25 V VLO Low-side output voltage LO1, LO2 -0.3 VDD+0.3 V VIN Logic input voltage (IN) -0.3 VDD+0.3 V VSD Shutdown logic input voltage -0.3 VDD+0.3 V VDT Dead-time control voltage -0.3 5.0 V GND Logic ground VDD-25 VDD+0.3 V 50 V/ns dVS/dt PD(2)(3)(4) Allowable offset voltage slew rate Power dissipation 1.0 W θJA Thermal resistance, junction-to-ambient 110 °C/W TJ Junction temperature 150 °C TSTG Storage temperature 150 °C Notes: 2. When mounted on 76.2 x 114.3 x 1.6mm PCB. (FR-4 glass epoxy material). 3. Please refer to: JESD51-2: Integral circuits thermal test method environmental conditions - Natural convection JESD51-3: Low effective thermal conductivity test board for leaded surface mount packages 4. Do not exceed PD under any circumstances. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Condition Min. Max. Unit VB High-side floating supply voltage VS+15 VS+20 V VS High-side floating supply offset voltage 6-VDD 600 V VDD Low-side supply voltage 15 20 V VHO High-side (HO) output voltage VS VB V VLO Low-side (LO) output voltage GND VDD V VIN Logic input voltage (IN) GND VDD V TA Ambient temperature -40 125 °C © 2006 Fairchild Semiconductor Corporation FAN7383 Rev. 1.0.3 www.fairchildsemi.com 5 FAN7383 Half-Bridge Gate-Drive IC Absolute Maximum Ratings VBIAS (VDD, VBS) = 15.0V, RDT = GND, TA = 25°C, unless otherwise specified. The VIN and IIN parameters are referenced to GND. The VO and IO parameters are referenced to VS and GND and are applicable to the respective outputs HO and LO. Symbol Parameter Condition Min. Typ. Max. Unit SUPPLY CURRENT SECTION IQBS Quiescent VBS supply current VIN=0V or 5V 35 90 IQDD Quiescent VDD supply current VIN=0V or 5V, RDT=0Ω 650 900 ISD(5) VDD supply current at shutdown mode SD=GND 650 900 IPBS Operating VBS supply current fIN=20kHz,rms value 400 700 IPDD Operating VDD supply current fIN=20kHz,rms value, RDT=0Ω 950 1200 ILK Offset supply leakage current VB=VS=600V μA 10 POWER SUPPLY SECTION VDDUV+ VBSUV+ VDD and VBS supply under-voltage positive going threshold 10.7 11.6 12.5 VDDUVVBSUV- VDD and VBS supply under-voltage negative going threshold 10.0 10.8 11.6 V VDDUVH VBSUVH VDD and VBS supply under-voltage lockout hysteresis 1.0 V 0.6 V 0.8 GATE DRIVER OUTPUT SECTION VOH High-level output voltage, VBIAS-VO IO=20mA VOL Low-level output voltage, VO IO+ Output high short-circuit pulse current VO=0V, VIN=5V with PW