FDBL86363_F085

MOSFET – POWERTRENCH) N-Channel 80 V, 240 A, 2.0 mW FDBL86363-F085 Features • • • • • www.onsemi.com Typical RDS(on) = 1.5 m at VGS = 10 V, ID = 80 A Typical Qg(tot) = 130 nC at VGS = 10 V, ID = 80 A UIS Capability AEC−Q101 Qualified and PPAP Capable These Devices are Pb−Free and are RoHS Compliant D Applications • • • • • G Automotive Engine Control PowerTrain Management Solenoid and Motor Drivers Integrated Starter/Alternator Primary Switch for 12 V Systems S N−Channel MOSFET MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Parameter Symbol Ratings Unit VDSS Drain−to−Source Voltage 80 V VGS Gate−to−Source Voltage ±20 V Drain Current − Continuous (VGS = 10), TC = 25°C (Note 1) 240 A ID Pulsed Drain Current, TC = 25°C See Figure 4 EAS Single Pulse Avalanche Energy (Note 2) 512 mJ PD Power Dissipation 357 W Derate Above 25°C 2.38 W/°C −55 to +175 °C 0.42 °C/W 43 °C/W TJ, TSTG Operating and Storage Temperature RJC Thermal Resistance, Junction to Case RJA Maximum Thermal Resistance, Junction to Ambient (Note 3) H−PSOF8L CASE 100CU MARKING DIAGRAM Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Current is limited by silicon. 2. Starting TJ = 25°C, L = 0.25 mH, IAS = 64 A, VDD = 80 V during inductor charging and VDD = 0 V during time in avalanche. 3. RJA is the sum of the junction−to−case and case−to−ambient thermal resistance, where the case thermal reference is defined as the solder mounting surface of the drain pins. RJC is guaranteed by design, while RJA is determined by the board design. The maximum rating presented here is based on mounting on a 1 in2 pad of 2oz copper. $Y&Z&3&K FDBL 86363 $Y &Z &3 &K FDBL86363 = ON Semiconductor Logo = Assembly Plant Code = Numeric Date Code = Lot Code = Specific Device Code ORDERING INFORMATION Device Top Mark Package Shipping{ FDBL86363 FDBL86363 H−PSOF8L 2000 Units/ −F085 Tape&Reel *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2015 January, 2020 − Rev. 3 1 Publication Order Number: FDBL86363−F085/D FDBL86363−F085 ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Parameter Symbol Test Conditions Min. Typ. Max. Unit OFF CHARACTERISTICS BVDSS IDSS IGSS Drain−to−Source Breakdown Voltage ID = 250 A, VGS = 0 V 80 − − V Drain−to−Source Leakage Current VDS = 80 V, VGS = 0 V TJ = 25°C − − 1 A TJ = 175°C (Note 4) − − 1 mA − − ±100 nA 2.0 3.0 4.0 V TJ = 25°C − 1.5 2.0 m TJ = 175°C (Note 4) − 3.1 4.1 m − 10000 − pF − 1540 − pF Gate−to−Source Leakage Current VGS = ±20 V ON CHARACTERISTICS VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 A RDS(on) Drain to Source on Resistance ID = 80 A, VGS = 10 V DYNAMIC CHARACTERISTICS Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Rg VDS = 40 V, VGS = 0 V, f = 1 MHz − 70 − pF Gate Resistance f = 1 MHz − 2.8 −  Total Gate Charge at 10 V − 130 169 nC − 18 27 nC − 47 − nC − 24 − nC − − 133 ns Threshold Gate Charge VGS = 0 to 10 V VDD = 64 V, ID = 80 A VGS = 0 to 2 V Qgs Gate−to−Source Gate Charge VDD = 64 V, ID = 80 A Qgd Gate−to−Drain “Miller” Charge Qg(ToT) Qg(th) SWITCHING CHARACTERISTICS ton Turn−On Time td(on) Turn−On Delay tr td(off) tf toff VDD = 40 V, ID = 80 A, VGS = 10 V, RGEN = 6  − 39 − ns Rise Time − 63 − ns Turn−Off Delay − 61 − ns Fall Time − 33 − ns Turn−Off Time − − 140 ns ISD = 80 A, VGS = 0 V − − 1.25 V ISD = 40 A, VGS = 0 V − − 1.2 V IF = 80 A, dISD/dt = 100 A/s, VDD = 64 V − 83 108 ns − 118 153 nC DRAIN−SOURCE DIODE CHARACTERISTIC VSD Source−to−Drain Diode Voltage trr Reverse−Recovery Time Qrr Reverse−Recovery Charge Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 4. The maximum value is specified by design at TJ = 175°C. Product is not tested to this condition in production. www.onsemi.com 2 FDBL86363−F085 TYPICAL CHARACTERISTICS 1.2 350 ID, Drain Current [A] Power Dissipation Multiplier 280 0.8 0.6 0.4 210 140 70 0.2 0.0 0 25 50 75 100 125 150 0 175 25 50 TC, Case Temperature [°C] 2 75 100 125 150 200 175 TC, Case Temperature [°C] Figure 1. Normalized Power Dissipation vs. Case Temperature ZJC, Normalized Thermal Impedance VGS = 10 V Current limited by silicon 1.0 Figure 2. Maximum Continuous Drain Current vs. Case Temperature DUTY CYCLE − DESCENDING ORDER 1 D = 0.50 0.20 0.10 0.05 0.02 0.01 0.1 PDM t1 t2 NOTES: Duty factor: D = t1 / t2 Peak TJ = PDM × ZJA × RJA + TC SINGLE PULSE 0.01 10−5 10−4 10−3 10−2 10−1 100 101 t, Rectangular Pulse Duration (s) Figure 3. Normalized Maximum Transient Thermal Impedance IDM, Peak Current [A] 10000 TC = 25°C For temperatures above 25°C derate peak current as follows: VGS = 10 V 1000 I + I2 ƪǸ 175 * T 150 C ƫ 100 SINGLE PULSE 10 10−5 10−4 10−3 10−2 t, Rectangular Pulse Duration (s) Figure 4. Peak Current Capability www.onsemi.com 3 10−1 100 101 FDBL86363−F085 TYPICAL CHARACTERISTICS (continued) 2000 1000 IAS, Avalanche Current [A] ID, Drain Current [A] 1000 100 100 s Operation in this area may be limited by rDS(on) 10 1 ms 1 SINGLE PULSE TJ = max rated TC = 25°C 0.1 0.1 1 10 ms 100 ms 10 100 Starting TJ = 25°C 10 Starting TJ = 150°C 1 0.001 500 100 If R = 0 tAV = (L)(IAS) / (1.3 × Rated BVDSS − VDD) If R ≠ 0 tAV = (L/R)ln[(IAS × R) / (1.3 × Rated BVDSS − VDD) + 1] 0.01 VDS, Drain to Source Voltage [V] 1 0.1 100 10 1000 tAV, Time in Avalanche [ms] NOTE: Refer to ON Semiconductor Application Notes AN7514 and AN7515. Figure 5. Forward Bias Safe Operating Area 350 400 Pulse duration = 80 s Duty cycle = 0.5% MAX VGS = 0 V IS, Reverse Drain Current [A] 300 ID, Drain Current [A] Figure 6. Unclamped Inductive Switching Capability VDD = 5 V 250 200 150 TJ = 25°C 100 TJ = −55°C TJ = 175°C 50 0 2 3 4 5 6 7 100 TJ = 175°C 10 TJ = 25°C 1 0.1 0.0 8 Figure 7. Transfer Characteristics 350 200 80 s Pulse Width TJ = 25°C 0 1 2 3 4 1.0 1.2 VGS 15 V Top 10 V 8V 7V 6V 5.5 V 5 V Bottom 250 200 150 100 80 s Pulse Width TJ = 175°C 50 50 0 0.8 300 150 100 0.6 350 ID, Drain Current [A] ID, Drain Current [A] 250 0.4 Figure 8. Forward Diode Characteristics VGS 15 V Top 10 V 8V 7V 6V 5.5 V 5 V Bottom 300 0.2 VSD, Body Diode Forward Voltage [V] VGS, Gate to Source Voltage [V] 0 5 0 1 2 3 4 VDS, Drain to Source Voltage [V] VDS, Drain to Source Voltage [V] Figure 9. Saturation Characteristics Figure 10. Saturation Characteristics www.onsemi.com 4 5 FDBL86363−F085 TYPICAL CHARACTERISTICS (continued) ID = 80 A 2.4 Pulse duration = 80 s Duty cycle = 0.5% MAX Normalized Drain to Source On−Resistance rDS(on), Drain to Source On−Resistance [m] 50 40 30 TJ = 175°C TJ = 25°C 20 10 0 2 4 6 8 Pulse duration = 80 s Duty cycle = 0.5% MAX 2.0 1.6 1.2 ID = 80 A VGS = 10 V 0.8 0.4 −80 10 −40 0 VGS, Gate to Source Voltage [V] Figure 11. RDSON vs. Gate Voltage 1.10 VGS = VDS ID = 250 A 1.2 0.9 0.6 0.3 0.0 −80 −40 0 40 80 120 160 0.95 0.90 −80 200 −40 0 VGS, Gate to Source Voltage [V] Capacitance [pF] 80 120 160 200 Figure 14. Normalized Drain to Source Breakdown Voltage vs. Junction Temperature Ciss Coss 1000 Crss f = 1 MHz VGS = 0 V 10 40 TJ, Junction Temperature [°C] 10 1 200 1.00 100000 10 0.1 160 1.05 Figure 13. Normalized Gate Threshold Voltage vs. Temperature 100 120 ID = 5 mA TJ, Junction Temperature [°C] 10000 80 Figure 12. Normalized RDSON vs. Junction Temperature Normalized Drain to Source Breakdown Voltage Normalized Gate Threshold Voltage 1.5 40 TJ, Junction Temperature [°C] 8 VDD = 32 V 40 V 48 V 6 4 2 0 100 ID = 80 A 0 30 60 90 120 150 Qg, Gate Charge [nC] VDS, Drain to Source Voltage [V] Figure 15. Capacitance vs. Drain to Source Voltage Figure 16. Gate Charge vs. Gate to Source Voltage POWERTRENCH is registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. www.onsemi.com 5 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS H−PSOF8L 11.68x9.80 CASE 100CU ISSUE B DATE 20 MAY 2022 GENERIC MARKING DIAGRAM* AYWWZZ XXXXXXXX XXXXXXXX A Y WW ZZ XXXX DOCUMENT NUMBER: DESCRIPTION: = Assembly Location = Year = Work Week = Assembly Lot Code = Specific Device Code 98AON13813G H−PSOF8L 11.68x9.80 *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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