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FDMD82100L
Dual N-Channel PowerTrench® MOSFET
100 V, 24 A, 19.5 mΩ
Features
General Description
Max rDS(on) = 19.5 mΩ at VGS = 10 V, ID = 7 A
This device includes two 100V N-Channel MOSFETs in a dual
Power (3.3 mm X 5 mm) package. HS source and LS Drain
internally connected for half/full bridge, low source inductance
package, low rDS(on)/Qg FOM silicon.
Max rDS(on) = 30 mΩ at VGS = 4.5 V, ID = 5.7 A
Ideal for flexible layout in primary side of bridge topology
Termination is Lead-free and RoHS Compliant
Applications
100% UIL tested
Synchronous Buck : Primary Switch of Half / Full bridge
converter for telecom
Kelvin High Side MOSFET drive pin-out capability
Motor Bridge : Primary Switch of Half / Full bridge converter
for BLDC motor
MV POL : 48V Synchronous Buck Switch
Pin 1
D1
1
12 G1
D1
2
11
D1
3
10 D2/S1
G2
4
9
D2/S1
S2
5
8
D2/S1
S2
6
7
D2/S1
G1R
Power 3.3 x 5
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Symbol
VDS
Drain to Source Voltage
Parameter
VGS
Gate to Source Voltage
Drain Current
-Continuous
ID
TC = 25 °C
TJ, TSTG
±20
V
24
-Continuous
TA = 25 °C
(Note 1a)
7
TA = 25 °C
(Note 4)
80
(Note 3)
150
Power Dissipation
PD
Units
V
-Pulsed
Single Pulse Avalanche Energy
EAS
Ratings
100
TC = 25 °C
A
mJ
38
Power Dissipation
TA = 25 °C
(Note 1a)
2.1
Power Dissipation
TA = 25 °C
(Note 1b)
1
Operating and Storage Junction Temperature Range
-55 to +150
W
°C
Thermal Characteristics
RθJC
Thermal Resistance, Junction to Case
3.3
RθJA
Thermal Resistance, Junction to Ambient
(Note 1a)
60
RθJA
Thermal Resistance, Junction to Ambient
(Note 1b)
130
°C/W
Package Marking and Ordering Information
Device Marking
82100L
Device
FDMD82100L
©2014 Fairchild Semiconductor Corporation
FDMD82100L Rev.C1
Package
Power 3.3 x 5
1
Reel Size
13 ’’
Tape Width
12 mm
Quantity
3000 units
www.fairchildsemi.com
FDMD82100L Dual N-Channel PowerTrench® MOSFET
June 2014
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
ID = 250 μA, VGS = 0 V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient
ID = 250 μA, referenced to 25 °C
IDSS
Zero Gate Voltage Drain Current
VDS = 80 V, VGS = 0 V
1
μA
IGSS
Gate to Source Leakage Current
VGS = ±20 V, VDS = 0 V
±100
nA
3.0
V
100
V
70
mV/°C
On Characteristics
VGS(th)
Gate to Source Threshold Voltage
VGS = VDS, ID = 250 μA
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient
ID = 250 μA, referenced to 25 °C
VGS = 10 V, ID = 7 A
13.5
rDS(on)
Static Drain to Source On Resistance
VGS = 4.5 V, ID = 5.7 A
17.9
30
VGS = 10 V, ID = 7 A, TJ = 125 °C
25
36
VDD = 5 V, ID = 7 A
29
gFS
Forward Transconductance
1.0
1.7
-6
mV/°C
19.5
mΩ
S
Dynamic Characteristics
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
Rg
Gate Resistance
VDS = 50 V, VGS = 0 V
f = 1 MHz
0.1
1130
1585
pF
173
245
pF
8.1
15
pF
1.8
3.6
Ω
7.9
16
ns
2.8
10
ns
21
34
ns
Switching Characteristics
td(on)
Turn-On Delay Time
tr
Rise Time
td(off)
Turn-Off Delay Time
tf
Fall Time
Qg(TOT)
VDD = 50 V, ID = 7 A
VGS = 10 V, RGEN = 6 Ω
2.9
10
ns
Total Gate Charge
VGS = 0 V to 10 V
17
24
nC
Total Gate Charge
VGS = 0 V to 4.5 V VDD = 50 V
ID = 7 A
8
12
3
nC
2.3
nC
Qgs
Gate to Source Charge
Qgd
Gate to Drain “Miller” Charge
nC
Drain-Source Diode Characteristics
VSD
Source to Drain Diode Forward Voltage
trr
Reverse Recovery Time
Qrr
Reverse Recovery Charge
VGS = 0 V, IS = 7 A
(Note 2)
IF = 7 A, di/dt = 100 A/μs
0.8
1.2
V
42
67
ns
39
62
nC
NOTES:
1. RθJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by
the user's board design.
b. 130 °C/W when mounted on
a minimum pad of 2 oz copper
a. 60 °C/W when mounted on
a 1 in2 pad of 2 oz copper
SS
SF
DS
DF
G
SS
SF
DS
DF
G
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0 %.
3. EAS of 150 mJ is based on starting TJ = 25 oC, L = 3 mH, IAS = 10 A, VDD = 90 V, VGS = 10 V. 100% tested at L = 0.1 mH, IAS = 31 A.
4. Pulse Id refers to Figure.11 Forward Bias Safe Operation Area.
©2014 Fairchild Semiconductor Corporation
FDMD82100L Rev.C1
2
www.fairchildsemi.com
FDMD82100L Dual N-Channel PowerTrench® MOSFET
Electrical Characteristics TJ = 25 °C unless otherwise noted
5
VGS = 10 V
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
ID, DRAIN CURRENT (A)
80
VGS = 6 V
VGS = 4.5 V
60
VGS = 4 V
40
VGS = 3.5 V
20
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 3 V
0
0
1
2
3
4
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 3 V
4
VGS = 3.5 V
3
VGS = 4 V
2
1
0
20
rDS(on), DRAIN TO
1.6
1.2
0.8
SOURCE ON-RESISTANCE (mΩ)
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
80
100
ID = 7 A
VGS = 10 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
80
ID = 7 A
60
40
TJ = 125 oC
20
TJ = 25 oC
0
-50
-25
0
25
50
75
100 125 150
2
TJ, JUNCTION TEMPERATURE (oC)
4
6
8
10
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 3. Normalized On Resistance
vs Junction Temperature
Figure 4. On-Resistance vs Gate to
Source Voltage
80
IS, REVERSE DRAIN CURRENT (A)
80
TJ
I D, DRAIN CURRENT (A)
60
Figure 2. Normalized On-Resistance
vs Drain Current and Gate Voltage
2.4
= -55 oC
TJ = 150 oC
60
T J = 25 oC
40
VDS = 5 V
20
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
0
40
ID, DRAIN CURRENT (A)
Figure 1. On Region Characteristics
0.4
-75
VGS = 10 V
0
5
VDS, DRAIN TO SOURCE VOLTAGE (V)
2.0
VGS = 6 V
VGS = 4.5 V
1
2
3
4
5
6
TJ = 150 oC
1
TJ = 25 oC
0.1
TJ = -55 oC
0.01
0.001
0.0
7
VGS, GATE TO SOURCE VOLTAGE (V)
0.2
0.4
0.6
0.8
1.0
1.2
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics
©2014 Fairchild Semiconductor Corporation
FDMD82100L Rev.C1
VGS = 0 V
10
Figure 6. Source to Drain Diode
Forward Voltage vs Source Current
3
www.fairchildsemi.com
FDMD82100L Dual N-Channel PowerTrench® MOSFET
Typical Characteristics (N-Channel) TJ = 25 °C unless otherwise noted
2000
ID = 7 A
1000
Ciss
8
VDD = 75 V
Coss
CAPACITANCE (pF)
VGS, GATE TO SOURCE VOLTAGE (V)
10
6
VDD = 50 V
4
VDD = 25 V
100
Crss
10
2
f = 1 MHz
VGS = 0 V
0
0
3
6
9
12
15
1
0.1
18
1
10
100
VDS, DRAIN TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
Figure 7. Gate Charge Characteristics
Figure 8. Capacitance vs Drain
to Source Voltage
100
40
o
ID, DRAIN CURRENT (A)
IAS, AVALANCHE CURRENT (A)
RθJC = 3.3 C/W
TJ = 25 oC
TJ = 100 oC
10
TJ = 150 oC
1
0.001
0.01
0.1
1
10
30
VGS = 10 V
20
Limited by Package
VGS = 4.5 V
10
0
25
100
50
10 μ s
10
1000
100 μs
SINGLE PULSE
T J = MAX RATED
1 ms
10 ms
DC
R θJC = 3.3 o C/W
0.1
T C = 25 o C
CURVE BENT TO
MEASURED DATA
0.01
0.1
150
10000
THIS AR EA
IS LIMITED
BY r DS(on)
1
125
Figure 10. Maximum Continuous Drain
Current vs Case Temperature
P(PK), PEAK TRANSIENT POWER (W)
I D , DRAIN CURRENT (A)
100
100
TC, CASE TEMPERATURE ( C)
Figure 9. Unclamped Inductive
Switching Capability
300
75
o
tAV, TIME IN AVALANCHE (ms)
1
10
100
300
VDS, DRAIN to SOURCE VOLTAGE (V)
TC = 25 oC
100
10
-5
10
-4
10
-3
10
-2
10
-1
10
1
t, PULSE WIDTH (sec)
Figure 11. Forward Bias Safe
Operating Area
©2014 Fairchild Semiconductor Corporation
FDMD82100L Rev.C1
SINGLE PULSE
RθJC = 3.3 oC/W
Figure 12. Single Pulse Maximum
Power Dissipation
4
www.fairchildsemi.com
FDMD82100L Dual N-Channel PowerTrench® MOSFET
Typical Characteristics (N-Channel) TJ = 25 °C unless otherwise noted
r(t), NORMALIZED EFFECTIVE TRANSIENT
THERMAL RESISTANCE
2
1
0.1
DUTY CYCLE-DESCENDING ORDER
D = 0.5
0.2
0.1
0.05
0.02
0.01
PDM
t1
t2
0.01
NOTES:
SINGLE PULSE
0.001
-5
10
ZθJC(t) = r(t) x RθJC
RθJC = 3.3 oC/W
Peak TJ = PDM x ZθJC(t) + TC
Duty Cycle, D = t1 / t2
-4
10
-3
-2
10
10
-1
10
1
t, RECTANGULAR PULSE DURATION (sec)
Figure 13. Junction-to-Ambient Transient Thermal Response Curve
©2014 Fairchild Semiconductor Corporation
FDMD82100L Rev.C1
5
www.fairchildsemi.com
FDMD82100L Dual N-Channel PowerTrench® MOSFET
Typical Characteristics (N-Channel) TJ = 25 °C unless otherwise noted
FDMD82100L Dual N-Channel PowerTrench® MOSFET
Dimensional Outline and Pad Layout
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
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Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
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©2014 Fairchild Semiconductor Corporation
FDMD82100L Rev.C1
6
www.fairchildsemi.com
tm
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Datasheet contains the design specifications for product development. Specifications
may change in any manner without notice.
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Datasheet contains preliminary data; supplementary data will be published at a later
date. Fairchild Semiconductor reserves the right to make changes at any time without
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Datasheet contains specifications on a product that is discontinued by Fairchild
Semiconductor. The datasheet is for reference information only.
Rev. I68
©2014 Fairchild Semiconductor Corporation
FDMD82100L Rev.C1
7
www.fairchildsemi.com
FDMD82100L Dual N-Channel PowerTrench® MOSFET
TRADEMARKS
The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not
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Marking Small Speakers Sound Louder
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