FDMF3037

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This literature is subject to all applicable copyright laws and is not for resale in any manner. FDMF3037 –Smart Power Stage (SPS) Module Features Description   Supports PS4 Mode for IMVP-8     High Current Handling: 35 A The SPS family is Fairchild’s next-generation, fully optimized, ultra-compact, integrated MOSFET plus driver power stage solution for high-current, highfrequency, synchronous buck, DC-DC applications. The FDMF3037 integrates a driver IC with a bootstrap Schottky diode and two power MOSFETs into a thermally enhanced, ultra-compact 5 mm x 5 mm package.  Fairchild PowerTrench MOSFETs for Clean Voltage Waveforms and Reduced Ringing  Fairchild SyncFET™ Technology (Integrated Schottky Diode) in Low-Side MOSFET      Integrated Bootstrap Schottky Diode  Fairchild Green Packaging and RoHS Compliance Ultra-Compact 5 mm x 5 mm PQFN Copper-Clip Package with Flip Chip Low-Side MOSFET 3-State 5 V PWM Input Gate Driver Low Shutdown Current: IVCC < 6 µA Diode Emulation for Enhanced Light Load Efficiency ® With an integrated approach, the SPS switching power stage is optimized for driver and MOSFET dynamic performance, minimized system inductance, and power MOSFET RDS(ON). The SPS family uses Fairchild's high® performance PowerTrench MOSFET technology, which reduces switch ringing, eliminating the need for a snubber circuit in most buck converter applications. Optimized for Switching Frequencies up to 1.5 MHz A driver IC with reduced dead times and propagation delays further enhances the performance. The FDMF3037 supports diode emulation (using FCCM pin) for improved light-load efficiency. The FDMF3037 also provides a 3-state 5 V PWM input for compatibility with a wide range of PWM controllers. Operating Junction Temperature Range: -40°C to +125°C Applications Optimized / Extremely Short Dead-Times Under-Voltage Lockout (UVLO) on VCC  Notebook, Tablet PC and Ultrabook  Servers and Workstations, V-Core and Non-V-Core DC-DC Converters  Desktop and All-in-One Computers, V-Core and Non-V-Core DC-DC Converters  High-Current DC-DC Point-of-Load Converters  Small Form-Factor Voltage Regulator Modules Ordering Information Part Number Current Rating Package Top Mark FDMF3037 35 A 31-Lead, Clip Bond PQFN SPS, 5.0 mm x 5.0 mm Package FDMF3037 © 2015 Fairchild Semiconductor Corporation FDMF3037 • Rev. 1.4 www.fairchildsemi.com FDMF3037 — Smart Power Stage (SPS) Module September 2015 FDMF3037 — Smart Power Stage (SPS) Module Application Diagram V5V VIN CPVCC PVCC PWM Input CVCC RVCC VCC CVIN VIN GL PWM RBOOT BOOT FDMF3037 CBOOT PHASE LOUT FCCM FCCM Input SW VOUT VSW AGND Figure 1. PGND COUT Typical Application Diagram Functional Block Diagram VCC PVCC BOOT VCC VIN PHASE DBoot ↓ 10uA ↓ 10uA (Q1) High Side MOSFET FCCM LEVEL SHIFT SW SHOOT- THROUGH PROTECTION 10k PWM HDRV (Q2) Low Side MOSFET PVCC CONTROL LOGIC LDRV GL PGND AGND Figure 2. © 2015 Fairchild Semiconductor Corporation FDMF3037 • Rev. 1.4 Functional Block Diagram www.fairchildsemi.com 2 FCCM PWM 8 7 6 5 4 3 2 1 31 30 N/C 29 PVCC 28 PGND PGND 27 GL PGND 26 SW PGND 14 SW PGND 15 FDMF3037 11 N/C 13 30 12 10 SW VIN VIN 10 31 9 9 25 1 24 2 VCC 3 AGND 4 BOOT 5 N/C 6 PHASE 7 VIN 8 32 AGND 29 11 VIN 28 16 17 18 19 20 Figure 3. 21 22 23 16 17 18 19 20 21 22 23 SW 24 SW 15 SW 25 SW 14 SW 26 SW 13 33 GL SW 27 SW 12 Pin Configuration - Top View and Transparent View Pin Definitions Pin # Name Description 1 PWM PWM input to the gate driver IC 2 FCCM The FCCM pin enables or disables Diode Emulation. When FCCM is LOW, diode emulation is allowed. When FCCM is HIGH, continuous conduction mode is forced. High impedance on the input of FCCM will shut down the driver IC (and module). 3 VCC 4, 32 AGND Analog ground for analog portions of the IC and for substrate, pin 4 and pin 32 are internally fused (shorted) 5 BOOT Supply for high-side MOSFET gate driver. A capacitor from BOOT to PHASE supplies the charge to turn on the N-channel high-side MOSFET. During the freewheeling interval (LS MOSFET on), the high side capacitor is recharged by an internal diode connected to PVCC. 6, 30, 31 N/C 7 PHASE Power supply input for all analog control functions; this is the “quiet” VCC No connect Return connection for the boot capacitor 8~11 VIN Power input for the power stage 12~15, 28 PGND Power return for the power stage 16~26 SW Switching node junction between high and low side MOSFETs; also the input into both the gate driver SW node comparator and the ZCD comparator 27, 33 GL Low-side MOSFET gate monitor 29 PVCC (1) Power supply input for LS gate driver and boot diode Note: 1. LS = Low Side. © 2015 Fairchild Semiconductor Corporation FDMF3037 • Rev. 1.4 www.fairchildsemi.com 3 FDMF3037 — Smart Power Stage (SPS) Module Pin Configuration Stresses exceeding the Absolute Maximum Ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. TA = TJ = 25°C Symbol VCC Parameter Min. Max. Unit Supply Voltage Referenced to AGND -0.3 7.0 V PVCC Drive Voltage Referenced to AGND -0.3 7.0 V VPWM PWM Signal Input Referenced to AGND -0.3 VCC+0.3 V VFCCM Skip Mode Input Referenced to AGND -0.3 VCC+0.3 V VGL Low Gate Manufacturing Test Pin Referenced to PGND (DC) GND-0.3 VCC+0.3 V Referenced to PGND (AC < 20 ns, 10 µJ) GND-0.3 VCC+0.3 V VIN Power Input Referenced to PGND -0.3 30.0 V Referenced to PGND (DC) -0.3 30.0 Referenced to PGND (AC < 20 ns, 10 µJ) -8.0 30.0 Referenced to AGND (DC) -0.3 33.0 V DC -0.3 7.0 V AC < 20 ns, 10 µJ -0.3 9.0 V VPHASE VSW PHASE and SW VBOOT Bootstrap Supply VBOOT-PHASE Boot to PHASE Voltage IO(AV) (2) θJ-A θJ-PCB Output Current fSW=300 kHz, VIN=12 V, VOUT=1 V 35 fSW=1000 kHz, VIN=12 V, VOUT=1 V 30 V A Junction-to-Ambient Thermal Resistance 12.4 °C/W Junction-to-PCB Thermal Resistance (under Fairchild SPS Thermal Board) 1.8 °C/W +125 °C +150 °C +150 °C TA Ambient Temperature Range TJ Maximum Junction Temperature TSTG Storage Temperature Range ESD Electrostatic Discharge Protection -40 -55 Human Body Model, JESD22-A114 1.5 Charged Device Model, JESD22-C101 2.5 kV Note: 2. IO(AV) is rated with testing Fairchild’s SPS evaluation board at TA = 25°C with natural convection cooling. This rating is limited by the peak SPS temperature, TJ = 150°C, and varies depending on operating conditions and PCB layout. This rating may be changed with different application settings. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended Operating Conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol VCC PVCC Parameter Min. Typ. Max. Unit Control Circuit Supply Voltage 4.5 5.0 5.5 V Gate Drive Circuit Supply Voltage 4.5 5.0 5.5 V (3) (4) VIN Output Stage Supply Voltage 4.5 12.0 24.0 V Notes: 3. 3.0 V VIN is possible according to the application condition. 4. Operating at high VIN can create excessive AC voltage overshoots on the SW-to-GND and BOOT-to-GND nodes during MOSFET switching transient. For reliable SPS operation, SW to GND and BOOT to GND must remain at or below the Absolute Maximum Ratings in the table above. © 2015 Fairchild Semiconductor Corporation FDMF3037 • Rev. 1.4 www.fairchildsemi.com 4 FDMF3037 — Smart Power Stage (SPS) Module Absolute Maximum Ratings Typical value is under VIN=12 V, VCC=PVCC=5 V and TA=TJ=+ 25°C unless otherwise noted. Minimum / Maximum values are under VIN=12 V, VCC=PVCC=5 V ± 10% and TJ=TA=-40 ~ 125°C unless otherwise noted. Symbol Parameter Condition Min. Typ. Max. Unit 11 µA Basic Operation ICC_SD Quiescent Current with PWM and FCCM pin floating (PS4 mode) ICC=IVCC + IPVCC, PWM=Floating, FCCM=Floating (Non-Switching) 6 ICC_HIGH Quiescent Current with PWM pin ICC=IVCC + IPVCC, PWM=Floating, floating and VFCCM = 5V FCCM=5 V 80 µA ICC_LOW Quiescent Current with PWM pin ICC=IVCC + IPVCC, PWM=Floating, floating and VFCCM = 0V FCCM=0 V 120 µA VUVLO_RISE UVLO Rising Threshold VCC Rising VUVLO_FALL UVLO Falling Threshold VCC Falling 3.4 tD_POR POR Delay to Enable IC VCC UVLO Rising to Internal PWM Enable IFCCM_HIGH Pull-Up Current VFCCM=5 V 50 µA IFCCM_LOW Pull-Down Current VFCCM=0 V -50 µA 2.5 3.9 3.0 V V 15 µs FCCM Input VIH_FCCM FCCM High Level Input Voltage VCC=PVCC=5 V 3.8 VTRI_FCCM FCCM 3-State Window VCC=PVCC=5 V 2.2 VIL_FCCM FCCM Low Level Input Voltage tPS_EXIT V 2.8 V VCC=PVCC=5 V 1.0 V PS4 Exit Latency VCC=PVCC=5 V 15 µs IPWM_HIGH Pull-Up Current VFCCM=5 V IPWM_LOW Pull-Down Current VFCCM=0 V VIH_PWM PWM High Level Input Voltage VCC=PVCC=5 V 4.1 VTRI_PWM PWM 3-State Window VCC=PVCC=5 V 1.6 VIL_PWM PWM Low Level Input Voltage VCC=PVCC=5 V 3-State Shut-off Time VCC=PVCC=5 V, TJ=25°C PWM Input tD_HOLD-OFF 100 250 µA -250 µA V 3.4 175 V 0.7 V 250 ns PWM Propagation Delays & Dead Times (VIN=12 V, VCC=PVCC=5 V, fSW=1 MHz, IOUT=20 A, TA=25°C) tPD_PHGLL PWM HIGH Propagation Delay PWM Going HIGH to GL Going LOW, VIH_PWM to 90% GL 25 ns tPD_PLGHL PWM LOW Propagation Delay PWM Going LOW to GH(5) Going LOW, VIL_PWM to 90% GH 15 ns tPD_PHGHH PWM HIGH Propagation Delay (FCCM Held LOW) PWM Going HIGH to GH Going HIGH, VIH_PWM to 10% GH (FCCM=LOW, IL=0, Assumes DCM) 15 ns tPD_TSGHH Exiting 3-State Propagation Delay PWM (from 3-State) Going HIGH to GH Going HIGH, VIH_PWM to 10% GH 35 ns tPD_TSGLH Exiting 3-State Propagation Delay PWM (from 3-State) Going LOW to GL Going HIGH, VIL_PWM to 10% GL 35 ns tD_DEADON LS Off to HS On Adaptive Dead Time SW