FDMS8350L

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This literature is subject to all applicable copyright laws and is not for resale in any manner. FDMS8350L N-Channel PowerTrench® MOSFET 40 V, 290 A, 0.85 mΩ Features General Description This N-Channel MOSFET is produced using Fairchild Semiconductor‘s advanced PowerTrench® process that has been especially tailored to minimize the on-state resistance and yet maintain superior switching performance. „ Max rDS(on) = 0.85 mΩ at VGS = 10 V, ID = 47 A „ Max rDS(on) = 1.2 mΩ at VGS = 4.5 V, ID = 38 A „ Advanced Package and Silicon combination for low rDS(on) and high efficiency „ MSL1 robust package design Applications „ 100% UIL tested „ Primary DC-DC MOSFET „ RoHS Compliant „ Secondary Synchronous Rectifier „ Load Switch Bottom Top S S Pin 1 D D D S Pin 1 S D G S D S D G D D Power 56 MOSFET Maximum Ratings TA = 25 °C unless otherwise noted Symbol VDS Drain to Source Voltage Parameter VGS Gate to Source Voltage Drain Current -Continuous ID TC = 25 °C TJ, TSTG ±20 V (Note 5) 290 -Continuous TC = 100 °C (Note 5) 183 TA = 25 °C (Note 1a) 47 (Note 4) 1737 (Note 3) 800 -Pulsed PD Units V -Continuous Single Pulse Avalanche Energy EAS Ratings 40 Power Dissipation TC = 25 °C Power Dissipation TA = 25 °C 113 (Note 1a) Operating and Storage Junction Temperature Range 2.7 -55 to + 150 A mJ W °C Thermal Characteristics RθJC Thermal Resistance, Junction to Case RθJA Thermal Resistance, Junction to Ambient 1.1 (Note 1a) 45 °C/W Package Marking and Ordering Information Device Marking FDMS8350L Device FDMS8350L ©2014 Fairchild Semiconductor Corporation FDMS8350L Rev.1.8 Package Power 56 1 Reel Size 13 ’’ Tape Width 12 mm Quantity 3000 units www.fairchildsemi.com FDMS8350L N-Channel PowerTrench® MOSFET March 2015 Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C IDSS Zero Gate Voltage Drain Current VDS = 32 V, VGS = 0 V 1 μA IGSS Gate to Source Leakage Current VGS = ±20 V, VDS = 0 V ±100 nA 3 V 40 V 25 mV/°C On Characteristics VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 μA ΔVGS(th) ΔTJ Gate to Source Threshold Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C VGS = 10 V, ID = 47 A 0.71 rDS(on) Static Drain to Source On Resistance VGS = 4.5 V, ID = 38 A 0.91 1.2 VGS = 10 V, ID = 47 A, TJ = 125 °C 0.94 1.2 VDS = 5 V, ID = 47 A 260 gFS Forward Transconductance 1 1.5 -6 mV/°C 0.85 mΩ S Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Rg Gate Resistance VDS = 20 V, VGS = 0 V, f = 1 MHz 0.1 12500 17500 pF 3430 4800 pF 136 190 pF 1 3 Ω 29 47 ns 22 36 ns 83 133 ns 18 33 ns nC Switching Characteristics td(on) Turn-On Delay Time tr Rise Time td(off) Turn-Off Delay Time tf Fall Time VDD = 20 V, ID = 47 A, VGS = 10 V, RGEN = 6 Ω Qg Total Gate Charge VGS = 0 V to 10 V 173 242 Qg Total Gate Charge 80 113 Qgs Gate to Source Charge VGS = 0 V to 4.5 V VDD = 20 V, ID = 47 A Qgd Gate to Drain “Miller” Charge nC 30 nC 18 nC Drain-Source Diode Characteristics VSD Source to Drain Diode Forward Voltage trr Reverse Recovery Time Qrr Reverse Recovery Charge VGS = 0 V, IS = 2.1 A (Note 2) 0.65 1.2 VGS = 0 V, IS = 47 A (Note 2) 0.76 1.3 IF = 47 A, di/dt = 100 A/μs V 72 116 ns 64 103 nC Notes: 1. RθJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθCA is determined by the user's board design. b. 115 °C/W when mounted on a minimum pad of 2 oz copper. a. 45 °C/W when mounted on a 1 in2 pad of 2 oz copper. SS SF DS DF G SS SF DS DF G 2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%. 3. EAS of 800 mJ is based on starting TJ = 25 °C, L = 1 mH, IAS = 40 A, VDD = 36 V, VGS = 10 V. 100% test at L = 0.1 mH, IAS = 86 A. 4. Pulsed Id please refer to Fig 11 SOA graph for more details. 5. Computed continuous current limited to Max Junction Temperature only, actual continuous current will be limited by thermal & electro-mechanical application board design. ©2014 Fairchild Semiconductor Corporation FDMS8350L Rev.1.8 2 www.fairchildsemi.com FDMS8350L N-Channel PowerTrench® MOSFET Electrical Characteristics TJ = 25 °C unless otherwise noted VGS = 10 V VGS = 4.5 V 240 VGS = 4 V VGS = 3.5 V 180 120 VGS = 3 V 60 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 0 0.0 0.5 1.0 1.5 VDS, DRAIN TO SOURCE VOLTAGE (V) 5 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE ID, DRAIN CURRENT (A) 300 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 4 VGS = 3 V 3 VGS = 3.5 V 2 1 0 2.0 0 60 120 180 240 300 Figure 2. Normalized On-Resistance vs Drain Current and Gate Voltage 4 1.6 ID = 47 A VGS = 10 V 1.5 SOURCE ON-RESISTANCE (mΩ) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE VGS = 10 V VGS = 4.5 V ID, DRAIN CURRENT (A) Figure 1. On Region Characteristics rDS(on), DRAIN TO 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 -75 -50 300 IS, REVERSE DRAIN CURRENT (A) VDS = 5 V 180 TJ = 150 oC 120 TJ = 25 oC 60 TJ = -55 oC 2.0 2.5 3.0 3.5 2 TJ = 125 oC 1 TJ = 25 oC 2 4 6 8 10 1000 VGS = 0 V 100 TJ = 150 oC 10 TJ = 25 oC 1 0.1 TJ = -55 oC 0.01 0.001 0.0 4.0 VGS, GATE TO SOURCE VOLTAGE (V) 0.2 0.4 0.6 0.8 1.0 1.2 VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 6. Source to Drain Diode Forward Voltage vs Source Current Figure 5. Transfer Characteristics ©2014 Fairchild Semiconductor Corporation FDMS8350L Rev.1.8 3 Figure 4. On-Resistance vs Gate to Source Voltage 240 1.5 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX VGS, GATE TO SOURCE VOLTAGE (V) PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 0 1.0 ID = 47 A 0 -25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (oC) Figure 3. Normalized On Resistance vs Junction Temperature ID, DRAIN CURRENT (A) VGS = 4 V 3 www.fairchildsemi.com FDMS8350L N-Channel PowerTrench® MOSFET Typical Characteristics TJ = 25 °C unless otherwise noted ID = 47 A Ciss VDD = 15 V 10000 8 CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 50000 10 VDD = 20 V 6 VDD = 25 V 4 Coss 1000 Crss 100 2 f = 1 MHz VGS = 0 V 0 0 25 50 75 100 125 150 10 0.1 175 1 10 40 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) Figure 7. Gate Charge Characteristics Figure 8. Capacitance vs Drain to Source Voltage 300 500 o ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) RθJC = 1.1 C/W 100 TJ = 25 oC TJ = 100 oC 10 TJ = 1 0.001 0.01 0.1 125 oC 1 10 100 240 180 VGS = 10 V 120 VGS = 4.5 V 60 0 25 1000 10000 50 P(PK), PEAK TRANSIENT POWER (W) ID, DRAIN CURRENT (A) 150 50000 1000 10 μs 10000 100 100 μs THIS AREA IS LIMITED BY rDS(on) 1 ms SINGLE PULSE TJ = MAX RATED 10 ms o RθJC = 1.1 C/W TC = 25 oC 0.1 0.1 125 Figure 10. Maximum Continuous Drain Current vs Case Temperature 3000 1 100 o Figure 9. Unclamped Inductive Switching Capability 10 75 TC, CASE TEMPERATURE ( C) tAV, TIME IN AVALANCHE (ms) CURVE BENT TO MEASURED DATA 1 10 DC 100 VDS, DRAIN to SOURCE VOLTAGE (V) SINGLE PULSE RθJC = 1.1 oC/W TC = 25 oC 100 -5 10 -4 10 -3 10 -2 10 -1 10 1 t, PULSE WIDTH (sec) Figure 11. Forward Bias Safe Operating Area ©2014 Fairchild Semiconductor Corporation FDMS8350L Rev.1.8 1000 Figure 12. Single Pulse Maximum Power Dissipation 4 www.fairchildsemi.com FDMS8350L N-Channel PowerTrench® MOSFET Typical Characteristics TJ = 25 °C unless otherwise noted r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 2 1 0.1 0.01 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 NOTES: SINGLE PULSE 0.001 -5 10 ZθJC(t) = r(t) x RθJC RθJC = 1.1 oC/W Peak TJ = PDM x ZθJC(t) + TC Duty Cycle, D = t1 / t2 -4 10 -3 -2 10 10 -1 10 1 t, RECTANGULAR PULSE DURATION (sec) Figure 13. Junction-to-Case Transient Thermal Response Curve ©2014 Fairchild Semiconductor Corporation FDMS8350L Rev.1.8 5 www.fairchildsemi.com FDMS8350L N-Channel PowerTrench® MOSFET Typical Characteristics TJ = 25 °C unless otherwise noted 5.10 4.90 A 3.81 PKG CL 8 4.42 B 5 8 7 6 5 1.14 KEEP OUT AREA 3.65 6.25 5.90 PKG CL 6.61 4.79 1.27 1 PIN #1 IDICATOR 4 TOP VIEW 1 2 3 4 1.27 SEE DETAIL A 0.61 3.81 5.10 LAND PATTERN RECOMMENDATION SIDE VIEW 3.81 0.10 1.27 (0.38) 1 C A B 0.47 (8X) 0.37 4 (0.35) 0.65 0.55 PIN #1 INDICATOR 4.66 4.46 8 5 4.33 4.13 0.70 BOTTOM VIEW 0.10 C 1.10 0.90 0.08 C C 0.25 0.15 SCALE: 2:1 0.05 0.00 SEATING PLANE NOTES: UNLESS OTHERWISE SPECIFIED A) PACKAGE STANDARD REFERENCE: JEDEC MO-240, ISSUE A, VAR. AA, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH. MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM. D) DIMENSIONING AND TOLERANCING PER ASME Y14.5M-2009. E) IT IS RECOMMENDED TO HAVE NO TRACES OR VIAS WITHIN THE KEEP OUT AREA. F) DRAWING FILE NAME: PQFN08JREV3. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. 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