FDP8870-F085

FDP8870 e May 2008 FDP8870 tmM N-Channel PowerTrench® MOSFET 30V, 156A, 4.1mΩ General Description Features This N-Channel MOSFET has been designed specifically to improve the overall efficiency of DC/DC converters using either synchronous or conventional switching PWM controllers. It has been optimized for low gate charge, low rDS(ON) and fast switching speed. • rDS(ON) = 4.1mΩ, VGS = 10V, ID = 35A • rDS(ON) = 4.6mΩ, VGS = 4.5V, ID = 35A • High performance trench technology for extremely low rDS(ON) • Low gate charge Applications • High power and current handling capability • DC/DC converters • (FLANGE) DRAIN RoHS Compliant D SOURCE DRAIN G GATE S TO-220AB FDP SERIES MOSFET Maximum Ratings TC = 25°C unless otherwise noted Symbol VDSS Drain to Source Voltage Parameter Ratings 30 Units V VGS Gate to Source Voltage ±20 V Continuous (TC = 25oC, VGS = 10V) (Note 1) 156 A Continuous (TC = 25oC, VGS = 4.5V) (Note 1) 147 A Continuous (Tamb = 25oC, VGS = 10V, with RθJA = 62oC/W) 19 A Drain Current ID Pulsed EAS PD TJ, TSTG Single Pulse Avalanche Energy (Note 2) Figure 4 A 300 mJ Power dissipation 160 W Derate above 25oC 1.07 W/oC -55 to 175 oC Operating and Storage Temperature Thermal Characteristics RθJC Thermal Resistance Junction to Case TO-220 RθJA Thermal Resistance Junction to Ambient TO-220 ( Note 3) 0.94 o C/W 62 o C/W Package Marking and Ordering Information Device Marking FDP8870 ©2008 Fairchild Semiconductor Corporation Device FDP8870 Package TO-220AB Reel Size Tube Tape Width N/A Quantity 50 units FDP8870 Rev. A3 Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage IDSS Zero Gate Voltage Drain Current IGSS Gate to Source Leakage Current ID = 250µA, VGS = 0V VDS = 24V VGS = 0V TC = 150oC VGS = ±20V 30 - - V - - 1 - - 250 µA - - ±100 nA - 2.5 V On Characteristics VGS(TH) rDS(ON) Gate to Source Threshold Voltage Drain to Source On Resistance VGS = VDS, ID = 250µA 1.2 ID = 35A, VGS = 10V - 0.0034 0.0041 ID = 35A, VGS = 4.5V - 0.0040 0.0046 ID = 35A, VGS = 10V, TJ = 175oC - 0.0051 0.0065 Ω Dynamic Characteristics - 5200 - - 970 - pF pF - 570 - pF CISS Input Capacitance COSS Output Capacitance CRSS Reverse Transfer Capacitance RG Gate Resistance VGS = 0.5V, f = 1MHz - 2.1 - Ω Qg(TOT) Total Gate Charge at 10V VGS = 0V to 10V - 106 132 nC VDS = 15V, VGS = 0V, f = 1MHz Qg(5) Total Gate Charge at 5V VGS = 0V to 5V Qg(TH) Threshold Gate Charge VGS = 0V to 1V Qgs Gate to Source Gate Charge Qgs2 Gate Charge Threshold to Plateau Qgd Gate to Drain “Miller” Charge Switching Characteristics VDD = 15V ID = 35A Ig = 1.0mA - 56 69 nC - 5.0 6.5 nC - 15 - nC - 10 - nC - 23 - nC (VGS = 10V) tON Turn-On Time - - 168 ns td(ON) Turn-On Delay Time - 11 - ns ns tr Rise Time td(OFF) Turn-Off Delay Time tf tOFF - 105 - - 70 - ns Fall Time - 46 - ns Turn-Off Time - - 173 ns ISD = 35A - - 1.25 V ISD = 15A - - 1.0 V VDD = 15V, ID = 35A VGS = 4.5V, RGS = 3.3Ω Drain-Source Diode Characteristics VSD Source to Drain Diode Voltage trr Reverse Recovery Time ISD = 35A, dISD/dt = 100A/µs - - 37 ns QRR Reverse Recovered Charge ISD = 35A, dISD/dt = 100A/µs - - 21 nC Notes: 1: Package current limitation is 80A. 2: Starting TJ = 25°C, L = 0.15mH, IAS = 64A, VDD = 27V, VGS = 10V. 3: Pulse width = 100s. 4 ©2008 Fairchild Semiconductor Corporation FDP8870 Rev. A3 FDP8870 Electrical Characteristics TC = 25°C unless otherwise noted FDP8870 Typical Characteristics TC = 25°C unless otherwise noted 175 1.0 150 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.2 0.8 0.6 0.4 CURRENT LIMITED BY PACKAGE 125 100 75 50 0.2 25 0 0 25 50 75 100 150 125 0 175 25 50 75 TC , CASE TEMPERATURE (oC) 100 125 TC, CASE TEMPERATURE Figure 1. Normalized Power Dissipation vs Case Temperature 150 175 (oC) Figure 2. Maximum Continuous Drain Current vs Case Temperature 2 ZθJC, NORMALIZED THERMAL IMPEDANCE 1 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC x RθJC + TC SINGLE PULSE 0.01 10-5 10-4 10-3 10-2 10-1 100 101 t, RECTANGULAR PULSE DURATION (s) Figure 3. Normalized Maximum Transient Thermal Impedance 1000 TC = 25oC IDM, PEAK CURRENT (A) TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: VGS = 4.5V 175 - TC I = I25 150 100 50 10-5 10-4 10-3 10-2 10-1 100 101 t, PULSE WIDTH (s) Figure 4. Peak Current Capability ©2008 Fairchild Semiconductor Corporation FDP8870 Rev. A3 FDP8870 Typical Characteristics TC = 25°C unless otherwise noted 500 1000 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R ≠ 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] IAS, AVALANCHE CURRENT (A) ID, DRAIN CURRENT (A) 10µs 100 100µs 10 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1ms 10ms 1 SINGLE PULSE TJ = MAX RATED TC = 25oC DC 100 STARTING TJ = 25oC 10 STARTING TJ = 150oC 0.1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 1 0.01 60 0.1 1 10 tAV, TIME IN AVALANCHE (ms) NOTE: Refer to Fairchild Application Notes AN7514 and AN7515 Figure 5. Forward Bias Safe Operating Area Figure 6. Unclamped Inductive Switching Capability 160 160 VGS = 5V VGS = 4V ID, DRAIN CURRENT (A) ID , DRAIN CURRENT (A) PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDD = 15V 120 TJ = 175oC 80 TJ = 25oC 40 120 VGS = 10V VGS = 3V 80 40 TC = 25oC PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX TJ = -55oC 0 0 1.5 2.0 2.5 3.0 VGS , GATE TO SOURCE VOLTAGE (V) 0 3.5 0.25 0.5 0.75 1.0 VDS , DRAIN TO SOURCE VOLTAGE (V) Figure 7. Transfer Characteristics Figure 8. Saturation Characteristics 1.6 10 NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX ID = 35A rDS(ON), DRAIN TO SOURCE ON RESISTANCE (mΩ) 100 8 6 4 ID = 1A PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 1.4 1.2 1.0 0.8 VGS = 10V, ID = 35A 2 2 4 6 8 10 VGS, GATE TO SOURCE VOLTAGE (V) Figure 9. Drain to Source On Resistance vs Gate Voltage and Drain Current ©2008 Fairchild Semiconductor Corporation 0.6 -80 -40 0 40 80 120 TJ, JUNCTION TEMPERATURE (oC) 160 200 Figure 10. Normalized Drain to Source On Resistance vs Junction Temperature FDP8870 Rev. A3 FDP8870 Typical Characteristics TC = 25°C unless otherwise noted 1.2 1.4 ID = 250µA NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, ID = 250µA NORMALIZED GATE THRESHOLD VOLTAGE 1.2 1.0 0.8 0.6 0.4 -80 -40 0 40 80 120 160 1.1 1.0 0.9 -80 200 -40 Figure 11. Normalized Gate Threshold Voltage vs Junction Temperature 80 120 160 200 10 VDD = 15V CRSS = CGD VGS , GATE TO SOURCE VOLTAGE (V) CISS = CGS + CGD C, CAPACITANCE (pF) 40 Figure 12. Normalized Drain to Source Breakdown Voltage vs Junction Temperature 10000 COSS ≅ CDS + CGD 1000 VGS = 0V, f = 1MHz 400 0.1 0 TJ , JUNCTION TEMPERATURE (oC) TJ, JUNCTION TEMPERATURE (oC) 8 6 4 WAVEFORMS IN DESCENDING ORDER: ID = 35A ID = 5A 2 0 1 10 VDS , DRAIN TO SOURCE VOLTAGE (V) Figure 13. Capacitance vs Drain to Source Voltage ©2008 Fairchild Semiconductor Corporation 30 0 20 40 60 Qg, GATE CHARGE (nC) 80 100 Figure 14. Gate Charge Waveforms for Constant Gate Current FDP8870 Rev. A3 FDP8870 Test Circuits and Waveforms VDS BVDSS tP L VDS VARY tP TO OBTAIN IAS + RG REQUIRED PEAK IAS VDD VDD - VGS DUT tP IAS 0V 0 0.01Ω tAV Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms VDS VDD Qg(TOT) VDS L VGS VGS = 10V VGS Qg(5) + Qgs2 VDD VGS = 5V DUT VGS = 1V Ig(REF) 0 Qg(TH) Qgs Qgd Ig(REF) 0 Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms VDS tON tOFF td(ON) td(OFF) RL tr VDS tf 90% 90% + VGS VDD - 10% 10% 0 DUT 90% RGS VGS VGS 0 Figure 19. Switching Time Test Circuit ©2008 Fairchild Semiconductor Corporation 50% 10% 50% PULSE WIDTH Figure 20. Switching Time Waveforms FDP8870 Rev. A3 .SUBCKT FDP8870 2 1 3 ; rev December 2003 Ca 12 8 4.5e-9 Cb 15 14 4.5e-9 Cin 6 8 4.7e-9 LDRAIN DPLCAP DRAIN 2 5 10 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD 5 51 ESLC EVTHRES + 19 8 + LGATE GATE 1 11 + 17 EBREAK 18 - 50 RDRAIN 6 8 ESG DBREAK + RSLC2 Ebreak 11 7 17 18 33.45 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1 It 8 17 1 RLDRAIN RSLC1 51 EVTEMP RGATE + 18 22 9 20 21 16 DBODY MWEAK 6 MMED MSTRO RLGATE Lgate 1 9 3.6e-9 Ldrain 2 5 1.0e-9 Lsource 3 7 3.3e-9 LSOURCE CIN 8 7 SOURCE 3 RSOURCE RLSOURCE RLgate 1 9 36 RLdrain 2 5 10 RLsource 3 7 33 Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD S1A 12 S2A 13 8 17 18 RVTEMP S2B 13 CB 19 6 8 VBAT 5 8 EDS - IT 14 + + EGS Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 2.15e-3 Rgate 9 20 2.1 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 Rsource 8 7 RsourceMOD 9e-4 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD 15 14 13 S1B CA RBREAK - + 8 22 RVTHRES Vbat 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*500),10))} .MODEL DbodyMOD D (IS=7.5E-12 IKF=17 N=1.01 RS=2.1e-3 TRS1=2e-3 TRS2=2e-7 + CJO=1.9e-9 M=0.57 TT=9e-11 XTI=2.6) .MODEL DbreakMOD D (RS=8e-2 TRS1=1e-3 TRS2=-8.9e-6) .MODEL DplcapMOD D (CJO=1.75e-9 IS=1e-30 N=10 M=0.4) .MODEL MmedMOD NMOS (VTO=2.1 KP=30 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2.1 T_ABS=25) .MODEL MstroMOD NMOS (VTO=2.51 KP=650 IS=1e-30 N=10 TOX=1 L=1u W=1u T_ABS=25) .MODEL MweakMOD NMOS (VTO=1.67 KP=0.1 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=21 RS=0.1 T_ABS=25) .MODEL RbreakMOD RES (TC1=8.3e-4 TC2=-9e-7) .MODEL RdrainMOD RES (TC1=2.3e-3 TC2=5e-6) .MODEL RSLCMOD RES (TC1=1e-4 TC2=1e-6) .MODEL RsourceMOD RES (TC1=8e-3 TC2=1e-6) .MODEL RvthresMOD RES (TC1=-2.3e-3 TC2=-9e-6) .MODEL RvtempMOD RES (TC1=-3e-3 TC2=2e-7) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-2) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2 VOFF=-4) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1 VOFF=-0.5) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.5 VOFF=-1) .ENDS Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. ©2008 Fairchild Semiconductor Corporation FDP8870 Rev. A3 FDP8870 PSPICE Electrical Model FDP8870 SABER Electrical Model rev December 2003 template FDP8870 n2,n1,n3 =m_temp electrical n2,n1,n3 number m_temp=25 { var i iscl dp..model dbodymod = (isl=7.5e-12,ikf=17,nl=1.01,rs=2.1e-3,trs1=2e-3,trs2=2e-7,cjo=1.9e-9,m=0.57,tt=9e-11,xti=2.6) dp..model dbreakmod = (rs=8e-2,trs1=1e-3,trs2=-8.9e-6) dp..model dplcapmod = (cjo=1.75e-9,isl=10e-30,nl=10,m=0.4) m..model mmedmod = (type=_n,vto=2.1,kp=30,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=2.51,kp=650,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=1.67,kp=0.1,is=1e-30, tox=1,rs=0.1) LDRAIN sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4,voff=-2) DPLCAP 5 sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-2,voff=-4) 10 sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-1,voff=-0.5) RLDRAIN RSLC1 sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=-0.5,voff=-1) 51 c.ca n12 n8 = 4.5e-9 RSLC2 c.cb n15 n14 = 4.5e-9 ISCL c.cin n6 n8 = 4.7e-9 spe.ebreak n11 n7 n17 n18 = 33.45 GATE spe.eds n14 n8 n5 n8 = 1 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evthres n6 n21 n19 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 RDRAIN 6 8 ESG EVTHRES + 19 8 + LGATE DBREAK 50 - dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod EVTEMP RGATE + 18 22 9 20 21 11 DBODY 16 MWEAK 6 EBREAK + 17 18 - MMED MSTRO RLGATE CIN DRAIN 2 8 LSOURCE 7 SOURCE 3 RSOURCE RLSOURCE i.it n8 n17 = 1 S1A 12 l.lgate n1 n9 = 3.6e-9 l.ldrain n2 n5 = 1.0e-9 l.lsource n3 n7 = 3.3e-9 14 13 13 8 S1B CA res.rlgate n1 n9 = 36 res.rldrain n2 n5 = 10 res.rlsource n3 n7 = 33 S2A RBREAK 15 17 18 RVTEMP S2B 13 CB 6 8 EGS 19 - IT 14 + + VBAT 5 8 EDS - m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u, temp=m_temp m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u, temp=m_temp m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u, temp=m_temp + 8 22 RVTHRES res.rbreak n17 n18 = 1, tc1=8.3e-4,tc2=-9e-7 res.rdrain n50 n16 = 2.15e-3, tc1=2.3e-3,tc2=5e-6 res.rgate n9 n20 = 2.1 res.rslc1 n5 n51 = 1e-6, tc1=1e-4,tc2=1e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 9e-4, tc1=8e-3,tc2=1e-6 res.rvthres n22 n8 = 1, tc1=-2.3e-3,tc2=-9e-6 res.rvtemp n18 n19 = 1, tc1=-3e-3,tc2=2e-7 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/500))** 10)) } } ©2008 Fairchild Semiconductor Corporation FDP8870 Rev. A3 th FDP8870 PSPICE Thermal Model JUNCTION REV 23 December 2003 FDP8870T CTHERM1 TH 6 1e-3 CTHERM2 6 5 2e-3 CTHERM3 5 4 3e-3 CTHERM4 4 3 9e-3 CTHERM5 3 2 1e-2 CTHERM6 2 TL 2e-2 RTHERM1 CTHERM1 6 RTHERM1 TH 6 3e-2 RTHERM2 6 5 8e-2 RTHERM3 5 4 1.1e-1 RTHERM4 4 3 1.6e-1 RTHERM5 3 2 1.72e-1 RTHERM6 2 TL 2e-1 RTHERM2 CTHERM2 5 SABER Thermal Model SABER thermal model FDP8870T template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 =1e-3 ctherm.ctherm2 6 5 =2e-3 ctherm.ctherm3 5 4 =3e-3 ctherm.ctherm4 4 3 =9e-3 ctherm.ctherm5 3 2 =1e-2 ctherm.ctherm6 2 tl =2e-2 rtherm.rtherm1 th 6 =3e-2 rtherm.rtherm2 6 5 =8e-2 rtherm.rtherm3 5 4 =1.1e-1 rtherm.rtherm4 4 3 =1.6e-1 rtherm.rtherm5 3 2 =1.72e-1 rtherm.rtherm6 2 tl =2e-1 } RTHERM3 CTHERM3 4 RTHERM4 CTHERM4 3 RTHERM5 CTHERM5 2 CTHERM6 RTHERM6 tl ©2008 Fairchild Semiconductor Corporation CASE FDP8870 Rev. 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Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. Obsolete Not In Production This datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only. Rev. I34 @2008 Fairchild Semiconductor Corporation FDP8870 Rev. A3