MC100EP140DR2G

DATA SHEET www.onsemi.com 3.3V ECL Phase-Frequency Detector MC100EP140 MARKING DIAGRAM 8 8 1 Description The MC100EP140 is a three state phase frequency−detector intended for phase−locked loop applications which require a minimum amount of phase and frequency difference at lock. Since the part is designed with fully differential internal gates, the noise is reduced throughout the circuit, especially at high speeds. The basic operation of a Phase/Frequency Detector (PFD) is to “compare” an incoming signal (feedback) to a set reference signal. When the Reference (R) and Feedback (FB) inputs are unequal in frequency and/or phase, the differential UP (U) and DOWN (D) outputs will provide pulse streams which, when subtracted and integrated, provide an error voltage for control of a VCO. Detector states of operation are shown in the Figure 2 and the State Table. The typical output amplitude of the EP140 is 400 mV, allowing faster switching time and greater bandwidth. For proper operation, the input edge rate of the R and FB inputs should be less than 5 ns. More information on Phase Lock Loop operation and application can be found in AND8040. The pinout is shown in Figure 1, the logic diagram in Figure 3, and the typical termination in Figure 5. A L Y W G SOIC−8 D SUFFIX CASE 751 1 KP140 ALYW G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. Features • • • • • • • • • • • 500 ps Typical Propagation Delay Maximum Frequency > 2.1 GHz Typical Fully Differential Internally Advanced High Band Output Swing of 400 mV Transfer Gain: 1.0 mV/Degree at 1.4 GHz 1.2 mV/Degree at 1.0 GHz Rise and Fall Time: 100 ps Typical The 100 Series Contains Temperature Compensation PECL Mode Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −3.6 V Open Input Default State These are Pb−Free Devices © Semiconductor Components Industries, LLC, 2006 September, 2022 − Rev. 10 1 Publication Order Number: MC100EP140/D MC100EP140 VCC R FB VEE 8 7 6 5 1 2 3 4 U U D D Table 1. PIN DESCRIPTION PIN FUNCTION D, D Differential Down Outputs U, U Differential Up Outputs R* ECL Reference Input FB* ECL Feedback Input VCC Positive Supply VEE Negative Supply * Pins will default LOW when left open. Figure 1. 8−Lead Pinout (Top View) Table 2. STATE TABLE R 1 FB R Pump Down U=L D=H PHASE DETECTOR STATE 2 3 Pump Up U=L D=L FB U=H D=L U C A A A U D L L L L 2−1 L H L H 1−2 H L L L 2 L L L L 2 L L L L 2−3 H L H L 3−2 H H L L 2 L L L L U U C S Reset FB PUMP UP 2−3−2 FB Figure 2. Phase Detector Logic Model R R U FF C A Reset D VEE B Reset FB D R B S D FF OUTPUT R PUMP DOWN 2−1−2 2 R INPUT D Reset B D B Figure 3. Logic Diagram www.onsemi.com 2 D D MC100EP140 Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 kW Internal Input Pullup Resistor 37.5 kW ESD Protection Human Body Model Machine Model Charged Device Model > 2 kV > 200 V > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) SOIC−8 Flammability Rating Oxygen Index: 28 to 34 Pb Pkg Pb−Free Pkg Level 1 Level 1 UL 94 V−0 @ 0.125 in Transistor Count 457 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Table 4. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit VCC PECL Mode Power Supply VEE = 0 V 6 V VEE NECL Mode Power Supply VCC = 0 V −6 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 −6 V V Iout Output Current Continuous Surge 50 100 mA mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm SOIC−8 SOIC−8 190 130 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board SOIC−8 41 to 44 °C/W Tsol Wave Solder 265 265 °C VI v VCC VI w VEE Pb Pb−Free Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Table 5. 100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 2) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 45 65 85 50 70 90 53 73 93 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 3) 2255 2350 2475 2275 2400 2525 2300 2425 2550 mV VOL Output LOW Voltage (Note 3) 1755 1900 2025 1800 1925 2050 1825 1950 2075 mV VIH Input HIGH Voltage (Single−Ended) 2075 2420 2075 2420 2075 2420 mV VIL Input LOW Voltage (Single−Ended) 1355 1675 1355 1675 1355 1675 mV IIH Input HIGH Current 150 mA IIL Input LOW Current 150 0.5 150 0.5 0.5 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 2. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −0.3 V. 3. All loading with 50 W to VCC − 2.0 V. www.onsemi.com 3 MC100EP140 Table 6. 100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = −3.6 V to −3.0 V (Note 4) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 45 65 85 50 70 90 53 73 93 mA Output HIGH Voltage (Note 5) −1075 −950 −825 −1025 −900 −775 −1000 −875 −750 mV VOL Output LOW Voltage (Note 5) −1525 −1400 −1275 −1500 −1375 −1250 −1475 −1350 −1225 mV VIH Input HIGH Voltage (Single−Ended) −1225 −880 −1225 −880 −1225 −880 mV VIL Input LOW Voltage (Single−Ended) −1945 −1625 −1945 −1625 −1945 −1625 mV IIH Input HIGH Current 150 mA IIL Input LOW Current IEE Power Supply Current VOH 150 150 0.5 0.5 0.5 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 4. Input and output parameters vary 1:1 with VCC. 5. All loading with 50 W to VCC − 2.0 V. Table 7. AC CHARACTERISTICS VCC = 0 V; VEE = −3.0 V to −3.6 V or VCC = 3.0 V to 3.6 V; VEE = 0 V (Note 6) −40°C Symbol Characteristic fmax Maximum Frequency (Figure 4) tPLH, tPHL Propagation Delay to Output Differential tJITTER Cycle−to−Cycle Jitter (Figure 4) VPP Input Voltage Swing tr tf Output Rise/Fall Times (20% − 80%) Min Typ 25°C Max Min >2 R to U, FB to D FB to U, R to D 300 400 Q, Q Typ 85°C Max Min >2 450 600 6002 800 .2 2 475 650 625 850 .2