3.3 V ECL Programmable
Delay Chip
MC100EP195B
Descriptions
The MC100EP195B is a Programmable Delay Chip (PDC)
designed primarily for clock deskewing and timing adjustment. It
provides variable delay of a differential NECL/PECL input transition.
The delay section consists of a programmable matrix of gates and
multiplexers as shown in the logic diagram, Figure 2. The delay
increment of the EP195B has a digitally selectable resolution of about
10 ps and a net range of up to 10.2 ns. The required delay is selected by
the 10 data select inputs D[9:0] values and controlled by the LEN
(pin 10). A LOW level on LEN allows a transparent LOAD mode of
real time delay values by D[9:0]. A LOW to HIGH transition on LEN
will LOCK and HOLD current values present against any subsequent
changes in D[10:0]. The approximate delay values for varying tap
numbers correlating to D0 (LSB) through D9 (MSB) are shown in
Table 6 and Figure 3.
The IN/IN inputs can accept LVPECL (SE of Diff), or LVDS level
signals. Because the EP195B is designed using a chain of multiplexers
it has a fixed minimum delay of 2.2 ns. An additional pin D10 is
provided for controlling Pins 14 and 15, CASCADE and CASCADE,
also latched by LEN, in cascading multiple PDCs for increased
programmable range. The cascade logic allows full control of multiple
PDCs. Switching devices from all “1” states on D[0:9] with SETMAX
LOW to all “0” states on D[0:9] with SETMAX HIGH will increase
the delay equivalent to “D0”, the minimum increment.
Select input pins D[10:0] may be threshold controlled by
combinations of interconnects between VEF (pin 7) and VCF (pin 8)
for LVCMOS, ECL, or LVTTL level signals. For LVCMOS input
levels, leave VCF and VEF open. For ECL operation, short VCF and
VEF (Pins 7 and 8). For LVTTL level operation, connect a 1.5 V
supply reference to VCF and leave open VEF pin. The 1.5 V reference
voltage to VCF pin can be accomplished by placing a 2.2 kW resistor
between VCF and VEE for a 3.3 V power supply.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single−ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
The 100 Series contains temperature compensation.
Features
•
•
•
•
•
•
March, 2021 − Rev. 3
MARKING
DIAGRAMS*
MC100
EP195B
AWLYYWWG
LQFP−32
FA SUFFIX
CASE 561AB
32
1
1
1
MC100
EP195B
ALYWG
G
32
QFN32
MN SUFFIX
CASE 488AM
A
WL, L
Y, YY
W, WW
G or G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
Device
Package
Shipping
MC100EP195BFAG
LQFP−32
(Pb−Free)
250 Units /
Tray
MC100EP195BMNG
QFN32
(Pb−Free)
74 Units /
Rail
• IN/IN Inputs Accept LVPECL, LVNECL, LVDS Levels
• A Logic High on the EN Pin Will Force Q to Logic Low
• D[10:0] Can Select Either LVPECL, LVCMOS, or
Maximum Input Clock Frequency >1.2 GHz Typical
Programmable Range: 0 ns to 10 ns
Delay Range: 2.2 ns to 12.2 ns
10 ps Increments
PECL Mode Operating Range:
VCC = 3.0 V to 3.6 V with VEE = 0 V
NECL Mode Operating Range:
VCC = 0 V with VEE = −3.0 V to −3.6 V
© Semiconductor Components Industries, LLC, 2014
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•
•
1
LVTTL Input Levels
VBB Output Reference Voltage
These are Pb−Free Devices
Publication Order Number:
MC100EP195B/D
MC100EP195B
D3
27
25
24
D9
2
23
D0
D10
3
22
VCC
IN
4
21
Q
20
Q
19
VCC
18
VCC
17
NC
5
VBB
6
VEF
7
VCF
8
26
D1
VEE
28
D2
D4
29
1
IN
31
D5
D6
D7
32
30
D8
MC100EP195B
11
12
13
14
VEE
LEN
SETMIN
SETMAX
VCC
CASCADE
15
16
EN
10
CASCADE
9
VEE
Figure 1. 32−Lead LQFP Pinout (Top View)
D5
D4
VEE
D3
30
29
28
27
26
D1
D6
31
D2
D7
32
25
D8
1
24
VEE
D9
2
23
D0
D10
3
22
VCC
IN
4
21
Q
IN
5
20
Q
VBB
6
19
VCC
VEF
7
18
VCC
VCF
8
17
NC
MC100EP195B
11
12
13
14
15
16
SETMIN
SETMAX
VCC
CASCADE
CASCADE
EN
VEE
10
LEN
9
Figure 1. 32−Lead QFN (Top View)
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2
Exposed Pad (EP)
MC100EP195B
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Default State
Description
23, 25, 26, 27,
29, 30, 31, 32,
1, 2
D[0:9]
LVCMOS, LVTTL,
ECL Input
Low
Single−Ended Parallel Data Inputs [0:9]. Internal 75 kW to VEE.
(Note 1)
3
D[10]
LVCMOS, LVTTL,
ECL Input
Low
Single−Ended CASCADE/CASCADE Control Input. Internal 75 kW
to VEE. (Note 1)
4
IN
LVPECL, LVDS
Low
Noninverted Differential Input. Internal 75 kW to VEE.
5
IN
LVPECL, LVDS
High
Inverted Differential Input. Internal 75 kW to VEE and 36.5 kW to
VCC.
6
VBB
−
−
ECL Reference Voltage Output
7
VEF
−
−
Reference Voltage for ECL Mode Connection
8
VCF
−
−
LVCMOS, ECL, OR LVTTL Input Mode Select
9, 24, 28
VEE
−
−
Negative Supply Voltage. All VEE Pins must be Externally
Connected to Power Supply to Guarantee Proper Operation.
(Note 2)
13, 18, 19, 22
VCC
−
−
Positive Supply Voltage. All VCC Pins must be externally
Connected to Power Supply to Guarantee Proper Operation.
(Note 2)
10
LEN
ECL Input
Low
Single−ended D pins LOAD / HOLD input. Internal 75 kW to VEE.
11
SETMIN
ECL Input
Low
Single−ended Minimum Delay Set Logic Input. Internal 75 kW to
VEE. (Note 1)
12
SETMAX
ECL Input
Low
Single−ended Maximum Delay Set Logic Input. Internal 75 kW to
VEE. (Note 1)
14
CASCADE
ECL Output
−
Inverted Differential Cascade Output for D[10]. Typically Terminated
with 50 W to VTT = VCC − 2 V.
15
CASCADE
ECL Output
−
Noninverted Differential Cascade Output. for D[10] Typically
Terminated with 50 W to VTT = VCC − 2 V.
16
EN
ECL Input
Low
17
NC
−
−
No Connect. The NC Pin is Electrically Connected to the Die and
”MUST BE” Left Open
21
Q
ECL Output
−
Noninverted Differential Output. Typically Terminated with 50 W to
VTT = VCC − 2 V.
20
Q
ECL Output
−
Inverted Differential Output. Typically Terminated with 50 W to
VTT = VCC − 2 V.
Single−ended Output Enable Pin. Internal 75 kW to VEE.
1. SETMIN will override SETMAX if both are high. SETMAX and SETMIN will override all D[0:10] inputs.
2. All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation.
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MC100EP195B
Table 2. CONTROL PIN
Pin
State
EN
LOW (Note 3)
Function
HIGH
LEN
Output Holds Logic Low State
LOW (Note 3)
HIGH
SETMIN
SETMAX
D10
Input Signal is Propagated to the Output
Transparent or LOAD mode for real time delay values present on D[0:10].
LOCK and HOLD mode for delay values on D[0:10]; further changes on D[0:10]
are not recognized and do not affect delay.
LOW (Note 3)
Output Delay set by D[0:10]
HIGH
Set Minimum Output Delay
LOW (Note 3)
Output Delay set by D[0:10]
HIGH
Set Maximum Output Delay
LOW (Note 3)
CASCADE Output LOW, CASCADE Output HIGH
HIGH
CASCADE Output LOW, CASCADE Output HIGH
3. Internal pulldown resistor will provide a logic LOW if pin is left unconnected.
Table 3. CONTROL D[0:10] INTERFACE
VCF
VEF Pin (Note 4)
VCF
No Connect
VCF
1.5 V ±100 mV
ECL Mode
LVCMOS Mode
LVTTL Mode (Note 5)
4. Short VCF (pin 8) and VEF (pin 7).
5. When Operating in LVTTL Mode, the reference voltage can be provided by connecting an external resistor, RCF (suggested resistor value
is 2.2 kW $5%), between VCF and VEE pins.
Table 4. DATA INPUT ALLOWED OPERATING VOLTAGE MODE TABLE
CONTROL DATA SELECT INPUTS PINS (D [0:10])
LVCMOS
LVTTL
LVPECL
LVNECL
PECL Mode Operating Range
YES
YES
YES
N/A
NECL Mode Operating Range
N/A
N/A
N/A
YES
POWER SUPPLY
Table 5. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor (R1)
75 kW
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 100 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 6)
Pb−Free Pkg
QFN−32
LQFP−32
Level 1
Level 2
Flammability Rating Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Transistor Count
1217 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
6. For additional information, see Application Note AND8003/D.
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5
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Figure 2. Logic Diagram
VEE
VEF
VCF
VBB
EN
IN
IN
R1
LEN
R1
SET MAX
SET MIN
R1
R1
R1
512
GD*
D9
R1
1
0
D10
Latch
R1
1
D8
R1
256
GD*
0
D7
1
CASCADE
CASCADE
R1
128
GD*
0
R1
64
GD*
D6
1
0
16
GD*
1
R1
D4
10 BIT LATCH
D5
1
0
R1
8
GD*
D3
1
0
R1
4
GD*
D2
1
0
R1
2
GD*
D1
1
0
*GD = (GATE DELAY) APPROXIMATELY 10 ps DELAY PER GATE
(MINIMUM FIXED DELAY APPROX. 2.2 ns)
R1
32
GD*
0
D0
R1
1
GD*
R1
1
0
1
GD*
1
0
Q
Q
MC100EP195B
MC100EP195B
Table 6. THEORETICAL DELAY VALUES
D(9:0) Value
SETMIN
SETMAX
Programmable Delay*
XXXXXXXXXX
H
L
0 ps
0000000000
L
L
0 ps
0000000001
L
L
10 ps
0000000010
L
L
20 ps
0000000011
L
L
30 ps
0000000100
L
L
40 ps
0000000101
L
L
50 ps
0000000110
L
L
60 ps
0000000111
L
L
70 ps
0000001000
L
L
80 ps
0000010000
L
L
160 ps
0000100000
L
L
320 ps
0001000000
L
L
640 ps
0010000000
L
L
1280 ps
0100000000
L
L
2560 ps
1000000000
L
L
5120 ps
1111111111
L
L
10230 ps
XXXXXXXXXX
L
H
10240 ps
*Fixed minimum delay not included.
14000
13000
85°C
12000
11000
25°C
−40°C
DELAY ( ps)
10000
9000
VCC = 0 V
8000
VEE = −3.3 V
7000
6000
5000
4000
3000
2000
1000
0
0
100
200
300
400
500
600
700
800
Decimal Value of Select Inputs (D[9:0])
Figure 3. Measured Delay vs. Select Inputs
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900
1000
MC100EP195B
Table 7. MAXIMUM RATINGS
Symbol
Rating
Unit
VCC
Positive Mode Power Supply
Parameter
VEE = 0 V
Condition 1
Condition 2
6
V
VEE
Negative Mode Power Supply
VCC = 0 V
−6
V
VI
Positive Mode Input Voltage
Negative Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
−6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
IBB
VBB Sink/Source
±0.5
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
QFN−32
QFN−32
31
27
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
2S2P Standard Board
QFN−32
12
°C/W
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
LQFP−32
LQFP−32
80
55
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
2S2P Standard Board
LQFP−32
12 to 17
°C/W
Tsol
Wave Solder
3.3 V, 5 W to 10 W in line with VEE required for maximum thermal
protection at elevated temperatures. Recommend VCC − VEE operation at ≤ 3.8 V.
12. All loading with 50 W to VCC − 2.0 V.
13. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
Table 10. AC CHARACTERISTICS (VCC = 0 V; VEE = −3.0 V to −3.6 V or VCC = 3.0 V to 3.6 V; VEE = 0 V) (Note 14)
−40°C
Symbol
fmax
VoutPP
tPLH
tPHL
tRANGE
Characteristic
Min
Maximum Frequency
Output Voltage Amplitude
Propagation Delay
IN to Q; D(0−10) = 0, SETMIN
IN to Q; D(0−10) = 1023, SETMAX
EN to Q; D(0−10) = 0
D0 to CASCADE
Programmable Range
tPD (max) − tPD (min)
Typ
25°C
Max
Min
1.2
Typ
85°C
Max
Min
1.2
610
820
2000
10900
1990
375
2400
12400
2500
475
8950
9950
Typ
Max
Unit
1.2
GHz
610
820
mV
610
820
2800
13900
2990
575
2150
11500
2130
400
2500
13000
2600
500
2950
14500
3130
600
2250
12250
2380
425
2700
13750
2800
525
3050
15250
3380
625
10950
9450
10450
11450
10110
11100
12110
ps
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
14. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V.
15. Specification limits represent the amount of delay added with the assertion of each individual delay control pin. The various combinations
of asserted delay control inputs will typically realize D0 resolution steps across the specified programmable range.
16. Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the cross point of the output.
17. This setup time defines the amount of time prior to the input signal the delay tap of the device must be set.
18. This setup time is the minimum time that EN must be asserted prior to the next transition of IN/IN to prevent an output response greater
than ±75 mV to that IN/IN transition.
19. This hold time is the minimum time that EN must remain asserted after a negative going IN or positive going IN to prevent an output response greater than ±75 mV to that IN/IN transition.
20. This release time is the minimum time that EN must be deasserted prior to the next IN/IN transition to ensure an output response that meets
the specified IN to Q propagation delay and transition times.
21. Deviation from a linear delay (actual Min to Max) in the 1024 programmable steps.
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MC100EP195B
Table 10. AC CHARACTERISTICS (VCC = 0 V; VEE = −3.0 V to −3.6 V or VCC = 3.0 V to 3.6 V; VEE = 0 V) (Note 14) (continued)
−40°C
Symbol
Dt
NLIN
tSKEW
Characteristic
Min
Step Delay (Note 15)
D0 High
D1 High
D2 High
D3 High
D4 High
D5 High
D6 High
D7 High
D8 High
D9 High
Typ
25°C
Max
Min
10
16
32
65
155
310
620
1200
2500
4900
Non−Linearity (Note 21)
0 to 511 Decimal Values for
D[9:0] Range
512 to 1024 Decimal Values for
D[9:0] Range
1 to 1023 Decimal Values for
D[9:0] Range
Typ
85°C
Max
Min
Typ
11
18
33
72
165
325
650
1300
2600
5200
15
26
46
92
195
370
720
1400
2800
5500
$7.0
$7.0
$11
$7.0
$7.0
$11
$11
$11
$18
25
90
25
90
25
ts
Setup Time
D to LEN
D to IN (Note 17)
EN to IN (Note 18)
200
500
300
−40
−550
100
200
500
300
−40
−590
100
200
500
300
−40
−650
120
th
Hold Time
LEN to D
IN to EN (Note 19)
200
400
50
−320
200
400
40
−350
200
400
30
−400
tR
Release Time
EN to IN (Note 20)
SET MAX to LEN
SET MIN to LEN
300
400
350
−150
180
220
300
400
350
−170
200
250
300
400
350
−200
210
260
RMS Random Clock Jitter @ 1.2 GHz
IN to Q; D(0:10) = 0 or SETMIN
IN to Q; D(0:10) = 1023 or SETMAX
VPP
Input Voltage Swing
(Differential Configuration)
tr
tf
Output Rise/Fall Time @ 50 MHz
20−80% (Q)
20−80% (CASCADE)
Unit
ps
ps
Duty Cycle Skew (Note 16)
|tPHL−tPLH|
tjitter
Max
0.9
1.9
2.0
5.0
150
800
1200
85
110
115
160
140
210
1.1
2.6
2.0
5.0
150
800
1200
100
120
120
175
140
230
90
ps
ps
ps
ps
1.2
3.3
2.0
5.0
150
800
1200
100
120
130
190
165
250
ps
mV
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
14. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V.
15. Specification limits represent the amount of delay added with the assertion of each individual delay control pin. The various combinations
of asserted delay control inputs will typically realize D0 resolution steps across the specified programmable range.
16. Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the cross point of the output.
17. This setup time defines the amount of time prior to the input signal the delay tap of the device must be set.
18. This setup time is the minimum time that EN must be asserted prior to the next transition of IN/IN to prevent an output response greater
than ±75 mV to that IN/IN transition.
19. This hold time is the minimum time that EN must remain asserted after a negative going IN or positive going IN to prevent an output response greater than ±75 mV to that IN/IN transition.
20. This release time is the minimum time that EN must be deasserted prior to the next IN/IN transition to ensure an output response that meets
the specified IN to Q propagation delay and transition times.
21. Deviation from a linear delay (actual Min to Max) in the 1024 programmable steps.
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MC100EP195B
IN
VINPP = VIH(D) − VIL(D)
IN
Q
VOUTPP = VOH(Q) − VOL(Q)
Q
tPHL
tPLH
Figure 4. AC Reference Measurement
Cascading Multiple EP195Bs
To increase the programmable range of the EP195B,
internal cascade circuitry has been included. This circuitry
allows for the cascading of multiple EP195Bs without the
need for any external gating. Furthermore, this capability
requires only one more address line per added E195B.
Obviously, cascading multiple programmable delay chips
will result in a larger programmable range: however, this
increase is at the expense of a longer minimum delay.
Figure 5 illustrates the interconnect scheme for cascading
two EP195Bs. As can be seen, this scheme can easily be
expanded for larger EP195B chains. The D10 input of the
EP195B is the CASCADE control pin. With the
interconnect scheme of Figure 5 when D10 is asserted, it
signals the need for a larger programmable range than is
achievable with a single device and switches output pin
CASCADE HIGH and pin CASCADE LOW. The A11
address can be added to generate a cascade output for the
next EP195B. For a 2−device configuration, A11 is not
required.
Need if Chip #3 is used
ADDRESS BUS
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
D7
D6
D5
D4
VEE
D3
D2
D7
D6
D5
D4
VEE
D3
D2
D1
VEE
D8
VEE
D9
D0
D9
D0
VCC
D10
Q
Q
VCC
VEF
NC
VCF
CHIP #1
OUTPUT
VCC
VCC
NC
EN
VBB
CASCADE
VCC
CASCADE
IN
VCC
CASCADE
CASCADE
VCC
SETMAX
LEN
VEE
VCF
SETMIN
VEF
Q
EN
CHIP #2
VBB
IN
SETMAX
IN
Q
SETMIN
IN
VCC
EP195B
LEN
EP195B
VEE
D10
INPUT
D1
D8
Figure 5. Cascading Interconnect Architecture
chip #2 will be reset and the device will be set at its minimum
delay.
Chip #1, on the other hand, will have both SET MIN and
SET MAX deasserted so that its delay will be controlled
entirely by the address bus A0—A9. If the delay needed is
greater than can be achieved with 1023 gate delays
(1111111111 on the A0—A9 address bus) D10 will be
An expansion of the latch section of the block diagram is
pictured in Figure 6. Use of this diagram will simplify the
explanation of how the cascade circuitry works. When D10
of chip #1 in Figure 5 is LOW this device’s
CASCADE output will also be low while the CASCADE
output will be high. In this condition the SET MIN pin of
chip #2 will be asserted HIGH and thus all of the latches of
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10
MC100EP195B
asserted to signal the need to cascade the delay to the next
EP195B device. When D10 is asserted, the SET MIN pin of
chip #2 will be deasserted and SET MAX pin asserted
resulting in the device delay to be the maximum delay.
Table 11 shows the delay time of two EP195B chips in
cascade.
To expand this cascading scheme to more devices, one
simply needs to connect the D10 pin from the next chip to
the address bus and CASCADE outputs to the next chip in
the same manner as pictured in Figure 5. The only addition
to the logic is the increase of one line to the address bus for
cascade control of the second programmable delay chip.
TO SELECT MULTIPLEXERS
SET
MIN
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
D0 Q0
D1 Q1
D2 Q2
D3 Q3
D4 Q4
D5 Q5
D6 Q6
D7 Q7
D8 Q8
D9 Q9
LEN
LEN
LEN
LEN
LEN
LEN
LEN
LEN
LEN
LEN
Set Reset
Set Reset
Set Reset
Set Reset
Set Reset
Set Reset
Set Reset
Set Reset
Set Reset
Set Reset
SET
MAX
Figure 6. Expansion of the Latch Section of the EP195B Block Diagram
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11
MC100EP195B
Table 11. Delay Value of Two EP195B Cascaded
VARIABLE INPUT TO CHIP #1 AND SETMIN FOR CHIP #2
INPUT FOR CHIP #1
Total
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Delay Value
Delay Value
0
0
0
0
0
0
0
0
0
0
0
0 ps
4400 ps
0
0
0
0
0
0
0
0
0
0
1
10 ps
4410 ps
0
0
0
0
0
0
0
0
0
1
0
20 ps
4420 ps
0
0
0
0
0
0
0
0
0
1
1
30 ps
4430 ps
0
0
0
0
0
0
0
0
1
0
0
40 ps
4440 ps
0
0
0
0
0
0
0
0
1
0
1
50 ps
4450 ps
0
0
0
0
0
0
0
0
1
1
0
60 ps
4460 ps
0
0
0
0
0
0
0
0
1
1
1
70 ps
4470 ps
0
0
0
0
0
0
0
1
0
0
0
80 ps
4480 ps
0
0
0
0
0
0
1
0
0
0
0
160 ps
4560 ps
0
0
0
0
0
1
0
0
0
0
0
220 ps
4720 ps
0
0
0
0
1
0
0
0
0
0
0
640 ps
5040 ps
0
0
0
1
0
0
0
0
0
0
0
1280 ps
5680 ps
0
0
1
0
0
0
0
0
0
0
0
2560 ps
6960 ps
0
1
0
0
0
0
0
0
0
0
0
5120 ps
9520 ps
0
1
1
1
1
1
1
1
1
1
1
10230 ps
14630 ps
VARIABLE INPUT TO CHIP #1 AND SETMAX FOR CHIP #2
INPUT FOR CHIP #1
Total
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Delay Value
Delay Value
1
0
0
0
0
0
0
0
0
0
0
10240 ps
14640 ps
1
0
0
0
0
0
0
0
0
0
1
10250 ps
14650 ps
1
0
0
0
0
0
0
0
0
1
0
10260 ps
14660 ps
1
0
0
0
0
0
0
0
0
1
1
10270 ps
14670 ps
1
0
0
0
0
0
0
0
1
0
0
10280 ps
14680 ps
1
0
0
0
0
0
0
0
1
0
1
10290 ps
14690 ps
1
0
0
0
0
0
0
0
1
1
0
10300 ps
14700 ps
1
0
0
0
0
0
0
0
1
1
1
10310 ps
14710 ps
1
0
0
0
0
0
0
1
0
0
0
10320 ps
14720 ps
1
0
0
0
0
0
1
0
0
0
0
10400 ps
14800 ps
1
0
0
0
0
1
0
0
0
0
0
10560 ps
14960 ps
1
0
0
0
1
0
0
0
0
0
0
10880 ps
15280 ps
1
0
0
1
0
0
0
0
0
0
0
11520 ps
15920 ps
1
0
1
0
0
0
0
0
0
0
0
12800 ps
17200 ps
1
1
0
0
0
0
0
0
0
0
0
15360 ps
19760 ps
1
1
1
1
1
1
1
1
1
1
1
20470 ps
24870 ps
www.onsemi.com
12
MC100EP195B
Multi−Channel Deskewing
be sent through each EP195B as shown in Figure 7. One signal
channel can be used as reference and the other EP195Bs can
be used to adjust the delay to eliminate the timing skews.
Nearly any high−speed system can be fine−tuned (as small as
10 ps) to reduce the skew to extremely tight tolerances.
The most practical application for EP195B is in multiple
channel delay matching. Slight differences in impedance and
cable length can create large timing skews within a high−speed
system. To deskew multiple signal channels, each channel can
EP195B
IN
IN
Q
Q
#1
EP195B
IN
IN
Q
Q
#2
EP195B
IN
IN
Q
Q
#N
Control
Logic
Digital
Data
Figure 7. Multiple Channel Deskewing Diagram
Measure Unknown High Speed Device Delays
If the programmed delay through the second EP195B is too
long, the flip−flop output will be at logic high. On the other
hand, if the programmed delay through the second EP195B is
too short, the flip−flop output will be at a logic low. If the
programmed delay is correctly fine−tuned in the second
EP195B, the flip−flop will bounce between logic high and
logic low. The digital code in the second EP195B can be
directly correlated into an accurate device delay.
EP195Bs provide a possible solution to measure the
unknown delay of a device with a high degree of precision.
By combining two EP195Bs and EP31 as shown in Figure
8, the delay can be measured. The first EP195B can be set
to SETMIN and its output is used to drive the unknown delay
device, which in turn drives the input of a D flip−flop of
EP31. The second EP195B is triggered along with the first
EP195B and its output provides a clock signal for EP31.
The programmed delay of the second EP195B is varied to
detect the output edge from the unknown delay device.
EP195B
CLOCK
IN
IN
CLOCK
Q
Q
Unknown Delay
Device
#1
D
Q
EP31
CLK
EP195B
IN
IN
Q
Q
#2
Control
Logic
Figure 8. Multiple Channel Deskewing Diagram
www.onsemi.com
13
Q
MC100EP195B
Q
Zo = 50 W
D
Receiver
Device
Driver
Device
Q
D
Zo = 50 W
50 W
50 W
VTT
VTT = VCC − 2.0 V
Figure 9. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1642/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
www.onsemi.com
14
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
QFN32 5x5, 0.5P
CASE 488AM
ISSUE A
1 32
SCALE 2:1
A
D
PIN ONE
LOCATION
ÉÉ
ÉÉ
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L
L
B
DATE 23 OCT 2013
L1
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTIONS
E
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
0.15 C
0.15 C
EXPOSED Cu
A
DETAIL B
0.10 C
(A3)
A1
0.08 C
DETAIL A
9
32X
L
ALTERNATE
CONSTRUCTION
GENERIC
MARKING DIAGRAM*
K
D2
1
XXXXXXXX
XXXXXXXX
AWLYYWWG
G
17
8
MOLD CMPD
DETAIL B
SEATING
PLANE
C
SIDE VIEW
NOTE 4
ÉÉ
ÉÉ
ÇÇ
TOP VIEW
MILLIMETERS
MIN
MAX
0.80
1.00
−−−
0.05
0.20 REF
0.18
0.30
5.00 BSC
2.95
3.25
5.00 BSC
2.95
3.25
0.50 BSC
0.20
−−−
0.30
0.50
−−−
0.15
E2
1
32
25
e
e/2
32X
b
0.10
M
C A B
0.05
M
C
BOTTOM VIEW
XXXXX = Specific Device Code
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer
to device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
NOTE 3
RECOMMENDED
SOLDERING FOOTPRINT*
5.30
32X
0.63
3.35
3.35 5.30
0.50
PITCH
32X
0.30
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON20032D
QFN32 5x5 0.5P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
LQFP−32, 7x7
CASE 561AB−01
ISSUE O
DOCUMENT NUMBER:
DESCRIPTION:
98AON30893E
32 LEAD LQFP, 7X7
DATE 19 JUN 2008
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
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