MC100EPT622MNR4G

3.3 V LVTTL/LVCMOS to LVPECL Translator MC100EPT622 Description The MC100EPT622 is a 10−Bit LVTTL/LVCMOS to LVPECL translator. Because LVPECL (Positive ECL) levels are used only +3.3 V and ground are required. The device has an OR−ed enable input which can accept either LVPECL (ENPECL) or TTL/LVCMOS inputs (ENTTL). If the inputs are left open, they will default to the enable state. The device design has been optimized for low channel−to−channel skew. www.onsemi.com MARKING DIAGRAMS* Features • • • • • • • • 450 ps Typical Propagation Delay Maximum Frequency > 1.5 GHz Typical MC100 EPT622 AWLYYWWG LQFP−32 FA SUFFIX CASE 561AB PECL Mode 32 Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V 1 PNP LVTTL Inputs for Minimal Loading Q Output Will Default HIGH with Inputs Open 1 MC100 EPT622 AWLYYWWG G The 100 Series Contains Temperature Compensation These Devices are Pb−Free, Halogen Free and are RoHS Compliant 32 1 QFN32 MN SUFFIX CASE 488AM A WL YY WW G or G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. Table 1. TRUTH TABLE ENPECL ENTTL D Q H X H H H X L L X H H H X H L L L L X L ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. © Semiconductor Components Industries, LLC, 2011 March, 2021 − Rev. 7 1 Publication Order Number: MC100EPT622/D MC100EPT622 VCCO D4 D3 D2 VEE D1 ENPECL D0 VCCO ENTTL D0 25 26 27 28 29 30 31 32 Q4 17 8 VEE Q3 18 7 ENPECL VCCO 19 6 ENTTL Q2 20 5 D9 MC100EPT622 Q1 21 4 D8 Q0 22 3 D7 VCCO 23 2 D6 24 1 D5 VCCO 16 15 14 13 12 11 10 9 32 31 D2 VEE D1 D0 VCCO 30 29 27 26 28 25 24 VCCO D6 2 23 Q0 D7 3 22 Q1 D8 4 21 Q2 D9 5 20 VCCO ENTTL 6 19 Q3 ENPECL 7 18 Q4 VEE 8 17 VCCO 10 11 12 13 Q8 Q7 VCC Q6 14 15 LVCMOS/TTL D4 D7 D8 1 9 D3 (EP) D5 VCCO Q9 D2 D6 Figure 1. 32−Lead LQFP Pinout (Top View) Exposed Pad D3 D1 D5 VCCO Q9 Q8 Q7 VCC Q6 Q5 VCCO Warning: All VCC, VCCO, and VEE pins must be externally connected to Power Supply to guarantee proper operation. VCCO D4 Q0 D9 Q1 Q2 Q3 Q4 LVPECL Q5 Q6 Q7 Q8 Q9 Figure 2. Logic Symbol 16 Q5 VCCO Figure 3. 32−Lead QFN Pinout (Top View) Table 1. PIN DESCRIPTION Pin Function D0:9 Data Input (TTL) Q0:9 Data Outputs (PECL) ENTTL Enable Control (TTL) ENPECL VCC, VCCO Enable Control (PECL) Positive Supply VEE Ground EP The exposed pad (EP) on the QFN−32 package bottom is thermally connected to the die for improved heat transfer out of the package. THe exposed pad must be attached to a heat−sinking conduit. The pad is electrically connected to VEE. www.onsemi.com 2 MC100EPT622 Table 2. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor N/A Internal Input Pullup Resistor N/A ESD Protection Human Body Model Machine Model Charged Device Model > 2 kV > 150 V > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack Pb−Free Pkg LQFP−32 QFN−32 Level 2 Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 596 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Table 3. MAXIMUM RATINGS Symbol Parameter Condition 1 VCC Power Supply VEE = 0 V VI Input Voltage VEE = 0 V Iout Output Current Continuous Surge Condition 2 VI ≤ VCC Rating Unit 5 V 5 to 0 V 50 100 mA mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm 32 LQFP 32 LQFP 80 55 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board 32 LQFP 12 to 17 °C/W qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm QFN−32 QFN−32 31 27 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) 2S2P QFN−32 12 °C/W Tsol Wave Solder 265 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Table 4. TTL INPUT DC CHARACTERISTICS (VCC = 3.3 V, GND= 0.0 V, TA = −40°C to 85°C) Symbol Characteristic Condition Min Typ Max Unit IIH Input HIGH Current VIN = 2.7 V 25 mA IIHH Input HIGH Current MAX VIN = VCC 100 mA IIL Input LOW Current VIN = 0.5 V −0.6 mA IIN = −18 mA VIK Input Clamp Voltage VIH Input HIGH Voltage VIL Input LOW Voltage −1.2 −0.9 V 2.0 V 0.8 V NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. www.onsemi.com 3 MC100EPT622 Table 5. PECL INPUT DC CHARACTERISTICS VCC = 3.3 V, GND= 0.0 V, TA = −40°C to 85°C Symbol Characteristic Condition Min Typ Max Unit IIH Input HIGH Current VIN = 2420 mV 150 mA IIL Input LOW Current VIN = 1490 mV 200 mA VIH Input HIGH Voltage 2075 2420 mV VIL Input LOW Voltage 1490 1675 mV NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Table 6. PECL OUTPUT DC CHARACTERISTICS VCC = 3.3 V, GND = 0.0 V (Note 1) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 85 115 145 90 120 155 95 130 155 mA IEE Power Supply Current VOH Output High Voltage (Note 2) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mV VOL Output Low Voltage (Note 2) 1355 1520 1700 1355 1520 1700 1355 1520 1700 mV NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 1. Input and output parameters vary 1:1 with VCC. 2. All loading with 50 W to VCC−2.0 V. Table 7. AC CHARACTERISTICS VCC = 3.0 V to 3.8 V (Note 3) −40°C Symbol Characteristic Min Typ 25°C Max fmax Maximum Frequency (See Figure 4) 1.0 1.5 tPLH, tPHL Propagation Delay to Output (Figure 5, Note 4) D to Q ENPECL to Q ENTTL to Q 100 150 300 450 500 450 800 875 800 0.7 3.0 200 450 tJITTER tr / tf TSKEW Random Clock Jitter (RMS) (See Figure 4) Output Rise/Fall Times (20% − 80%) 100 Duty Cycle Skew (Note 5) D to Q Channel 0−7 Channel 8−9 ENPECL to Q ENTTL to Q 85°C Min Typ 1.0 1.5 100 150 300 500 500 500 875 875 800 0.7 3.0 200 250 100 Max Min Typ 1.0 1.5 100 200 300 500 550 500 800 925 800 0.7 3.0 ps 200 300 ps 100 Max Unit GHz ps ps 120 200 120 100 375 775 400 275 120 200 120 100 375 775 400 275 120 200 120 100 375 775 400 275 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 3. Measured using a 2.4 V source, 50% duty cycle clock source. All loading with 50 W to VCC−2.0 V. 4. 1.5 V to 50% point of the output. 5. Duty cycle skew |tPLH − tPHL| on the specific path. www.onsemi.com 4 MC100EPT622 2400 10.0 9.0 8.0 VCC = 3.3 V TA = 25°C 2000 VOH (mV) 7.0 6.0 VOL (mV) 1800 5.0 1600 4.0 1400 3.0 RMS Jitter (ps) 1200 RMS JITTER (ps) OUTPUT AMPLITUDE (mV) 2200 2.0 1.0 1000 0.5 1.0 1.5 2.0 0.0 FREQUENCY (GHz) Figure 4. Average Output Amplitude/Jitter (3.3 V, 255C) 800 700 tPLH, tPHL (ps) 600 500 400 300 200 100 0 ÉÉ tPLH ÉÉ ÉÉ ÉÉÉÉ ÉÉ É É ÉÉ ÉÉ ÉÉ É É ÉÉ É É É ÉÉ ÉÉÉÉ ÉÉ É É ÉÉ É É É ÉÉ É É ÉÉÉÉÉÉ ÉÉÉÉ ÉÉ ÉÉ ÉÉ É É ÉÉ É É É ÉÉÉÉÉÉ ÉÉÉÉÉÉÉ É É ÉÉÉ ÉÉÉÉÉÉÉÉÉÉ tPHL CHANNEL Figure 5. Average Propagation Delay (3.3 V, 255C) Q Zo = 50 W D Receiver Device Driver Device Q D Zo = 50 W 50 W 50 W VTT VTT = VCC − 2.0 V Figure 6. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) www.onsemi.com 5 MC100EPT622 ORDERING INFORMATION Package Shipping MC100EPT622FAG Device LQFP−32 (Pb−Free) 250 Units / Tray MC100EPT622MNG QFN32 (Pb−Free) 74 Units / Rail Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. www.onsemi.com 6 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS QFN32 5x5, 0.5P CASE 488AM ISSUE A 1 32 SCALE 2:1 A D PIN ONE LOCATION ÉÉ ÉÉ NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30MM FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L L B DATE 23 OCT 2013 L1 DETAIL A ALTERNATE TERMINAL CONSTRUCTIONS E DIM A A1 A3 b D D2 E E2 e K L L1 0.15 C 0.15 C EXPOSED Cu A DETAIL B 0.10 C (A3) A1 0.08 C DETAIL A 9 32X L ALTERNATE CONSTRUCTION GENERIC MARKING DIAGRAM* K D2 1 XXXXXXXX XXXXXXXX AWLYYWWG G 17 8 MOLD CMPD DETAIL B SEATING PLANE C SIDE VIEW NOTE 4 ÉÉ ÉÉ ÇÇ TOP VIEW MILLIMETERS MIN MAX 0.80 1.00 −−− 0.05 0.20 REF 0.18 0.30 5.00 BSC 2.95 3.25 5.00 BSC 2.95 3.25 0.50 BSC 0.20 −−− 0.30 0.50 −−− 0.15 E2 1 32 25 e e/2 32X b 0.10 M C A B 0.05 M C BOTTOM VIEW XXXXX = Specific Device Code A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. NOTE 3 RECOMMENDED SOLDERING FOOTPRINT* 5.30 32X 0.63 3.35 3.35 5.30 0.50 PITCH 32X 0.30 DIMENSION: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON20032D QFN32 5x5 0.5P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS LQFP−32, 7x7 CASE 561AB−01 ISSUE O DOCUMENT NUMBER: DESCRIPTION: 98AON30893E 32 LEAD LQFP, 7X7 DATE 19 JUN 2008 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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