MC74LVX259
8-Bit Addressable
Latch/1-of-8 Decoder
CMOS Logic Level Shifter
With LSTTL−Compatible Inputs
http://onsemi.com
The MC74LVX259 is an 8−bit Addressable Latch fabricated with
silicon gate CMOS technology.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The LVX259 is designed for general purpose storage applications in
digital systems. The device has four modes of operation as shown in
the mode selection table. In the addressable latch mode, the data on
Data In is written into the addressed latch. The addressed latch follows
the data input with all non−addressed latches remaining in their
previous states. In the memory mode, all latches remain in their
previous state and are unaffected by the Data or Address inputs. In the
one−of−eight decoding or demultiplexing mode, the addressed output
follows the state of Data In with all other outputs in the LOW state. In
the Reset mode, all outputs are LOW and unaffected by the address
and data inputs. When operating the LVX259 as an addressable latch,
changing more than one bit of the address could impose a transient
wrong address. Therefore, this should only be done while in the
memory mode.
The MC74LVX259 input structure provides protection when
voltages up to 7.0 V are applied, regardless of the supply voltage. This
allows the MC74LVX259 to be used to interface 5.0 V circuits to
3.0 V circuits.
SOIC−16
D SUFFIX
CASE 751B
PIN ASSIGNMENT
•
A0
1
16
VCC
A1
2
15
RESET
A2
3
14
ENABLE
Q0
4
13
DATA IN
Q1
5
12
Q7
Q2
6
11
Q6
Q3
7
10
Q5
GND
8
9
Q4
MARKING DIAGRAMS
Features
•
•
•
•
•
•
•
•
•
TSSOP−16
DT SUFFIX
CASE 948F
High Speed: tPD = 7.0 ns (Typ) at VCC = 3.3 V
Low Power Dissipation: ICC = 2 mA (Max) at TA = 25°C
High Noise Immunity: VNIH = VNIL = 28% VCC
CMOS−Compatible Outputs: VOH > 0.8 VCC; VOL < 0.1 VCC @Load
Power Down Protection Provided on Inputs and Outputs
Balanced Propagation Delays
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
ESD Performance:
Human Body Model > 2000 V;
Machine Model > 200 V
These Devices are Pb−Free and are RoHS Compliant
16
16
LVX
259
ALYWG
G
LVX259G
AWLYWW
1
1
SOIC−16
LVX259
A
WL, L
Y
WW, W
G or G
TSSOP−16
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 4
1
Publication Order Number:
MC74LVX259/D
MC74LVX259
4
A0
ADDRESS
INPUTS
A1
A2
DATA IN
RESET
ENABLE
1
5
Q0
Q1
2
6
Q2
7
9
10
Q3
Q4
Q5
11
12
Q6
3
13
NONINVERTING
OUTPUTS
Q7
PIN 16 = VCC
PIN 8 = GND
15
14
Figure 1. Logic Diagram
A0
1
A1
2
A2
3
BIN/OCT
1
0
2
1
4
2
3
4
13
ID
14
EN
6
15
R
7
5
4
5
6
7
8
10
11
12
A0
1
Q1
A1
2
Q2
A2
3
Q0
DMUX
0
0
0
G
7
1
2
2
Q3
3
Q4
4
13
Q5
ID
14
Q6
15
Q7
5
EN
6
R
7
4
5
6
7
8
10
11
12
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Figure 2. IEC Logic Symbol
MODE SELECTION TABLE
Enable
Reset
LATCH SELECTION TABLE
Mode
Address Inputs
B
A
Latch
Addressed
L
H
Addressable Latch
C
H
H
Memory
L
L
L
Q0
L
L
8−Line Demultiplexer
L
L
H
Q1
H
L
Reset
L
H
L
Q2
L
H
H
Q3
H
L
L
Q4
H
L
H
Q5
H
H
L
Q6
H
H
H
Q7
http://onsemi.com
2
MC74LVX259
DATA INPUT
13
D
D
D
D
4
5
6
7
Q0
Q1
Q2
Q3
A0
ADDRESS
INPUTS
3 TO 8
DECODER
A1
D
9
Q4
A2
D
ENABLE
Q5
14
D
D
RESET
10
15
Figure 3. Expanded Logic Diagram
http://onsemi.com
3
11
12
Q6
Q7
MC74LVX259
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VCC
Positive DC Supply Voltage
−0.5 to +7.0
V
VIN
Digital Input Voltage
−0.5 to +7.0
V
VOUT
DC Output Voltage
−0.5 to VCC +0.5
V
IIK
Input Diode Current
−20
mA
IOK
Output Diode Current
±20
mA
IOUT
DC Output Current, per Pin
±25
mA
ICC
DC Supply Current, VCC and GND Pins
±75
mA
PD
Power Dissipation in Still Air
200
180
mW
TSTG
Storage Temperature Range
−65 to +150
°C
VESD
ESD Withstand Voltage
> 2000
> 200
> 2000
V
Above VCC and Below GND at 125°C (Note 4)
±300
mA
SOIC Package
TSSOP
143
164
°C/W
ILATCHUP
qJA
SOIC Package
TSSOP
Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
Latchup Performance
Thermal Resistance, Junction−to−Ambient
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Tested to EIA/JESD22−A114−A
2. Tested to EIA/JESD22−A115−A
3. Tested to JESD22−C101−A
4. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol
Characteristics
Min
Max
Unit
2.0
3.6
V
VCC
DC Supply Voltage
VIN
DC Input Voltage
0
5.5
V
DC Output Voltage
0
VCC
V
−40
85
°C
0
100
ns/V
VOUT
TA
Operating Temperature Range, all Package Types
tr, tf
Input Rise or Fall Time
VCC = 3.3 V ± 0.3 V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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4
MC74LVX259
DC CHARACTERISTICS (Voltages Referenced to GND)
VCC
Symbol
Parameter
Condition
−40°C ≤ TA ≤ 85°C
TA = 25°C
(V)
Min
Typ
Max
Min
Max
Unit
VIH
Minimum High−Level
Input Voltage
2.0
3.0
3.6
0.75 VCC
0.7 VCC
0.7 VCC
−
−
−
−
−
−
0.75 VCC
0.7 VCC
0.7 VCC
−
−
−
V
VIL
Maximum Low−Level
Input Voltage
2.0
3.0
3.6
−
−
−
−
−
−
0.25 VCC
0.3 VCC
0.3 VCC
−
−
−
0.25 VCC
0.3 VCC
0.3 VCC
V
VOH
High−Level Output
Voltage
IOH = −50 mA
2.0
1.9
2.0
−
1.9
−
V
IOH = −50 mA
3.0
2.9
3.0
−
2.9
−
IOH = −4 mA
3.0
2.58
−
−
2.48
−
IOL = 50 mA
2.0
−
0.0
0.1
−
0.1
IOL = 50 mA
3.0
−
0.0
0.1
−
0.1
VOL
Low−Level Output
Voltage
IOL = 4 mA
V
3.0
−
−
0.36
−
0.44
IIN
Input Leakage Current
VIN = 5.5 V or GND
0 to 3.6
−
−
±0.1
−
±1.0
mA
ICC
Maximum Quiescent
Supply Current
(per package)
VIN = VCC or GND
3.6
1.0
1.0
2.0
−
−
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
AC ELECTRICAL CHARACTERISTICS Input tr = tf = 3.0 ns
−40°C ≤ TA ≤ 85°C
TA = 25°C
Symbol
tPLH,
tPHL
tPLH,
tPHL
tPLH,
tPHL
tPHL
CIN
Parameter
Maximum Propagation
Delay, Data to Output
(Figures 4 and 8)
Test Conditions
Min
Typ
Max
Min
Max
Unit
ns
VCC = 2.7 V
CL = 15pF
CL = 50pF
−
−
6.3
9.0
9.0
14.0
1.0
1.0
12.0
15.0
VCC = 3.3 V ± 0.3 V
CL = 15pF
CL = 50pF
−
−
5.6
8.0
8.0
12.0
1.0
1.0
11.0
14.0
Maximum Propagation
Delay, Address Select
to Output
(Figures 5 and 8)
VCC = 2.7 V
CL = 15pF
CL = 50pF
−
−
6.3
9.0
9.0
14.0
1.0
1.0
12.0
15.0
VCC = 3.3 V ± 0.3 V
CL = 15pF
CL = 50pF
−
−
5.6
8.0
8.0
12.0
1.0
1.0
11.0
14.0
Maximum Propagation
Delay, Enable to Output
(Figures 6 and 8)
VCC = 2.7 V
CL = 15pF
CL = 50pF
−
−
6.3
9.0
9.0
14.0
1.0
1.0
12.0
15.0
VCC = 3.3 V ± 0.3 V
CL = 15pF
CL = 50pF
−
−
5.6
8.0
9.0
12.0
1.0
1.0
11.0
14.0
VCC = 2.7 V
CL = 15pF
CL = 50pF
−
−
6.3
9.0
9.0
14.0
1.0
1.0
12.0
15.0
VCC = 3.3 V ± 0.3 V
CL = 15pF
CL = 50pF
−
−
5.6
8.0
9.0
12.0
1.0
1.0
11.0
14.0
−
6
10
−
10
Maximum Propogation
Delay, Reset to Output
(Figures 6 and 8)
Maximum Input
Capacitance
ns
ns
ns
pF
Typical @ 25°C, VCC = 3.3 V
CPD
30
Power Dissipation Capacitance (Note 5)
pF
5. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no−load dynamic
power consumption; PD = CPD VCC2 fin + ICC VCC.
http://onsemi.com
5
MC74LVX259
TIMING REQUIREMENTS Input tr = tf = 3.0 ns
TA = ≤ 85°C
TA = 25°C
Symbol
Parameter
tw
tsu
th
tr, tf
Test Conditions
Min
Typ
Max
Min
Max
Unit
ns
Minimum Pulse Width, Reset or Enable
(Figure 7)
VCC = 2.7 V
4.5
−
−
5.0
−
VCC = 3.3 V ± 0.3 V
4.5
−
−
5.0
−
Minimum Setup Time, Address or Data to Enable
(Figure 7)
VCC = 2.7 V
4.0
−
−
4.0
−
VCC = 3.3 V ± 0.3 V
3.0
−
−
3.0
−
Minimum Hold Time, Enable to Address or Data
(Figure 6 or 7)
VCC = 2.7 V
2.0
−
−
2.0
−
VCC = 3.3 V ± 0.3 V
2.0
−
−
2.0
−
Maximum Input, Rise and Fall Times
(Figure 4)
VCC = 2.7 V
−
−
400
−
300
VCC = 3.3 V ± 0.3 V
−
−
300
−
300
ns
ns
ns
VCC
DATA
IN
tf
tr
VCC
50%
DATA
IN
GND
ADDRESS
SELECT
VCC
50%
GND
GND
tPLH
tPHL
VCC
50%
GND
50%
tPHL
OUTPUT
Q
tPHL
OUTPUT
Q
50%
Figure 4. Switching Waveform
Figure 5. Switching Waveform
VCC
DATA IN
tw
tw
ENABLE
50%
50%
tPHL
VCC
GND
DATA IN
VCC
RESET
tw
50%
tPHL
GND
VCC
50%
GND
GND
tPHL
OUTPUT Q
OUTPUT Q
50%
Figure 6. Switching Waveform
Figure 7. Switching Waveform
TEST POINT
DATA IN OR
ADDRESS
SELECT
VCC
OUTPUT
50%
th(H)
tsu
th(H)
tsu
ENABLE
GND
DEVICE
UNDER
TEST
CL *
VCC
50%
GND
*Includes all probe and jig capacitance
Figure 8. Switching Waveform
Figure 9. Test Circuit
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6
MC74LVX259
ORDERING INFORMATION
Package
Shipping†
MC74LVX259DG
SOIC−16
(Pb−Free)
48 Units / Rail
MC74LVX259DR2G
SOIC−16
(Pb−Free)
2500 Tape & Reel
MC74LVX259DTG
TSSOP−16
(Pb−Free)
96 Units / Rail
MC74LVX259DTR2G
TSSOP−16
(Pb−Free)
2500 Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
EMBOSSED CARRIER DIMENSIONS (See Notes 6 and 7)
Tape
Size
B1
Max
8 mm
4.35 mm
(0.179”)
12 mm
8.2 mm
(0.323”)
16 mm
24 mm
D
D1
E
F
K
P
P0
P2
R
T
W
1.5 mm
+ 0.1
−0.0
(0.059”
+0.004
−0.0)
1.0 mm
Min
(0.179”)
1.75 mm
±0.1
(0.069
±0.004”)
3.5 mm
±0.5
(1.38
±0.002”)
2.4 mm
Max
(0.094”)
4.0 mm
±0.10
(0.157
±0.004”)
4.0 mm
±0.1
(0.157
±0.004”)
2.0 mm
±0.1
(0.079
±0.004”)
25 mm
(0.98”)
0.6 mm
(0.024)
8.3 mm
(0.327)
5.5 mm
±0.5
(0.217
±0.002”)
6.4 mm
Max
(0.252”)
4.0 mm
±0.10
(0.157
±0.004”)
8.0 mm
±0.10
(0.315
±0.004”)
12.1 mm
(0.476”)
7.5 mm
±0.10
(0.295
±0.004”)
7.9 mm
Max
(0.311”)
4.0 mm
±0.10
(0.157
±0.004”)
8.0 mm
±0.10
(0.315
±0.004”)
12.0 mm
±0.10
(0.472
±0.004”)
16.3 mm
(0.642)
20.1 mm
(0.791”)
11.5 mm
±0.10
(0.453
±0.004”)
11.9 mm
Max
(0.468”)
16.0 mm
±0.10
(0.63
±0.004”)
24.3 mm
(0.957)
1.5 mm
Min
(0.060)
30 mm
(1.18”)
12.0 mm
±0.3
(0.470
±0.012”)
6. Metric Dimensions Govern−English are in parentheses for reference only.
7. A0, B0, and K0 are determined by component size. The clearance between the components and the cavity must be within 0.05 mm min to
0.50 mm max. The component cannot rotate more than 10° within the determined cavity
http://onsemi.com
7
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
DATE 29 DEC 2006
SCALE 1:1
−A−
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
9
−B−
1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
F
X 45 _
C
−T−
SEATING
PLANE
J
M
D
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
16 PL
0.25 (0.010)
M
T B
S
A
S
STYLE 1:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
COLLECTOR
BASE
EMITTER
NO CONNECTION
EMITTER
BASE
COLLECTOR
COLLECTOR
BASE
EMITTER
NO CONNECTION
EMITTER
BASE
COLLECTOR
EMITTER
COLLECTOR
STYLE 2:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
CATHODE
ANODE
NO CONNECTION
CATHODE
CATHODE
NO CONNECTION
ANODE
CATHODE
CATHODE
ANODE
NO CONNECTION
CATHODE
CATHODE
NO CONNECTION
ANODE
CATHODE
STYLE 3:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
COLLECTOR, DYE #1
BASE, #1
EMITTER, #1
COLLECTOR, #1
COLLECTOR, #2
BASE, #2
EMITTER, #2
COLLECTOR, #2
COLLECTOR, #3
BASE, #3
EMITTER, #3
COLLECTOR, #3
COLLECTOR, #4
BASE, #4
EMITTER, #4
COLLECTOR, #4
STYLE 4:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
STYLE 5:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
DRAIN, DYE #1
DRAIN, #1
DRAIN, #2
DRAIN, #2
DRAIN, #3
DRAIN, #3
DRAIN, #4
DRAIN, #4
GATE, #4
SOURCE, #4
GATE, #3
SOURCE, #3
GATE, #2
SOURCE, #2
GATE, #1
SOURCE, #1
STYLE 6:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
ANODE
ANODE
ANODE
ANODE
ANODE
ANODE
ANODE
ANODE
STYLE 7:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
SOURCE N‐CH
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
GATE P‐CH
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
SOURCE P‐CH
SOURCE P‐CH
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
GATE N‐CH
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
SOURCE N‐CH
COLLECTOR, DYE #1
COLLECTOR, #1
COLLECTOR, #2
COLLECTOR, #2
COLLECTOR, #3
COLLECTOR, #3
COLLECTOR, #4
COLLECTOR, #4
BASE, #4
EMITTER, #4
BASE, #3
EMITTER, #3
BASE, #2
EMITTER, #2
BASE, #1
EMITTER, #1
SOLDERING FOOTPRINT
8X
6.40
16X
1
1.12
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42566B
SOIC−16
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−16
CASE 948F−01
ISSUE B
16
DATE 19 OCT 2006
1
SCALE 2:1
16X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
S
V
S
K
S
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
K1
2X
L/2
16
9
J1
B
−U−
L
SECTION N−N
J
PIN 1
IDENT.
N
8
1
0.25 (0.010)
M
0.15 (0.006) T U
S
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
N
F
DETAIL E
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
D
H
G
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193 0.200
0.169 0.177
−−− 0.047
0.002 0.006
0.020 0.030
0.026 BSC
0.007
0.011
0.004 0.008
0.004 0.006
0.007 0.012
0.007 0.010
0.252 BSC
0_
8_
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT
7.06
16
XXXX
XXXX
ALYW
1
1
0.65
PITCH
16X
0.36
DOCUMENT NUMBER:
DESCRIPTION:
16X
1.26
98ASH70247A
TSSOP−16
DIMENSIONS: MILLIMETERS
XXXX
A
L
Y
W
G or G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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