NB3L8504SDTR2G

NB3L8504S 2.5 V / 3.3 V 1:4 Differential Input to LVDS Fanout Buffer / Translator Description The NB3L8504S is a differential 1:4 LVDS fanout buffer/translator with OE control for each differential output. The differential inputs which can be driven by either a differential or single−ended input, can accept various logic level standards such as LVPECL, LVDS, HSTL, HCSL and SSTL. These signals are then translated to four identical LVDS copies of the input up to 700 MHz. As such, the NB3L8504S is ideal for Clock distribution applications that require low skew. The NB3L8504S is offered in the TSSOP−16 package. www.onsemi.com MARKING DIAGRAM* 16 16 1 Features • • • • • • • • • • • • • NB3L 8504 ALYWG G 1 Four Differential LVDS Outputs Each Differential Output has OE Control 700 MHz Maximum Output Frequency 660 ps Max Output Rise and Fall Times, LVCMOS Translates Differential Input to LVDS Levels Additive Phase Jitter RMS: < 100 fs Typical 50 ps Maximum Output Skew 350 ps Maximum Part−to−part Skew 1.3 ns Maximum Propagation Delay Operating Range: VCC = 2.5 V ± 5% or 3.3 V ± 10% −40°C to +85°C Ambient Operating Temperature 16−Pin TSSOP, 4.4 mm x 5.0 mm x 0.925 mm These are Pb−Free Devices A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. Applications • • • • TSSOP−16 DT SUFFIX CASE 948F CLK Telecom Ethernet Networking SONET CLK Figure 1. Logic Diagram ORDERING INFORMATION See detailed ordering and shipping information on page 9 of this data sheet. © Semiconductor Components Industries, LLC, 2016 April, 2016 − Rev. 2 1 Publication Order Number: NB3L8504S/D NB3L8504S Table 1. PIN DESCRIPTIONS AND CHARACTERISTICS Pin Name I/O Description 1 OE0 LVTTL/LVCMOS Input Output Enable pin for Q0, Q0 outputs. Defaults High when left open; internal pull−up resistor. 2 OE1 LVTTL/LVCMOS Input Output Enable pin for Q1, Q1 outputs. Defaults High when left open; internal pull−up resistor. 3 OE2 LVTTL/LVCMOS Input Output Enable pin for Q2, Q2 outputs. Defaults High when left open; internal pull−up resistor. 4 VDD Power 3.3 V / 2.5 V Positive Supply Voltage. 5 GND Power 3.3 V / 2.5 V Negative Supply Voltage. 6 CLK Multi−Level Input Non−inverting differential Clock input. Defaults Low when left open; internal pull−down resistor. 7 CLK Multi−Level Input Inverting differential Clock input. Defaults to VDD/2 when left open; internal pull−up and pull−down resistors. 8 OE3 LVTTL/LVCMOS Input 9 Q3 LVDS Output Inverting differential Clock output. 10 Q3 LVDS Output Non−inverting differential Clock output. 11 Q2 LVDS Output Inverting differential Clock output. 12 Q2 LVDS Output Non−inverting differential Clock output. 13 Q1 LVDS Output Inverting differential Clock output. 14 Q1 LVDS Output Non−inverting differential Clock output. 15 Q0 LVDS Output Inverting differential Clock output. 16 Q0 LVDS Output Non−inverting differential Clock output. Output Enable pin for Q3, Q3 outputs. Defaults High when left open; internal pull−up resistor. 1. All VDD and GND pins must be externally connected to a power supply for proper operation. OE0 1 16 Q0 OE1 2 15 Q0 OE2 3 14 Q1 VDD 4 13 Q1 GND 5 12 Q2 CLK 6 11 Q2 CLK 7 10 Q3 OE3 8 9 Q3 Figure 2. NB3L8504S Pinout, 16−pin TSSOP (Top View) Table 2. OUTPUT ENABLE FUNCTION TABLE OE[3:0] Outputs – Q[0:3], Q[0:3] LOW High Impedance HIGH (Default) Active www.onsemi.com 2 NB3L8504S Table 3. ATTRIBUTES Characteristics Value ESD Protection Human Body Model Machine Model RPU − Input Pull−up Resistor RPD − Input Pull−down Resistor 50 kW 50 kW CIN − Input Capacitance 4 pF RIN − Input Impedance 10 kW Moisture Sensitivity (Note 2) Flammability Rating > 2 kV > 200 V TSSOP−16 Oxygen Index: 28 to 34 Transistor Count Level 1 UL 94 V−0 @ 0.125 in 371 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 2. For additional information, see Application Note AND8003/D. Table 4. MAXIMUM RATINGS Symbol Condition Rating Unit VDD GND = 0 V 4.6 V VIN GND = 0 V −0.5 to VDD +0.5 V LVDS Outputs 10 15 mA mA 12 24 mA mA −40 to +85 _C −65 to +150 _C Iout IOSC Parameter Continuous Current Surge Current Output Short Circuit Current Line−to−Line (Q to Q) Line−to−GND (Q or Q to GND) Q or Q Q to Q to GND Continuous Continuous TA Operating Temperature Range TSSOP−16 Tstg Storage Temperature Range θJA Thermal Resistance (Junction−to−Ambient) (Note 3) 0 lfpm 500 lfpm TSSOP−16 TSSOP−16 138 108 _C/W _C/W θJC Thermal Resistance (Junction−to−Case) (Note 3) TSSOP−16 33 − 36 _C/W Tsol Wave Solder (Pb−Free) 265 _C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 3. JEDEC standard multilayer board – 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. www.onsemi.com 3 NB3L8504S Table 5. DC CHARACTERISTICS VDD = 2.5 V ± 5% or 3.3 V ± 10%; GND = 0 V; TA = −40°C to 85°C Characteristic Symbol Min Typ Max Unit 2.97 2.375 3.3 2.5 3.63 2.625 V 41 50 mA 250 350 450 mV 50 mV 1075 1250 1375 mV 50 mV 1600 mV POWER SUPPLY / CURRENT (Note 4) VDD Power Supply Voltage IDD Power Supply Current for VDD VDD = 3.3 V VDD = 2.5 V LVDS OUTPUTS (Note 5) VOD DVOD VOS DVOS Differential Output Voltage (Figure 12) (Notes 6 and 7) VOD Magnitude Change (Figure 12) (Notes 6 and 7) Offset Voltage (Figure 13) (Notes 6 and 7) VOS Magnitude Change (Figure 13) (Notes 6 and 7) VOH Output HIGH Voltage VOL Output LOW Voltage 1425 900 1075 mV DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (see Figure 5 & 6) (Note 11) VIHD Differential Input HIGH Voltage 500 VDD – 850 mV VILD Differential Input LOW Voltage −300 VIHD – 150 mV VID Differential Input Voltage (VIHD − VILD) 150 1300 mV GND + 0.5 VDD – 850 mV 150 mA VIHCMR Input Common Mode Voltage Range (Differential Configuration) (Note 10) (Figure 7) IIH Input HIGH Current, VDD = VIN = 3.63 V IIL Input LOW Current, VDD = 3.63 V, VIN = 0 V CLK, CLK CLK CLK mA −5 −150 LVCMOS – OE Control Inputs VIH Input HIGH Voltage 2.0 VDD + 0.3 V VIL Input LOW Voltage −0.3 0.8 V IIH Input HIGH Current, VDD = VIN = 3.63 V 5 mA IIL Input LOW Current, VDD = 3.63 V, VIN = 0 V −150 mA Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. Input pins open and output pins loaded with RL=100 W across differential. 5. LVDS outputs require 100 W receiver termination resistor between diff. pair. See Figure 14. 6. VOS max + ½ VOD max. Also see Figures 12 and 13. 7. VOS min − ½ VOD max. Also see Figures 12 and 13. 8. VIH, VIL, Vth, and VISE parameters must be complied with simultaneously. 9. Vth is applied to the complementary input when operating in single−ended mode. 10. VIHCMR max varies 1:1 with VDD, VIHCMR min varies 1:1 with GND. 11. VIHD, VILD, VID and VIHCMR parameters must be complied with simultaneously. www.onsemi.com 4 NB3L8504S Table 6. AC CHARACTERISTICS VDD = 2.5 V ± 5% or 3.3 V ± 10%; GND = 0 V; TA = −40°C to 85°C (Note 12) (Figure 10) Symbol fMAX VOUTPP tpd tjit(f) Characteristic Input Clock Frequency Min Typ VOUTPP ≥ 250 mV @ VINPPmax Output Voltage Amplitude (@ VINPPmin) fin ≤ 700 MHz (See Figure 3) 250 Differential Input to Differential Output Propagation Delay at fMAX @ VDD = 3.3 V 0.9 Additive Phase Jitter RMS (Figure 4) Integration Range:12 kHz − 20 MHz fout = 156.25 MHz fout = 100 MHz Max Unit 700 MHz 350 0.07 0.10 mV 1.3 ns 0.08 0.105 ps tSKEW(o−o) Output−to−output Skew (Note 14) (Figure 8) 50 ps TSKEW(pp) Part−to−part Skew (Note 14) 350 ps tr / tf Output Rise/Fall Times @ 50 MHz, 20% − 80% 180 350 660 ps tDC Output Clock Duty Cycle (Input Duty Cycle = 50%) 45 50 55 % Input Voltage Swing (Differential Configuration) (Note 13) 150 1300 mV VINPP Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 12. Measured by forcing a 50% duty cycle clock source. All LVDS output loading with an external RL = 100 W across Q & Q. 13. VINPP(max) cannot exceed VDD. Input voltage swing is a single−ended measurement operating in differential mode. 14. Skew is measured between outputs under identical transition at 50 MHz. Figure 3. Output Voltage Amplitude (VOUTPP) vs. Input Clock Frequency (fin) and Temperature (@ VDD = 2.5 V) www.onsemi.com 5 NB3L8504S Figure 4. Additive Phase Jitter VDD VIHCMRmax VIHDmax VILDmax IN VIHCMR IN VIHCMRmin Figure 5. Differential Inputs Driven Differentially VID = VIHD - VILD VIHDtyp VILDtyp VIHDmin VILDmin GND Figure 7. VIHCMR Diagram Figure 6. Differential Inputs Driven Differentially Figure 8. Output−to−Output Skew www.onsemi.com 6 NB3L8504S Figure 9. LVDS Output Figure 10. AC Reference Measurements Figure 12. VOD and DVOD Figure 11. LVDS Output Figure 13. VOS and DVOS LVDS Driver Device Q Zo = 50 W D 100 W Q Zo = 50 W LVDS Receiver Device D Figure 14. Typical LVDS Termination for Output Driver and Device Evaluation www.onsemi.com 7 NB3L8504S 2.05 ± 0.165 V SCOPE Qx VDD Zo = 50 W 50 W LVDS Qx Zo = 50 W GND 50 W −1.25 V Figure 15. Typical Test Setup and Termination for Evaluation. The VDD = 2.05 V +0.165 V and GND of −1.25 Split Supply Allows a Direct Connection to an Oscilloscope 50 W Input Module VDD = +3.3 V VDD = +3.3 V R1 127 Q VDD = +3.3 V 2.5 V R3 127 VDD = +3.3 V VDD = +3.3 V R1 120 Q Zo = 50 W R3 120 Zo = 50 W LVPECL LVDS SSTL LVDS Zo = 50 W Zo = 50 W Q Q R2 83 R4 83 R2 120 R4 120 SSTL to LVDS LVPECL to LVDS VDD = +3.3 V VDD = +3.3 V 2.5 V VDD = +3.3 V Q Q Zo = 50 W Zo = 50 W R1 100 LVDS Zo = 50 W LVDS LVDS HSTL Zo = 50 W Q Q R2 50 LVDS to LVDS R4 50 HSTL to LVDS VDD = +3.3 V VDD = +3.3 V R1 50 Q VDD = +3.3 V VDD = +3.3 V 2.5 V R3 50 Q RS 33 Zo = 50 W CML Zo = 50 W LVDS HSTL LVDS Zo = 50 W Zo = 50 W Q Q CML to LVDS RS 33 R2 50 R4 50 HCSL to LVDS Figure 16. Differential Input Interface from LVPECL, CML, LVDS, HSTL, SSTL or HCSL www.onsemi.com 8 NB3L8504S VDD R1 1k CLK CLK Vref C1 0.1 mF R2 1k GND Figure 17. Differential Input Driven Single−ended Differential Clock Input to Accept Single−ended Input as a bypass capacitor. Locate these components close the device pins. R1 and R2 must be adjusted to position Vref to the center of the input swing on CLK. Figure 17 shows how the CLK input can be driven by a single−ended Clock signal. C1 is connected to the Vref node Table 7. ORDERING INFORMATION Device Package Shipping NB3L8504SDTG TSSOP−16 (Pb−Free) 96 Units / Tube NB3L8504SDTR2G TSSOP−16 (Pb−Free) 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 9 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSSOP−16 CASE 948F−01 ISSUE B 16 DATE 19 OCT 2006 1 SCALE 2:1 16X K REF 0.10 (0.004) 0.15 (0.006) T U M T U S V S K S ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ K1 2X L/2 16 9 J1 B −U− L SECTION N−N J PIN 1 IDENT. N 8 1 0.25 (0.010) M 0.15 (0.006) T U S A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. N F DETAIL E −W− C 0.10 (0.004) −T− SEATING PLANE D H G DETAIL E DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT 7.06 16 XXXX XXXX ALYW 1 1 0.65 PITCH 16X 0.36 DOCUMENT NUMBER: DESCRIPTION: 16X 1.26 98ASH70247A TSSOP−16 DIMENSIONS: MILLIMETERS XXXX A L Y W G or G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Electronic versions are uncontrolled except when accessed directly from the Document Repository. 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