NB3N2302DG

NB3N2302 3.3V / 5V 5MHz to 133MHz Frequency Multiplier and Zero Delay Buffer Description http://onsemi.com The NB3N2302 is a versatile Zero Delay Buffer that operates from 5 MHz to 133 MHz with a 3.3 V or 5 V power supply. It accepts a reference input and drives a B1 and a B2 clock output. The NB3N2302 has an on−chip PLL which locks to the input reference clock presented on the REF_IN pin. The PLL feedback is required to be driven to the FBIN pin and can be obtained by connecting either the OUT1 or OUT2 pin to the FBIN pin. The Function Select inputs control the various multiplier output frequency combinations as shown in Table 1. MARKING DIAGRAM 8 SOIC−8 D SUFFIX CASE 751 2302 A L Y W G Features • • • • • • • • • • • 8 1 Output Frequency Range: 5 MHz to 133 MHz Two LVTTL/LVCMOS Outputs 65 ps Typical Jitter OUT2 115 ps Typical Jitter OUT1 25 ps Typical Output−to−Output Skew Operating Voltage Range: VDD = 3.3 V $5% or 5 V $10% Clock Multiplication of the Reference Input Frequency, See Table 1 for Options Packaged in 8−Pin SOIC −40°C to +85°C Ambient Operating Temperature Range Ideal for PCI−X and Networking Clocks These are Pb−Free Devices 1 3N2302 ALYWG G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. External feedback connection to OUT1 or OUT2, not both FBIN FS0 FS1 Select Input Decoding OUT1 REF_IN PLL ÷2 OUT2 Figure 1. Simplified Logic Diagram © Semiconductor Components Industries, LLC, 2011 October, 2011 − Rev. 1 1 Publication Order Number: NB3N2302/D NB3N2302 FBIN 1 8 OUT2 REF_IN 2 7 VDD GND 3 6 OUT1 FS0 4 5 FS1 Figure 2. NB3N2302 Package Pinout (Top View) 8−pin SOIC (150 mil) Table 1. CLOCK MULTIPLIER SELECT TABLE FBIN FS0 FS1 OUT1 OUT2 REF_IN Min (MHz) REF_IN Max (MHz) OUT1 0 0 2 x REF REF 5 66.5 OUT1 1 0 4 x REF 2 x REF 5 33.25 OUT1 0 1 REF REF / 2 10 133 OUT1 1 1 8 x REF 4 x REF 5 16.625 OUT2 0 0 4 x REF 2 x REF 5 33.25 OUT2 1 0 8 x REF 4 x REF 5 16.625 OUT2 0 1 2 x REF REF 5 66.5 OUT2 1 1 16 x REF 8 x REF 5 8.3125 Table 2. PIN DESCRIPTION Pin # Pin Name 1 FBIN LVCMOS/LVTTL Input Feedback Input: This input must be fed by one of the outputs (OUT1 or OUT2) to ensure proper functionality. If the trace between FBIN and the output pin being used for feedback is equal in length to the traces between the outputs and the signal destinations, then the signals received at the destinations are synchronized to the REF signal input (REF_IN). 2 REF_IN LVCMOS/LVTTL Input Reference Input: The output signals are synchronized to this signal. 3 GND Power 4 FS0 LVCMOS/LVTTL Input Function Select Input: Tie to VDD (HIGH, 1) or GND (LOW, 0) as desired per Table 1. 5 FS1 LVCMOS/LVTTL Input Function Select Input: Tie to VDD (HIGH, 1) or GND (LOW, 0) as desired per Table 1. 6 OUT1 LVCMOS/LVTTL Output Output 1: The frequency of the signal provided by this pin is determined by the feedback signal connected to FBIN, and the FS0:1 inputs (see Table 1). 7 VDD Power Positive supply voltage This pin should be bypassed with a 0.1 mF decoupling capacitor. Use ferrite beads to help reduce noise for optimal jitter performance. 8 OUT2 LVCMOS/LVTTL Output Output 2: The frequency of the signal provided by this pin is one−half of the frequency of OUT1. See Table 1. Type Description Negative supply voltage; Connect to ground, 0 V http://onsemi.com 2 NB3N2302 Table 3. ATTRIBUTES Characteristics ESD Protection Value Human Body Model Machine Model Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Oxygen Index Transistor Count > 2 kV > 200 V Level 1 UL 94 V−O @ 0.125 in 6910 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Table 4. MAXIMUM RATINGS Symbol VDD, VIN Parameter Condition 1 Voltage on any pin Condition 2 GND = 0 V Unit V 0 to +70 −40 to +85 °C TA Operating Temperature Range, Tstg Storage Temperature Range −65 to +150 °C TB Ambient Temperature under Bias –55 to +125 °C qJA Thermal Resistance (Junction−to−Ambient) 190 130 °C/W PD Power Dissipation 0.5 W qJC Thermal Resistance (Junction−to−Case) 42 °C/W 265 °C TSOL Commercial Industrial Rating –0.5 to +7.0 0 lfpm 500 lfpm (Note 2) Wave Solder Pb−Free SOIC−8 SOIC−8 SOIC−8 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power http://onsemi.com 3 NB3N2302 Table 5. DC CHARACTERISTICS VDD = 3.3 V ± 5% or 5 V ± 10%, GND = 0 V, TA = −40°C to +85°C Symbol Characteristic Min IDD Power Supply Current, 100 MHz, Unloaded Outputs VDD = 3.3 V $ 5% VDD = 5 V $ 10% VOH Output HIGH Voltage IOH = −12 mA VOL Output LOW Voltage IOL = 12 mA VIH Input HIGH Voltage VIL Input LOW Voltage IIH Input HIGH Current, VIN = VDD IIL Input LOW Current, VIN = 0 V Typ Max Unit 20 25 35 50 mA 2.4 V 0.4 2.0 VDD = 3.3 V $ 5% VDD = 5 V $ 10% V V 0.8 V 5 mA 5 5 mA −40 −80 Table 6. AC CHARACTERISTICS VDD = 3.3 V ± 5% or 5 V ± 10%, GND = 0 V, TA = −40°C to +85°C (Note 5) Symbol fIN fOUT Characteristic Min Input Frequency (Note 3) 5 Output Frequency, OUT1 15 pF load 10 tD Output Duty Cycle @ 1.4 V, 120 MHz, 50% duty cycle in, 15 pF load 40 tr/tf Output rise and fall times; 0.8 V to 2.0V, 15 pF load VDD = 3.3 V $ 5% VDD = 5 V $ 10% Typ 50 Max Unit 133 MHz 133 MHz 60 % 3.5 / 2.5 2.5 / 1.5 ns tINCLK tr/tf Input Clock rise and fall time (Note 4) 10 ns tLOCK PLL Lock Time, power supply stable 1.0 ms 300 300 ps tJC Cycle−to−cycle Jitter tDC Die “Fave Away” Out Time. 33 MHz reference input suddenly stopped (0 MHz). Number of cycles provided prior to output falling to < 16 MHz. 100 tpd Propagation Delay, (Note 10) −350 tskew 115 65 OUT1, fOUT > 30 MHz OUT2, fOUT > 30 MHz Output−to−output skew; (Note 6) Clock Cycles 25 350 ps 250 ps 3. Input frequency is limited by output frequency range and input to output frequency multiplication factor (which is determined by circuit configuration). See Table 1. 4. Longer input rise and fall time degrades skew and jitter performance. 5. All AC specifications are measured with a 50 W transmission line, load terminated with 50 W to 1.4 V. 6. Skew is measured at 1.4 V on rising edges, all outputs with equal loading. 7. Duty cycle is measured at 1.4 V. 8. 33 MHz reference input suddenly stopped (0 MHz). Number of cycles provided prior to output falling to < 16 MHz. 9. Duty Cycle measured at 120 MHz. For 133 MHz, degrades to 35/65 worst case. 10. While in lock, propagation delay is measured from REF_IN to OUT1 using < 1 in feedback trace, (See Figure 1). http://onsemi.com 4 NB3N2302 Overview Delay feature. This is explained further in the sections of this datasheet titled “How to Implement Zero Delay,” and “Inserting Other Devices in Feedback Path.” The NB3N2302 is a two−output zero delay buffer and frequency multiplier. It provides an external feedback path allowing maximum flexibility when implementing the Zero Figure 3. Schematic / Suggested Layout How to Implement Zero Delay Inserting Other Devices in Feedback Path Typically, Zero Delay Buffers (ZDBs) are used because a designer wants to provide multiple copies of a clock signal in phase with each other. The whole concept behind ZDBs is that the signals at the destination chips are all going HIGH at the same time as the input to the ZDB. In order to achieve this, layout must compensate for trace length between the ZDB and the target devices. The method of compensation is described as follows. External feedback is the trait that allows for this compensation. The PLL on the ZDB causes the feedback signal to be in phase with the reference signal. When laying out the board, match the trace lengths between the output being used for feedback and the FBIN input to the PLL. If it is desirable to either add a little delay, or slightly precede the input signal, this may also be implemented by either making the trace to the FBIN pin a little shorter or a little longer than the traces to the devices being clocked. Another nice feature available due to the external feedback is the ability to synchronize signals to the signal coming from some other device. This implementation can be applied to any device (ASIC, multiple output clock buffer/driver, etc.) that is put into the feedback path. Referring to Figure 4, if the traces between the ASIC/Buffer and the destination of the clock signal(s) are equal in length to the trace between the buffer and the FBIN pin, the signals at the destination(s) device is driven HIGH at the same time when the Reference clock provided to the ZDB goes HIGH. Synchronizing the other outputs of the ZDB to the outputs from the ASIC/Buffer is more complex however, as any propagation delay from the ZDB output to the ASIC/Buffer output must be accounted for. Reference Input Signal NB3N2302 Zero Delay Buffer ASIC / Buffer / Fanout Feedback Signal Figure 4. Output Buffer in the Feedback Path http://onsemi.com 5 NB3N2302 Phase Alignment supplied). If OUT2 is desired to be rising−edge aligned to the IN input’s rising edge, then connect the OUT2 (i.e., the lowest frequency output) to the FBIN pin. This set−up provides a consistent input−output phase relationship. In cases where OUT1 (i.e., the higher frequency output) is connected to FBIN input pin the output OUT2 rising edges may be either 0° or 180° phase aligned to the IN input waveform (as set randomly when the input and/or power is Figure 5. Switching Waveforms ORDERING INFORMATION Package Shipping† NB3N2302DG SOIC−8 (Pb−Free) 98 Units / Rail NB3N2302DR2G SOIC−8 (Pb−Free) 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 6 NB3N2302 PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK −X− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M J SOLDERING FOOTPRINT* S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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