NCL30002
Power Factor Corrected
Buck LED Driver
The NCL30002 is a switch mode power supply controller intended
for low to medium power single stage power factor (PF) corrected
LED Drivers. The device operates as a critical conduction mode
(CrM) buck controller to regulate LED current at a high power factor
for a specific line voltage range. The current limit threshold is tightly
trimmed allowing open loop control techniques to reduce parts count
while maintaining accurate current regulation and high power factor.
CrM operation is particularly suited for LED applications as very high
efficiency can be achieved even at low power levels. These are
important in LED lighting to comply with regulatory requirements and
meet overall system luminous efficacy requirements. In CrM, the
switching frequency will vary with line and load. Switching losses are
low as recovery losses in the output rectifier are negligible since the
current goes to zero prior to reactivating the main MOSFET switch.
The device features a programmable on time limiter, zero current
detect sense block, gate driver, trans−conductance error amplifier as
well as all PWM control circuitry and protection functions required to
implement a CrM switch mode power supply. Moreover, for high
efficiency, the device features low startup current enabling fast, low
loss charging of the VCC capacitor. The current sense protection
threshold has been set at 485 mV to minimize power dissipation in the
external sense resistor. To support the environmental operation range
of Solid State Lighting, the device is specified across a wide junction
temperature range of −40°C to 125°C.
MARKING
DIAGRAM
8
Very Low 24 mA Typical Startup Current
Cycle−by−Cycle Current Protection
Tightly Trimmed Low Current Sense Threshold of 485 mV ±2%
Low 2 mA Typical Operating Current
Source 500 mA / Sink 800 mA Totem Pole Gate Driver
Wide Operating Temperature Range
Enable Function and Overvoltage Protection
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
8
1
SOIC−8
D SUFFIX
CASE 751
A
L
Y
W
G
1
L0002
ALYW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
PIN CONNECTION
MFP
Comp
Ct
CS
VCC
DRV
GND
ZCD
(Top View)
ORDERING INFORMATION
Device
Features
•
•
•
•
•
•
•
•
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NCL30002DR2G
Package
Shipping†
SOIC−8 2500 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Typical Applications
• LED Driver Power Supplies
• LED Based Bulbs
• Commercial and Residential LED Fixtures
© Semiconductor Components Industries, LLC, 2012
March, 2012 − Rev. 0
1
Publication Order Number:
NCL30002/D
NCL30002
OVP
+
−
+
VOVP
UVP
−
+
+
VUVP
(Enable EA)
E/A −
+
MFP
gm
+
RMFP
VREF
Fault
COMP
VControl
VEAH
Clamp
mVDD
VDD
Power Good
VDD
PWM
270 mA*
−
+
Add Ct
Offset
Ct
S Q
DRV
CS
VCC
VCC
Management
LEB
195 ns*
+
OCP
R Q
−
+
VCC
VILIM
+
ZCD
+
S Q
−
VZCD(ARM)
+
+
−
VZCD(TRIG)
Demag
R Q
R Q
Reset
mVDD
180 ms*
S Q
Off Timer
R Q
ZCD
Clamp
* Typical Values Shown
DRV
S Q
All SR Latches are Reset Dominant
Figure 1. Block Diagram
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GND
NCL30002
Table 1. PIN FUNCTION DESCRIPTION
Pin
Name
Function
1
MFP
The multi−function pin is connected to the internal error amplifier. By pulling this pin below the Vuvp threshold, the
controller is disabled. In addition, this pin also has an over voltage comparator which will disable the controller in the
event of a fault.
2
COMP
The COMP pin is the output of the internal error amplifier. A compensation network connected between this pin and
ground sets the loop bandwidth.
3
Ct
The Ct pin sources a regulated current to charge an external timing capacitor. The PWM circuit controls the power
switch on time by comparing the Ct voltage to an internal voltage derived from VControl. The CT pin discharges the
external timing capacitor at the end of the on time cycle.
4
CS
The CS input threshold is precisely trimmed to accurately sense the instantaneous switch current in the external
MOSFET. This signal is conditioned by an internal leading edge blanking circuit. The current limit threshold is tightly
trimmed for precise peak current control.
5
ZCD
The voltage of an auxiliary zero current detection winding is sensed at this pin. When the ZCD control block circuit
detects that the winding current has gone to zero, a control signal is sent to the gate drive block to turn on the
external MOSFET.
6
GND
This is the analog ground for the device. All bypassing components should be connected to the GND pin with a short
trace length.
7
DRV
The high current capability of the totem pole gate drive (+0.5/−0.8 A) makes it suitable to effectively drive high gate
charge power MOSFETs. The driver stage provides both passive and active pull down circuits that force the output to
a voltage less than the turn−on threshold voltage of the power MOSFET when VCC(on) is not reached.
8
VCC
This pin is the positive supply of the controller. The circuit starts to operate when VCC exceeds VCC(on), nominally
12 V and turns off when VCC goes below VCC(off), typically 9.5 V. After startup, the operating range is 10.2 V up to
20 V.
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NCL30002
AC1
F1
EMI Filter/ Rectifier / Surge Suppression
Lemi1
L4
AC1
RV1
MOV
+
AC2
D4
AC2
Start−up Resistors HVDC Filter Caps
Output Filter Cap
LED +
C6
C4
Rstart
−
Dbuck
Dovp
Cout
OVP Zener
LED −
Lemi2
Dvcc
Lout
R15
Rtop
Rin
1
2
3
4
Rfb
U1
MFP Vcc
Comp DRV
CT
GND
CS
ZCD
Cvcc
8
7
6
5
Rzcd
NCL30002
Cfilter
Rbottom
Ccomp
Vcc Bootstrap
Rgdrv
ZCD
Ct
Current Sense
R8
R2 (Optional)
Feed Forward Compensation
Qbuck
Rsense
On Time Capacitor
Figure 2. Simplified PFC Buck Application
Overview
Buck switching on the low side eliminates a floating gate
drive but references the LED to the HV rail. Buck converters
only produce output when the input voltage exceeds the load
voltage. Consequently, the input current goes to zero near
the zero crossing of the line. The exact phase angle of this
event depends on the LED string voltage and the line
voltage. Unlike the boost PFC, the buck PFC has increased
distortion near the zero crossing. However even with cross
over distortion, high power factor and acceptable harmonics
can be achieved.
Figure 2 illustrates the basic NCL30002 architecture for
a non-isolated low power high power factor LED driver. One
of the notable features of this architecture is the open loop
control. Notice that there is no direct measurement of the
LED current. Tight peak current control coupled with line
feed-forward compensation to vary the on-time allows for
accurate LED drive current. Fortunately in the vast majority
of LED bulb and luminaire applications, the LED forward
voltage range is well bounded and the line voltage may be
limited to one operating range. This is a huge advantage
which makes the simplicity of open loop control possible.
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NCL30002
Table 2. MAXIMUM RATINGS
Symbol
Value
Unit
MFP Voltage
Rating
VMFP
−0.3 to 10
V
MFP Current
IMFP
±10
mA
COMP Voltage
VControl
−0.3 to 6.5
V
COMP Current
IControl
−2 to 10
mA
Ct Voltage
VCt
−0.3 to 6
V
Ct Current
ICt
±10
mA
CS Voltage
VCS
−0.3 to 6
V
CS Current
ICS
±10
mA
ZCD Voltage
VZCD
−0.3 to 10
V
ZCD Current
IZCD
±10
mA
DRV Voltage
VDRV
−0.3 to VCC
V
IDRV(sink)
800
mA
IDRV(source)
500
mA
VCC
−0.3 to 20
V
ICC
±20
mA
PD
450
mW
RqJA
RqJA
RqJA
178
168
127
TJ
−40 to 125
°C
TJ(MAX)
150
°C
TSTG
−65 to 150
°C
TL
300
°C
DRV Sink Current
DRV Source Current
Supply Voltage
Supply Current
Power Dissipation (TA = 70°C, 2.0 Oz Cu, 55
mm2
Printed Circuit Copper Clad)
Thermal Resistance Junction−to−Ambient
(2.0 Oz Cu, 55 mm2 Printed Circuit Copper Clad)
Junction−to−Air, Low conductivity PCB (Note 3)
Junction−to−Air, High conductivity PCB (Note 4)
Operating Junction Temperature Range
Maximum Junction Temperature
Storage Temperature Range
Lead Temperature (Soldering, 10 s)
°C/W
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device series contains ESD protection and exceeds the following tests:
Pins 1– 8: Human Body Model 2000 V per JEDEC Standard JESD22−A114E.
Pins 1– 8: Machine Model Method 200 V per JEDEC Standard JESD22−A115−A.
2. This device contains Latch−Up protection and exceeds ± 100 mA per JEDEC Standard JESD78.
3. As mounted on a 40x40x1.5 mm FR4 substrate with a single layer of 80 mm2 of 2 oz copper traces and heat spreading area. As specified
for a JEDEC 51 low conductivity test PCB. Test conditions were under natural convection or zero air flow.
4. As mounted on a 40 x 40 x 1.5 mm FR4 substrate with a single layer of 650 mm2 of 2 oz copper traces and heat spreading area. As specified
for a JEDEC 51 high conductivity test PCB. Test conditions were under natural convection or zero air flow.
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NCL30002
Table 3. ELECTRICAL CHARACTERISTICS
VMFP = 2.4 V, VControl = 4 V, Ct = 1 nF, VCS = 0 V, VZCD = 0 V, CDRV = 1 nF, VCC = 12 V, unless otherwise specified
(For typical values, TJ = 25°C. For min/max values, TJ = −40°C to 125°C, unless otherwise specified)
Characteristic
Test Conditions
Symbol
Min
Typ
Max
Unit
Startup Voltage Threshold
VCC Increasing
VCC(on)
11
12
12.5
V
Minimum Operating Voltage
VCC Decreasing
VCC(off)
8.8
9.5
10.2
V
HUVLO
2.2
2.5
2.8
V
0 V < VCC < VCC(on) − 200 mV
Icc(startup)
−
24
35
mA
CDRV = open, 70 kHz Switching,
VCS = 2 V
Icc1
−
1.4
1.7
mA
70 kHz Switching, VCS = 2 V
Icc2
−
2.1
2.6
mA
No Switching, VMFP = 0 V
Icc(fault)
−
0.75
0.95
mA
STARTUP AND SUPPLY CIRCUITS
Supply Voltage Hysteresis
Startup Current Consumption
No Load Switching
Current Consumption
Switching Current Consumption
Fault Condition Current Consumption
OVERVOLTAGE AND UNDERVOLTAGE PROTECTION
Overvoltage Detect Threshold
VMFP = Increasing
Overvoltage Hysteresis
VOVP
2.5
2.67
2.85
V
VOVP(HYS)
20
60
100
mV
Overvoltage Detect Threshold
Propagation Delay
VMFP = 1 V to 3 V step,
VMFP = VOVP to VDRV = 10%
tOVP
−
500
800
ns
Undervoltage Detect Threshold
VMFP = Decreasing
VUVP
0.25
0.31
0.4
V
Undervoltage Detect Threshold
Propagation Delay
VMFP = 2 V to 0 V step,
VMFP = VUVP to VDRV = 10%
tUVP
80
200
320
ns
TJ = 25°C
TJ = −40°C to 125°C
VREF
2.397
2.359
2.510
2.510
2.623
2.661
V
VCC(on) + 200 mV < VCC < 20 V
VREF(line)
−10
−
10
mV
Error Amplifier Current Capability
VMFP = VREF + 0.11 V
VMFP = 1.08*VREF
VMFP = 0.5 V
IEA(sink)
IEA(sink)OVP
IEA(source)
6
10
−110
10
20
−210
20
30
−250
mA
Transconductance
VMFP = VREF ± 100 mV
TJ = 25°C
TJ = −40°C to 125°C
gm
90
70
110
110
120
135
VMFP = VUVP to VREF
RMFP
2
4.6
10
MW
VMFP = 2.5 V
IMFP
0.25
0.54
1.25
mA
VMFP = 0 V
IControl
−1
−
1
mA
IControl(pullup) = 10 mA,
VMFP = VREF
VEAH
5
5.5
6
V
VControl = Decreasing until
VDRV is low, VCt = 0 V
Ct(offset)
0.37
0.65
0.88
V
VEAH – Ct(offset)
VEA(DIFF)
4.5
4.9
5.3
V
ERROR AMPLIFIER
Voltage Reference
Voltage Reference Line Regulation
Feedback Pin Internal Pull−Down
Resistor
Feedback Bias Current
Control Bias Current
Maximum Control Voltage
Minimum Control Voltage to Generate
Drive Pulses
Control Voltage Range
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mS
NCL30002
Table 3. ELECTRICAL CHARACTERISTICS (Continued)
VMFP = 2.4 V, VControl = 4 V, Ct = 1 nF, VCS = 0 V, VZCD = 0 V, CDRV = 1 nF, VCC = 12 V, unless otherwise specified
(For typical values, TJ = 25°C. For min/max values, TJ = −40°C to 125°C, unless otherwise specified)
Characteristic
Test Conditions
Symbol
Min
Typ
Max
Unit
VCOMP = open
VCt(MAX)
4.535
4.93
5.25
V
VCOMP = open
VCt = 0 V to VCt(MAX)
Icharge
240
270
292
mA
VCOMP = open
VCt = VCt(MAX) −100 mV to 500 mV
tCt(discharge)
−
50
150
ns
dV/dt = 30 V/ms
VCt = VControl − Ct(offset)
to VDRV = 10%
tPWM
−
130
220
ns
ZCD Arming Threshold
VZCD = Increasing
VZCD(ARM)
1.25
1.4
1.55
V
ZCD Triggering Threshold
VZCD = Decreasing
VZCD(TRIG)
0.6
0.7
0.83
V
VZCD(HYS)
500
700
900
mV
RAMP CONTROL
Ct Peak Voltage
On Time Capacitor Charge Current
Ct Capacitor Discharge Duration
PWM Propagation Delay
ZERO CURRENT DETECTION
ZCD Hysteresis
ZCD Bias Current
VZCD = 5 V
IZCD
−2
−
+2
mA
Positive Clamp Voltage
IZCD = 3 mA
VCL(POS)
9.8
10
12
V
Negative Clamp Voltage
IZCD = −2 mA
VCL(NEG)
−0.9
−0.7
−0.5
V
ZCD Propagation Delay
VZCD = 2 V to 0 V ramp,
dV/dt = 20 V/ms
VZCD = VZCD(TRIG) to VDRV = 90%
tZCD
−
100
170
ns
Minimum ZCD Pulse Width
tSYNC
−
70
−
ns
Falling VDRV = 10% to
Rising VDRV = 90%
tstart
75
165
300
ms
Isource = 100 mA
Isink = 100 mA
ROH
ROL
−
−
12
6
20
13
W
Rise Time
10% to 90%
trise
−
35
80
ns
Fall Time
90% to 10%
tfall
−
25
70
ns
VCC = VCC(on)−200 mV,
Isink = 10 mA
Vout(start)
−
−
0.2
V
Current Sense Voltage Threshold
TJ = 25°C
TJ = −40°C to 125°C
VILIM
0.475
0.470
0.485
0.485
0.495
0.500
V
Leading Edge Blanking Duration
VCS = 2 V, VDRV = 90% to 10%
tLEB
100
195
350
ns
dV/dt = 10 V/ms
VCS = VILIM to VDRV = 10%
tCS
40
100
170
ns
VCS = 2 V
ICS
−1
−
1
mA
Maximum Off Time in Absence of ZCD
Transition
DRIVE
Drive Resistance
Drive Low Voltage
CURRENT SENSE
Overcurrent Detection Propagation
Delay
Current Sense Bias Current
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NCL30002
TYPICAL CHARACTERISTICS
2.75
2.70
2.65
2.60
2.55
2.50
−50
VUVP, UNDERVOLTAGE DETECT THRESHOLD (V)
VOVP(HYS), OVERVOLTAGE HYSTERESIS (mV)
2.80
−25
0
25
50
75
100
125
80
70
60
50
40
−50
−25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 3. Overvoltage Detect Threshold vs.
Junction Temperature
Figure 4. Overvoltage Hysteresis vs. Junction
Temperature
0.325
0.320
0.315
0.310
0.305
0.300
−50
−25
0
25
50
75
100
125
RMFP, FEEDBACK PIN INTERNAL PULL−
DOWN RESISTOR (MW)
VOVP, OVERVOLTAGE DETECT
THRESHOLD (V)
2.85
7
6
5
4
3
2
1
0
−50
−25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. Undervoltage Detect Threshold vs.
Junction Temperature
Figure 6. MFP Pin Internal Pull−Down Resistor
vs. Junction Temperature
VREF, REFERENCE VOLTAGE (V)
2.54
2.53
2.52
2.51
2.50
2.49
2.48
2.47
2.46
−50
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
Figure 7. Reference Voltage vs. Junction
Temperature
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NCL30002
TYPICAL CHARACTERISTICS
220
18
16
14
12
10
8
−25
0
25
50
75
100
205
200
195
190
VMFP = 0.5 V
185
−25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 8. Error Amplifier Sink Current vs.
Junction Temperature
Figure 9. Error Amplifier Source Current vs.
Junction Temperature
120
115
110
105
100
95
90
−25
0
25
50
75
100
200
TJ, JUNCTION TEMPERATURE (°C)
200
180
180
Phase
160
160
140
140
120
120
Transconductance
100
125
Figure 10. Error Amplifier Transconductance
vs. Junction Temperature
100
80
60
40
20
0
80
RControl = 100 kW
CControl = 2 pF
VMFP = 2.5 Vdc, 1 Vac
VCC = 12 V
TA = 25°C
0.01
0.1
60
40
1
10
20
0
1000
100
f, FREQUENCY (kHz)
Figure 11. Error Amplifier Transconductance
and Phase vs. Frequency
290
Icharge, Ct CHARGE CURRENT (mA)
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
−50
210
180
−50
125
125
85
−50
215
q, PHASE (DEGREES)
gm, ERROR AMPLIFIER TRANSCONDUCTANCE (mS)
6
−50
Ct(offset), MINIMUM CONTROL VOLTAGE
TO GENERATE DRIVE PULSES (V)
IEA(source), ERROR AMPLIFIER
SOURCE CURRENT (mA)
VMFP = VREF + 0.11 V
gm, ERROR AMPLIFIER TRANSCONDUCTANCE (mS)
IEA(sink), ERROR AMPLIFIER SINK
CURRENT (mA)
20
−25
0
25
50
75
100
125
285
280
275
270
265
260
255
250
245
240
−50
TJ, JUNCTION TEMPERATURE (°C)
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
Figure 12. Minimum Control Voltage to Generate
Drive Pulses vs. Junction Temperature
Figure 13. On Time Capacitor Charge Current
vs. Junction Temperature
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125
NCL30002
TYPICAL CHARACTERISTICS
5.5
5.0
4.5
4.0
−50
−25
0
25
50
75
100
125
170
160
150
140
130
120
110
100
−50
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 14. Ct Peak Voltage vs. Junction
Temperature
Figure 15. PWM Propagation Delay vs.
Junction Temperature
500
125
220
tLEB, LEADING EDGE BLANKING
DURATION (ns)
497
494
491
488
485
482
479
476
473
470
−50
−25
0
25
50
75
100
210
200
190
180
−50
125
−25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 16. Current Sense Voltage Threshold
vs. Junction Temperature
Figure 17. Leading Edge Blanking Duration vs.
Junction Temperature
205
18
200
16
DRIVE RESISTANCE (W)
tstart, MAXIMUM OFF TIME IN ABSENCE OF ZCD TRANSITION (ms)
VILIM, CURRENT SENSE VOLTAGE THRESHOLD (mV)
tPWM, PWM PROPAGATION DELAY (ns)
VCt(MAX), Ct PEAK VOLTAGE (V)
6.0
195
190
185
180
175
170
ROH
14
12
10
8
6
ROL
4
2
165
−50
−25
0
25
50
75
100
125
0
−50
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 18. Maximum Off Time in Absence of
ZCD Transition vs. Junction Temperature
Figure 19. Drive Resistance vs. Junction
Temperature
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NCL30002
TYPICAL CHARACTERISTICS
ICC(startup), STARTUP CURRENT
CONSUMPTION (mA)
26
VCC(on)
12
11
10
VCC(off)
9
8
−50
−25
0
25
50
75
100
24
22
20
18
16
14
−50
125
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 20. Supply Voltage Thresholds vs.
Junction Temperature
Figure 21. Startup Current Consumption vs.
Junction Temperature
2.16
ICC2, SWITCHING CURRENT CONSUMPTION (mA)
VCC, SUPPLY VOLTAGE
THRESHOLDS (V)
13
2.14
2.12
2.10
2.08
2.06
2.04
2.02
2.00
−50
−25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
Figure 22. Switching Current Consumption vs.
Junction Temperature
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125
NCL30002
THEORY OF OPERATION
power factor is 0.7. So a certain amount of distortion can be
accepted while maintaining high power factor. This buck
topology meets the requirements for PF greater than 0.9 and
regulate LED current in a single power stage. Unlike the
boost converter, the NCL30002 buck controller operates in
several different modes over the line cycle.
High power factor, high efficiency, and small size are key
parameters for LED drivers in the incandescent replacement
market. The NCL30002 has all the features required to
accomplish that is in a compact SOIC-8 package. Power
factor is broadly defined as:
PF +
P in(avg)
V in(rms) I in(rms)
Buck Modes
This differs from the classical definition where there is a
phase angle difference between the input voltage and
current. However, the underlying concept of optimizing
power delivery by minimizing line current is the same.
Ideally, current would be directly proportional to the voltage
which is the case when the load is a resistor. Offline power
converters are active devices which are not purely resistive,
capacitive, or inductive often drawing distorted current
waveforms from the power lines. This distortion reduces
power factor by increasing input RMS current.
Preregulators using boost converters are the most common
method to correcting the distortion and making the offline
power supply appear to be a resistor as far as the power line
is concerned. Their performance is excellent achieving
power factor greater than 0.99. Regrettably, this two stage
approach negatively impacts efficiency and board area.
Fortunately, power factors greater than 0.9 are acceptable in
the general lighting market and in some applications like US
Energystart Integral LED bulbs, the minimum acceptable
1. “Zero” Input Current (Iin=0) - Buck converters
cannot deliver power when Vin is less than Vout.
The “dead time” where no current flows around
the zero crossing is dependent on the line voltage
and the load voltage.
2. Constant On-Time (Ton = constant) - This is the
same as the boost converter. Constant Ton forces
the peak current to be proportional to the input
voltage which is key to improved PF.
3. Constant Peak Current (Ipeak = constant) – The
NCL30002 limits the peak inductor and thus the
LED current. In this region, the unique nature of
the CrM buck means that the average output
current is equal to half the peak current. Also the
off time is fixed is this mode since the peak current
and the output voltage are virtually constant.
In the example below (Figure 23) in spite of the distortion,
the power factor is 0.97. The corresponding pre-filtered
output current is shown in Figure 24.
Mode 3 Ipeak = Constant
Mode 2 ton = Constant
Mode 1 Input Current = 0
Figure 23. Theoretical Average Input Current over one half line cycle (conduction angle)
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12
NCL30002
Mode 3 Ipeak = Constant
Mode 2 ton = Constant
Mode 1 Input Current = 0
Figure 24. Theoretical Average Output Current over one half line cycle (conduction angle)
On Time Control
An output capacitor filters the output current in the LED
string. The dynamic LED resistance, line frequency, and the
size of the filter capacitance determine the exact LED ripple.
The NCL30002 operates as a CrM controller. The
controller draws very low currents while the Vcc filter
capacitor charges to the start-up threshold. Since CrM
operation is not clocked at a fixed frequency and depends on
the state of the power circuit to initiate a new switching
cycle, a kick start timer turns on the gate driver to start a new
cycle. The kick start timer will do this anytime the driver is
off for more than about 180 msec as long as none of the
protection circuits are disabling the gate driver output.
The NCL30002 (refer to the block diagram − Figure 1) is
composed of 4 key functional blocks along with protection
circuitry to ensure reliable operation of the controller.
• On−Time Control
• Zero Current Detection Control
• MOSFET Gate Driver
• Startup and VCC Management
The on−time control circuitry (Figure 25) consists of a
precision current source which charges up an external
capacitor (Ct) in a linear ramp. The voltage on Ct (after
removing an internal offset) is compared to an external
control voltage and the output of the comparator is used to
turn off the output driver thus terminating the switching
cycle. A signal from the driver is fed back to the on−time
control block to discharge the Ct capacitor thus preparing the
circuit for the start of the next switching cycle.
The state of Vcontrol is determined by the external
regulation loop. The range of on−time is determined by the
charging slope of the Ct capacitor and is clamped at 4.93 V
nominal. The Ct capacitor is sized to ensure that the required
on−time is reached at maximum output power and the
minimum input line voltage condition.
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13
NCL30002
VControl
MOSFET Conduction
COMP
VDD
VEAH
Output Rectifier Conduction
PWM
Icharge
Ct
+
−
+
ton
Iprimary
0A
Isecondary
0A
DRV
Ct(offset)
VCt
VCt(off)
VControl − Ct(offset)
VControl
ton(max)
DRV
DRV
Figure 25. On Time Control
0V
Off Time Sequence
Vout
The off time is determined by the peak inductor current,
the inductance and the output voltage. In mode 2, the off time
is variable because the peak inductor current is not fixed.
However in mode 3, the off time is constant since the peak
current and the output voltage are both fixed. The auxiliary
winding used to provide bias to the NCL30002 is also used
to detect when the current has dropped to zero. This is
illustrated in Figure 26.
0V
VZCD(WIND)
VZCD(WIND),off
0V
VZCD(WIND),on
VCL(POS)
VZCD(ARM)
VZCD(TRIG)
0V
VCL(NEG)
ton
tdiode
toff
tSW
Figure 26. Ideal CrM Waveforms with ZCD Winding
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14
NCL30002
ZCD Detection Block
the ZCD input has a dual comparator input structure to arm
the latch when the ZCD detect voltage rises above 1.4 V
(nominal) thus setting the latch. When the voltage on ZCD
falls below 0.7 V (nominal) a zero current event is detected
and a signal is asserted which initiates the next switching
cycle. This is illustrated in Figure 27. The input of the ZCD
has an internal circuit which clamps the positive and
negative voltage excursions on this pin. The current into or
out of the ZCD pin must be limited to ±10 mA with an
external resistor.
A dedicated circuit block is necessary to implement the
zero current detection. The NCL30002 provides a separate
input pin to signal the controller to turn the power switch
back on just after inductor current reaches zero. When the
output winding current reaches zero the winding voltage
will reverse. Since all windings of the inductor reflect the
same voltage characteristic this voltage reversal appears on
the bias winding. Coupling the winding voltage to the ZCD
input of the NCL30002 allows the controller to start the next
switching cycle at the precise time. To avoid false triggering,
Varm
NZCD
Vtrig
+
−
S
VZCD(ARM)
+
+
−
Q
Reset
Dominant
Latch
R
Q
DRIVE
Demag
VZCD(TRIG)
+
ZCD
Bias Winding Voltage
RZCD
ZCD Clamp
Figure 27. ZCD Operation
At startup, there is no energy in the ZCD winding and no
voltage signal to activate the ZCD comparators. To enable
the controller to start under these conditions, an internal
watchdog timer is provided which initiates a switching cycle
in the event that the output drive has been off for more than
180 ms (nominal).
The timer is deactivated only under an OVP or UVP fault
condition which will be discussed in the next section.
OCP
VILIM
optional
Figure 28. CS Circuitry with Optional
External RC Filter
The dedicated CS pin of the NCL30002 senses the current
through the MOSFET switch and the output inductor. If the
voltage of the CS pin exceeds VILIM, the internal comparator
will detect the event and turn off the MOSFET. The peak
switch current is calculated using Equation 1:
V ILIM
R sense
+
−
LEB
+
Rsense
CS
I SW(peak) +
CS
DRV
MFP Input
The multi−function pin connects to the inverting terminal
of the transconductance amplifier, the undervoltage and
overvoltage protection comparators. This allows this pin to
perform several functions. To place the device in standby,
the MFP pin should be pulled below the Vuvp threshold. This
is illustrated in Figure 29. Additionally, raising the MFP pin
above Vovp will also suspend switching activity but not place
the controller in the standby mode. This can be used
implement overvoltage monitoring on the bias winding and
add an additional layer of fault protection.
(eq. 1)
To avoid false detection, the NCL30002 incorporates
leading edge blanking circuit (LEB) which masks the CS
signal for a nominal time of 190 ns. If required, an optional
RC filter can be added between Rsense and CS to provide
additional filtering. This is illustrated below.
http://onsemi.com
15
NCL30002
+
VOVP
Bias
+
R1
OVP Fault
POWER GOOD
− UVP
+
UVP Fault
VUVP
MFP
−
+
RFB
R2
COMP
+
Shutdown
+ OVP
−
EA
(Enable EA)
gm
VREF
VControl
CCOMP
Figure 29. Multi−Function Pin Operation
Design Tool
The positive input of the transconductance amplifier is
connected to a 2.51 V (nominal) reference. A filtered line
feed-forward signal (see Figure 2) is connected to the
negative input of the error amplifier and used to control the
on-time of controller.
The NCL30002 implements a unique control method to
achieve high power and superior current regulation even
though the average current is not directly sensed. There are
a number of design tradeoffs that can be made between peak
switch current, inductor size, and desired power factor that
can impact the current regulation accuracy, efficiency, and
physical size. These tradeoffs can be made by adjusting the
amount of line feed forward applied, selecting the amount of
time where the controller is operating in mode 2 and 3, as
well as factoring in the LED forward voltage range. To
simplify the component selection process and allow the
designer to interactively make these tradeoffs,
ON Semiconductor has developed an EXCELt based
Design Guide which allows step-by-step analysis. This tool
is available at onsemi.com along with a supporting
application note that illustrates a complete design and
provides typical application performance.
VCC Management
The NCL30002 incorporates a supervisory circuitry to
manage the startup and shutdown of the circuit. By
managing the startup and keeping the initial startup current
at less than 35 mA, a startup resistor connected between the
rectified ac line and VCC charges the VCC capacitor to
VCC(on). Turn on of the device occurs when the startup
voltage has exceeded 12 V (nominal) when the internal
reference and switching logic are enabled. A UVLO
comparator with a hysteresis of 2.5 V nominal gives ample
time for the device to start switching and allow the bias from
the auxiliary winding to supply VCC.
http://onsemi.com
16
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
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