Dimmable Power Factor
Corrected LED Driver
NCL30486
The NCL30486 is a power factor corrected flyback controller
targeting isolated constant current LED drivers. The controller
operates in a quasi−resonant mode to provide high efficiency. Thanks
to a novel control method, the device is able to tightly regulate a
constant LED current from the primary side. This removes the need
for secondary side feedback circuitry, its biasing and for an
optocoupler.
The device is highly integrated with a minimum number of external
components. A robust suite of safety protection is built in to simplify
the design. This device is specifically intended for very compact space
efficient designs and supports analog and digital dimming with two
dedicated dimming inputs control ideal for Smart LED Lighting
applications.
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9
1
SOIC−9
CASE 751BP
MARKING
DIAGRAM
Features
•
•
•
•
•
•
•
•
•
•
•
•
9
High Voltage Startup
Quasi−resonant Peak Current−mode Control Operation
Primary Side Feedback
CC / CV Accurate Control Vin up to 320 V rms
Tight LED Constant Current Regulation of ±2% Typical
Digital Power Factor Correction
Analog and Digital Dimming
Cycle by Cycle Peak Current Limit
Wide Operating VCC Range
−40 to + 125°C
Robust Protection Features
♦ Brown−Out
♦ OVP on VCC
♦ Constant Voltage / LED Open Circuit Protection
♦ Winding Short Circuit Protection
♦ Secondary Diode Short Protection
♦ Output Short Circuit Protection
♦ Thermal Shutdown
♦ Line over Voltage Protection
This is a Pb−Free Device
L30486XX
ALYWX
G
1
L30486
XX
A
L
YW
G
= Specific Device Code
= Version
= Assembly Location
= Wafer Lot
= Assembly Start Week
= Pb−Free Package
PIN CONNECTIONS
Typical Applications
• Integral LED Bulbs
• LED Power Driver Supplies
• LED Light Engines
HV
ADIM
1
COMP
2
ZCD
3
8
PDIM
CS
4
7
VCC
GND
5
6
DRV
10
ORDERING INFORMATION
See detailed ordering and shipping information on page 27 of
this data sheet.
© Semiconductor Components Industries, LLC, 2020
May, 2021 − Rev. 2
1
Publication Order Number:
NCL30486/D
NCL30486
.
.
Aux
.
V ADIM
NCL30486
1
10
2
9
3
8
4
7
5
6
PWM signal
Figure 1. Typical Application Schematic for NCL30486
PIN FUNCTION DESCRIPTION NCL30486
Pin N5
Pin Name
Function
1
ADIM
Analog dimming
Pin Description
2
COMP
OTA output for CV loop
This pin receives a compensation network to stabilize the constant voltage loop
3
ZCD
Zero crossing Detection
Vaux sensing
This pin connects to the auxiliary winding and is used to detect the core reset event.
This pin also senses the auxiliary winding voltage for accurate output voltage control
4
CS
Current sense
5
GND
−
6
DRV
Driver output
7
VCC
Supplies the controller
8
PDIM
PWM dimming
9
NC
creepage
10
HV
High Voltage sensing
This pin is used for analog control of the output current. Applying a voltage varying
between VDIM(EN) and VDIM100 will dim the output current from 0% to 100%.
This pin monitors the primary peak current.
The controller ground
The driver’s output to an external MOSFET
This pin is connected to an external auxiliary voltage.
This pin is used for PWM dimming control. An optocoupler can be connected directly
to the pin if the PWM control signal is from the secondary side
This pin connects after the diode bridge to provide the startup current and internal
high voltage sensing function.
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2
NCL30486
INTERNAL CIRCUIT ARCHITECTURE
STOP
COMP
L_OVP
Aux_SCP
Fast_OVP
Enable
Standby
VCV
Constant Voltage
Control
Slow_OVP
VCC
Fault
Management
Thermal
Shutdown
Fast_OVP
CS_short
OFF
VCC Management
UVLO
VCC
OVP
VCC_OVP
VREFX VHVdiv Slow_OVP
dimCV_mode
BO_NOK
ZCD
Zero crossing detection Logic
(ZCD blanking, Time−Out, …)
Aux . Winding Short Circuit Prot
Line
feed −forward
CS
Leading
Edge
Blanking
HV
Startup
Q_drv
VHVdiv
Enable
STOP
Valley Selection
.
VHVdiv
VDIMA VHVdiv dc_DIM
Power factor and
Constant −current control
Max. Peak
Current Limit
Winding /
Output diode
SCP
L_OVP
S
Q
R
Q
Q_drv
Driver
and
Clamp
VREFX
DRV
CS_reset
Ipk_max
STOP
Maximum
on −time
WOD_SCP
VDIMA
dimCV_mode
CS Short
Protection
HV
Frequency foldback
Aux_SCP
Standby
Brown −Out
Line OVP
Analog
Dimming
ADIM
Enable
CS_short
GND
dc_DIM
dimCV_mode
Figure 2. Internal Circuit Architecture NCL30486
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3
PWM
Dimming
PDIM
NCL30486
MAXIMUM RATINGS TABLE
Symbol
VCC(MAX)
ICC(MAX)
Rating
Maximum Power Supply voltage, VCC pin, continuous voltage
Maximum current for VCC pin
VDRV(MAX) Maximum driver pin voltage, DRV pin, continuous voltage
IDRV(MAX) Maximum current for DRV pin
VHV(MAX)
IHV(MAX)
Value
Unit
−0.3 to 30
Internally limited
V
mA
−0.3, VDRV (Note 1)
−300, +500
V
mA
−0.3, +700
±20
V
mA
−0.3, 5.5 (Note 2)
−2, +5
V
mA
Maximum voltage on HV pin
Maximum current for HV pin (dc current self−limited if operated within the allowed range)
VMAX
IMAX
Maximum voltage on low power pins (except pins DRV and VCC)
Current range for low power pins (except pins DRV and VCC)
RθJ−A
Thermal Resistance Junction−to−Air
210
°C/W
Maximum Junction Temperature
150
°C
Operating Temperature Range
−40 to +125
°C
Storage Temperature Range
−60 to +150
°C
TJ(MAX)
ESD Capability, HBM model except HV pin (Note 3)
ESD Capability, HBM model HV pin
ESD Capability, CDM model (Note 3)
4
kV
1.5
kV
1
kV
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. VDRV is the DRV clamp voltage VDRV(high) when VCC is higher than VDRV(high). VDRV is VCC otherwise.
2. This level is low enough to guarantee not to exceed the internal ESD diode and 5.5 V ZENER diode. More positive and negative voltages
can be applied if the pin current stays within the −2 mA / 5 mA range.
3. This device series contains ESD protection and exceeds the following tests: Human Body Model 4000 V per Mil−Std−883, Method 3015.
Charged Device Model 1000 V per JEDEC Standard JESD22−C101D.
4. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.
ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V, VZCD = 0 V, VCS = 0 V)
For min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V)
Parameter
Test Condition
Symbol
Min
Typ
Max
Unit
HIGH VOLTAGE SECTION
High voltage current source
VCC = VCC(on) – 200 mV
IHV(start2)
3.9
5.1
6.2
mA
High voltage current source
VCC = 0 V
IHV(start1)
−
300
−
mA
VCC(TH)
−
0.8
−
V
−
17
−
V
VCC level for IHV(start1) to IHV(start2) transition
Minimum startup voltage
VCC = 0 V
VHV(MIN)
HV source leakage current
VHV = 450 V
IHV(leak)
−
4.5
10
mA
VHV(OL)
320
−
−
V rms
VCC(on)
VCC(off)
VCC(HYS)
VCC(reset)
16
9.3
7.6
4
18
10.2
−
5
20
10.7
−
6
Over Voltage Protection
VCC OVP threshold
VCC(OVP)
25
26.5
28
V
VCC(off) noise filter (Note 5)
VCC(reset) noise filter (Note 5)
tVCC(off)
tVCC(reset)
−
−
5
20
−
−
ms
ICC1
ICC2
ICC3
ICC4
1.2
–
−
−
1.35
3.0
3.5
1.7
1.6
3.5
4.0
1.88
Maximum input voltage (rms) for correct operation of
the PFC loop
SUPPLY SECTION
Supply Voltage
Startup Threshold
Minimum Operating Voltage
Hysteresis VCC(on) – VCC(off)
Internal logic reset
Supply Current
Device Disabled/Fault
Device Enabled/No output load on pin 5
Device Switching (Fsw = 65 kHz)
Device switching (Fsw = 700 Hz)
VCC increasing
VCC decreasing
VCC decreasing
VCC > VCC(off)
Fsw = 65 kHz
CDRV = 470 pF, Fsw = 65 kHz
VCOMP v 0.9 V
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V
mA
NCL30486
ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V, VZCD = 0 V, VCS = 0 V)
For min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V) (continued)
Parameter
Test Condition
Symbol
Min
Typ
Max
Unit
Maximum Internal current limit
VILIM
1.33
1.40
1.47
V
Leading Edge Blanking Duration for VILIM
tLEB
283
345
407
ns
Propagation delay from current detection to gate
off−state
tILIM
−
100
150
ns
Maximum on−time (option 1)
ton(MAX)
29
39
49
ms
Maximum on−time (option 2)
ton(MAX)
16
20
24
ms
Threshold for immediate fault protection activation
(140% of VILIM)
VCS(stop)
1.9
2.0
2.1
V
CURRENT SENSE
Leading Edge Blanking Duration for VCS(stop)
tBCS
−
170
−
ns
Current source for CS to GND short detection
ICS(short)
400
500
600
mA
VCS(low)
20
60
90
mV
Drive Resistance
DRV Sink
DRV Source
RSNK
RSRC
−
−
13
30
−
−
Drive current capability
DRV Sink (Note GBD)
DRV Source (Note GBD)
ISNK
ISRC
−
−
500
300
−
−
Current sense threshold for CS to GND short
detection
VCS rising
GATE DRIVE
W
mA
Rise Time (10% to 90%)
CDRV = 470 pF
tr
–
30
−
ns
Fall Time (90 %to 10%)
CDRV = 470 pF
tf
–
20
−
ns
DRV Low Voltage
VCC = VCC(off)+0.2 V
CDRV = 470 pF, RDRV = 33 kW
VDRV(low)
8
–
−
V
DRV High Voltage
VCC = VCC(MAX)
CDRV = 470 pF, RDRV = 33 kW
VDRV(high)
10
12
14
V
Upper ZCD threshold voltage
VZCD rising
VZCD(rising)
−
90
150
mV
Lower ZCD threshold voltage
VZCD falling
VZCD(falling)
35
55
−
mV
VZCD(start)
−
0.7
−
V
VZCD(HYS)
15
−
−
mV
tZCD(DEM)
−
−
150
ns
Additional delay from valley lockout output to DRV
latch set (prog option)
tLEB4
125
250
375
ns
Equivalent time constant for ZCD input (GBD)
tPAR
−
20
−
ns
ZERO VOLTAGE DETECTION CIRCUIT
Threshold to force VREFX maximum during startup
ZCD hysteresis
Propagation Delay from valley detection to DRV high
(no tLEB4)
VZCD decreasing
Blanking delay after on−time (option 1)
VREFX > 0.35 V
tZCD(blank1)
1.1
1.5
1.9
ms
Blanking delay after on−time (option 2)
VREFX > 0.35 V
tZCD(blank1)
0.75
1.0
1.25
ms
Blanking Delay at light load (option 1)
VREFX < 0.25 V
tZCD(blank2)
0.6
0.8
1.0
ms
Blanking Delay at light load (option 2)
VREFX < 0.25 V
tZCD(blank2)
0.45
0.6
0.75
ms
tTIMO
5
6.5
8
ms
Timeout after last DEMAG transition
Pulling−down resistor
VZCD = VZCD(falling)
RZCD(pd)
−
200
−
kW
ZCD pin current source for forcing CV mode when
minimum dimming
VADIM = 0.5 V
IZCDdim
145
170
195
mA
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NCL30486
ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V, VZCD = 0 V, VCS = 0 V)
For min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V) (continued)
Parameter
Test Condition
Symbol
Min
Typ
Max
Unit
CONSTANT CURRENT CONTROL
Reference Voltage
Tj = 25°C − 85°C
VREF/3
327.9
334.2
341.2
mV
Reference Voltage
Tj = −40°C to 125°C
VREF/3
324
334.2
346
mV
10% Reference Voltage
Tj = 25°C − 85°C
VREF10/3
30
33.33
36.66
mV
10% Reference Voltage
Tj = −40°C to 125°C
VREF10/3
27.33
33.33
39.33
mV
5% Reference Voltage
Tj = 25°C − 85°C
VREF05/3
14.17
17
19.17
mV
5% Reference Voltage
Tj = −40°C to 125°C
VREF05/3
13.34
17
20
mV
Current sense lower threshold for detection of the
leakage inductance reset time
VCS falling
VCS(low)
20
50
100
mV
tCS(low)
−
120
−
ns
Blanking time for leakage inductance reset detection
POWER FACTOR CORRECTION
Clamping value for VREF(PFC)
TJ = 0°C to 125°C
VREF(PFC)CLP
2.06
2.2
2.34
V
Line range detector for PFC loop
VHV increases
VHL(PFC)
−
240
−
Vdc
Line range detector for PFC loop
VHV decreases
VLL(PFC)
−
230
−
Vdc
VREF(CV)
3.41
3.52
3.63
V
GEA
40
50
60
mS
CONSTANT VOLTAGE SECTION
Internal voltage reference for constant voltage
regulation
CV Error amplifier Gain
Error amplifier current capability
VREFX = VREF (no dimming)
COMP pin lower clamp voltage
IEA
−
±60
−
mA
VCV(clampL)
−
0.6
−
V
COMP pin higher clamp voltage
TJ = 0°C to 125°C
VCV(clampH)
4.05
4.12
4.25
V
COMP pin higher clamp voltage
TJ = −40°C to 125°C
VCV(clampH)
4.01
4.12
4.25
V
Internal ZCD voltage below which the CV OTA is
boosted
VREF(CV) * 85%
Vboost(CV)
2.796
2.975
3.154
V
Threshold for releasing the CV boost
VREF(CV) * 90%
Vboost(CV)RST
2.96
3.15
3.34
V
Internal ZCD voltage below which the CV OTA is
boosted (opt.2)
VREF(CV) * 80%
Vboost(CV)2
2.632
2.8
2.968
V
Error amplifier current capability during boost phase
ZCD OVP 1st level (slow OVP) option 1
ZCD OVP
1st
level (slow OVP) option 2
VREF(CV) * 115%
IEAboost
−
±140
−
mA
VOVP1
3.783
4.025
4.267
V
VREF(CV) * 120%
VOVP1
3.948
4.2
4.452
V
ZCD voltage at which slow OVP is exit (option 1)
VREF(CV) * 105%
VOVP1rst
−
3.675
−
V
ZCD voltage at which slow OVP is exit (option 2)
VREF(CV) * 110%
VOVP1rst
−
3.85
−
V
Tsw(OVP1)
−
1.5
−
ms
VOVP2
−
4.7
−
V
V
Switching period during slow OVP
ZCD fast OVP option 2
Vref(CV) * 130% + 150 mV
ZCD fast OVP option 1
Vref(CV) * 125% + 150 mV
Number of switching cycles before fast OVP
confirmation
Duration for disabling DRV pulses during ZCD fast
OVP
COMP pin internal pullup resistor (prog option)
VOVP2
4.253
4.525
4.797
TOVP2_CNT
−
4
−
Trecovery
−
4
−
s
Rpullup
−
15
−
kW
LINE FEED FORWARD
VHV to ICS(offset) conversion ratio
KLFF
0.189
0.21
0.231
mA/V
Offset current maximum value
VHV > (450 V or 500 V)
Ioffset(MAX)
76
95
114
mA
Line feed−forward current
DRV high, VHV = 200 V
IFF
35
40
45
mA
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NCL30486
ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V, VZCD = 0 V, VCS = 0 V)
For min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V) (continued)
Parameter
Test Condition
Symbol
Min
Typ
Max
Unit
VALLEY LOCKOUT SECTION
Threshold for line range detection VHV increasing
(1st to 2nd valley transition for VREFX > 80% VREF)
(prog. option: 1st to 3rd valley transition)
VHV increases
VHL
228
240
252
V
Threshold for line range detection VHV decreasing
(2nd to 1st valley transition for VREFX > 80% VREF)
(prog. option: 3rd to 1st valley transition)
VHV decreases
VLL
218
230
242
V
tHL(blank)
15
25
35
ms
VREF decreases
VVLY1−2/2−3
−
0.80
−
VREF increases
VVLY2−1/3−2
−
0.90
−
VREF decreases
VVLY2−3/3−4
−
0.65
−
VREF increases
VVLY3−2/4−3
−
0.75
−
VREF decreases
VVLY3−4/4−5
−
0.50
−
VREF increases
VVLY4−3/5−4
−
0.60
−
VREF decreases
VVLY4−5/5−6
−
0.35
−
VREF increases
VVLY5−4/6−5
−
0.45
−
VREF value at which the FF mode is activated
VREF decreases
VFFstart
−
0.25
−
V
VREF value at which the FF mode is removed
VREF increases
VFFstop
−
0.35
−
V
Added dead time
VREFX = 0.25 V
tFF1LL
0.8
1.0
1.2
ms
Added dead time
VREFX = 0.08 V
tFFchg
−
40
−
ms
Dead−time clamp ( option 1)
VREFX < 3 mV
tFFend1
−
675
−
ms
Dead−time clamp ( option 2)
VREFX < 11.2 mV
tFFend2
−
250
−
ms
DIM pin voltage for zero output current (OFF voltage)
VADIM(EN)
0.475
0.5
0.525
V
ADIM pin voltage for 1% reference voltage
VADIM(MIN)
0.668
0.7
0.732
V
Minimum dimming level (option 1)
KDIM(MIN)1
−
0
−
%
Minimum dimming level (option 2)
KDIM(MIN)2
−
1
−
%
Minimum dimming level (option 3)
KDIM(MIN)3
−
5
−
%
Minimum dimming level (option 4)
KDIM(MIN)4
−
8
−
%
VADIM100
−
3.0
3.1
V
VADIM(range)
−
2.3
−
V
Blanking time for line range detection
Valley thresholds
1st to 2nd valley transition at LL and 2nd to 3rd valley
HL, VREF decr. (prog. option: 3rd to 4th valley HL)
2nd to 1st valley transition at LL and 3rd to 2nd valley
HL, VREF incr. (prog. option: 4th to 3rd valley HL)
2nd to 3rd valley transition at LL and 3rd to 4th valley
HL, VREF decr. (prog. option: 4th to 5th valley HL)
3rd to 2nd valley transition at LL and 4th to 3rd valley
HL, VREF incr. (prog. option: 5th to 4th valley HL)
3rd to 4th valley transition at LL and 4th to 5th valley
HL, VREF decr. (prog. option: 5th to 6th valley HL)
4th to 3th valley transition at LL and 5th to 4th valley
HL, VREF incr. (prog. option: 6th to 5th valley HL)
4th to 5th valley transition at LL and 5th to 6th valley
HL, VREF decr. (prog. option: 6th to 7th valley HL)
5th to 4th valley transition at LL and 6th to 5th valley
HL, VREF incr. (prog. option: 7th to 6th valley HL)
V
FREQUENCY FOLDBACK
DIMMING SECTION
ADIM pin voltage for maximum output current
(VREFX = 1 V)
Dimming range
Clamping voltage for DIM pin
Dimming pin pull−up current source
VADIM(CLP)
−
6.8
−
V
IADIM(pullup)1
8
10
12
mA
70
80
mA
Current Comparator threshold for PDIM
IPDIM rising
IPDIM(THR)
60
Current Comparator threshold for PDIM
IPDIM falling
IPDIM(THD)
131
153
175
mA
IPDIM(LIM)
−
1080
−
mA
VPDIM
Cascode current limit for PDIM
PDIM pin voltage
−
3
−
V
Maximum period of the PWM dimming signal
−
6
−
ms
Minimum on−time for PWM signal applied on PDIM
−
8
−
ms
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NCL30486
ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V, VZCD = 0 V, VCS = 0 V)
For min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V) (continued)
Parameter
Test Condition
Symbol
Min
Typ
Max
Unit
TSHDN
130
150
170
°C
FAULT PROTECTION
Thermal Shutdown (Note 5)
Device switching (FSW
around 65 kHz)
Thermal Shutdown Hysteresis
TSHDN(HYS)
−
20
–
°C
Threshold voltage for output short circuit or aux.
winding short circuit detection
VZCD(short)
0.6
0.65
0.7
V
tOVLD
70
90
110
ms
trecovery
3
4
5
s
Short circuit detection Timer
VZCD < VZCD(short)
Auto−recovery Timer
Line OVP threshold
VHV increasing
VHV(OVP)
457
469
485
Vdc
HV pin voltage at which Line OVP is reset
VHV decreasing
VHV(OVP)RST
430
443
465
Vdc
TLOVP(blank)
15
25
35
ms
Blanking time for line OVP reset
BROWN−OUT AND LINE SENSING
Brown−Out ON level (IC start pulsing)
VHV increasing
VHVBO(on)
101.5
108
114.5
Vdc
Brown−Out ON level (IC start pulsing) option 2
VHV increasing
VHVBO(on)2
129.7
138
146.3
Vdc
Brown−Out OFF level (IC stops pulsing)
VHV decreasing
VHVBO(off)
92
98
104
Vdc
Brown−Out OFF level (IC stops pulsing) option 2
VHV decreasing
VHVBO(off)2
121
129
137
Vdc
HV pin voltage above which the sampling of ZCD is
enabled low line
VHV decreasing, low line
VsampENLL
−
55
−
V
HV pin voltage above which the sampling of ZCD is
enabled highline
VHV decreasing, highline
VsampENHL
−
105
−
V
ZCD sampling enable comparator hysteresis
VHV increasing
VsampHYS
−
5
−
V
BO comparators delay
tBO(delay)
−
30
−
ms
Brown−Out blanking time
tBO(blank)
15
25
35
ms
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Guaranteed by design.
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NCL30486
TYPICAL CHARACTERISTICS
5,4
309
5,3
304
5,1
IHV(start1) (mA)
IHV(start2) (mA)
5,2
5
4,9
4,8
4,7
299
294
289
4,6
4,5
284
−50
−25
0
25
50
75
100
−50
125
−25
0
TEMPERATURE (°C)
25
50
75
100
125
100
125
100
125
TEMPERATURE (°C)
Figure 3. IHV(start2) vs. Temperature
Figure 4. IHV(start1) vs. Temperature
361
18,34
357
VCC(on) (V)
VHV(OL) (V rms)
359
355
18,29
18,24
353
18,19
351
349
−50
−25
0
25
50
75
100
18,14
125
−50
−25
0
TEMPERATURE (°C)
25
50
75
TEMPERATURE (°C)
Figure 5. VHV(OL) vs. Temperature
Figure 6. VCC(on) vs. Temperature
10,25
26,96
10,23
26,91
VCC(OVP) (V)
VCC(off) (V)
10,21
10,19
10,17
26,86
26,81
10,15
26,76
10,13
26,71
26,66
10,11
−50
−25
0
25
50
75
100
−50
125
TEMPERATURE (°C)
−25
0
25
50
75
TEMPERATURE (°C)
Figure 7. VCC(off) vs. Temperature
Figure 8. VCC(OVP) vs. Temperature
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9
NCL30486
TYPICAL CHARACTERISTICS (continued)
1,7
1,41
1,69
1,39
ICC4 (mA)
ICC1 (mA)
1,68
1,37
1,35
1,33
1,67
1,66
1,65
1,64
1,31
1,63
1,29
1,62
−50
−25
0
25
50
75
100
−50
125
−25
0
TEMPERATURE (°C)
Figure 9. ICC1 vs. Temperature
54
1.402
53,5
VCS(low)F (mV)
VILIM (V)
1.400
1.398
1.396
1.394
1.392
100
125
51,5
50,5
50
125
52
1.388
25
100
52,5
51
0
75
53
1.390
−25
50
Figure 10. ICC4 vs. Temperature
1.404
1.386
−50
25
TEMPERATURE (°C)
75
100
50
125
−50
−25
0
TEMPERATURE (°C)
25
50
75
TEMPERATURE (°C)
Figure 11. VILIM vs. Temperature
Figure 12. VCS(low)F vs. Temperature
2,06
20,24
20,19
2,02
ton(MAX)2 (ms)
VCS(stop) (V)
2,04
2
1,98
20,14
20,09
20,04
19,99
19,94
1,96
19,89
19,84
1,94
−50
−25
0
25
50
75
100
−50
125
TEMPERATURE (°C)
−25
0
25
50
75
100
TEMPERATURE (°C)
Figure 13. VCS(stop) vs. Temperature
Figure 14. ton(MAX)2 vs. Temperature
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10
125
NCL30486
TYPICAL CHARACTERISTICS (continued)
359
180
179
354
tBCS (ns)
tLEB (ns)
178
349
344
177
176
175
174
339
173
334
172
−50
−25
0
25
50
75
100
−50
125
−25
0
TEMPERATURE (°C)
25
50
75
100
125
100
125
100
125
TEMPERATURE (°C)
Figure 15. tLEB vs. Temperature
Figure 16. tBCS vs. Temperature
120
10,5
110
9,5
100
RSNK (W)
tILIM (ns)
8,5
90
80
70
7,5
6,5
5,5
60
4,5
50
−50
−25
0
25
50
75
100
3,5
125
−50
−25
0
TEMPERATURE (°C)
25
50
75
TEMPERATURE (°C)
Figure 17. tILIM vs. Temperature
Figure 18. RSNK vs. Temperature
34
15,5
32
30
tr (ns)
RSRC (W)
13,5
11,5
28
26
9,5
24
7,5
22
20
5,5
−50
−25
0
25
50
75
100
−50
125
TEMPERATURE (°C)
−25
0
25
50
75
TEMPERATURE (°C)
Figure 19. RSRC vs. Temperature
Figure 20. tr vs. Temperature
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11
NCL30486
TYPICAL CHARACTERISTICS (continued)
21,5
83
20,5
82,5
19,5
VZCD(rising) (mV)
82
tF (ns)
18,5
17,5
16,5
15,5
81,5
81
80,5
80
14,5
79,5
13,5
12,5
79
−50
−25
0
25
50
75
100
−50
125
−25
0
TEMPERATURE (°C)
25
50
75
100
125
TEMPERATURE (°C)
Figure 21. tf vs. Temperature
Figure 22. VZCD(rising) vs. Temperature
0,672
54,5
53,5
VZCD(short) (V)
VZCD(falling) (mV)
0,67
52,5
51,5
0,668
0,666
0,664
0,662
50,5
0,66
49,5
−50
−25
0
25
50
75
100
0,658
125
−50
−25
0
TEMPERATURE (°C)
25
50
75
100
125
TEMPERATURE (°C)
Figure 23. VZCD(falling) vs. Temperature
Figure 24. VZCD(short) vs. Temperature
116
1,605
tZCD(blank1)OPN1 (ms)
111
tZCD(DEM) (ns)
106
101
96
91
86
1,595
1,585
1,575
1,565
81
1,555
76
−50
−25
0
25
50
75
100
−50
125
TEMPERATURE (°C)
−25
0
25
50
75
100
TEMPERATURE (°C)
Figure 25. tZCD(dem) vs. Temperature
Figure 26. tZCD(blank1)OPN1 vs. Temperature
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12
125
NCL30486
TYPICAL CHARACTERISTICS (continued)
0,861
tZCD(blank2)OPN1 (ms)
tZCD(blank1)OPN2 (ms)
1,072
1,067
1,062
1,057
1,052
0,856
0,851
0,846
0,841
1,047
1,042
0,836
−50
−25
0
25
50
75
100
−50
125
−25
0
TEMPERATURE (°C)
Figure 27. tZCD(blank1)OPN2 vs. Temperature
50
75
100
125
Figure 28. tZCD(blank2)OPN1 vs. Temperature
0,584
6,92
0,579
6,87
tTIMO (ms)
tZCD(blank2)OPN2 (ms)
25
TEMPERATURE (°C)
0,574
0,569
6,82
6,77
0,564
−50
−25
0
25
50
75
100
6,72
125
−50
−25
0
TEMPERATURE (°C)
25
50
75
100
125
100
125
TEMPERATURE (°C)
Figure 29. tZCD(blank2)OPN2 vs. Temperature
Figure 30. tTIMO vs. Temperature
336,8
336,3
34,6
335,8
VREF10/3 (mV)
VREF/3 (mV)
335,3
334,8
334,3
333,8
333,3
34,1
33,6
33,1
332,8
332,3
32,6
331,8
−50
−25
0
25
50
75
100
−50
125
TEMPERATURE (°C)
−25
0
25
50
75
TEMPERATURE (°C)
Figure 31. VREF/3 vs. Temperature
Figure 32. VREF10/3 vs. Temperature
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13
NCL30486
TYPICAL CHARACTERISTICS (continued)
3,545
17,7
3,535
3,525
17,3
VREF(CV) (V)
VREF5/3 (mV)
17,5
17,1
16,9
3,515
3,505
16,7
3,495
16,5
3,485
16,3
3,475
−50
−25
0
25
50
75
100
125
−50
−25
0
TEMPERATURE (°C)
25
50
75
100
125
TEMPERATURE (°C)
Figure 33. VREF5/3 vs. Temperature
Figure 34. VREF(CV) vs. Temperature
4,15
4,075
4,065
4,13
4,055
VOVP1 (V)
VCV(clampH) (V)
4,14
4,12
4,11
4,045
4,035
4,025
4,1
4,015
4,09
4,005
4,08
−50
−25
0
25
50
75
100
3,995
125
−50
−25
0
TEMPERATURE (°C)
25
50
75
100
125
100
125
TEMPERATURE (°C)
Figure 35. VCV(clampH) vs. Temperature
Figure 36. VOVP1 vs. Temperature
0,2095
4,54
0,2085
0,2075
KLFF (mA/V)
VOVP2 (V)
4,53
4,52
4,51
0,2065
0,2055
0,2045
0,2035
0,2025
4,5
0,2015
0,2005
−50
4,49
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
−25
0
25
50
75
TEMPERATURE (°C)
Figure 37. VOVP2 vs. Temperature
Figure 38. KLFF vs. Temperature
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14
NCL30486
TYPICAL CHARACTERISTICS (continued)
104
41,7
103
41,5
41,3
101
IFF (mA)
Ioffset(MAX) (mA)
102
100
99
41,1
40,9
40,7
98
40,5
97
40,3
96
40,1
−50
−25
0
25
50
75
100
−50
125
−25
0
TEMPERATURE (°C)
25
50
75
100
125
100
125
TEMPERATURE (°C)
Figure 39. Ioffset(MAX) vs. Temperature
Figure 40. IFF vs. Temperature
1,0395
2,208
1,0375
2,203
VREF(PFC)CLP (V)
1,0385
tFF1LL (ms)
1,0365
1,0355
1,0345
1,0335
2,198
2,193
2,188
2,183
1,0325
2,178
1,0315
2,173
1,0305
−50
−25
0
25
50
75
100
2,168
125
−50
−25
0
TEMPERATURE (°C)
Figure 41. tFF1LL vs. Temperature
0,708
0,5045
0,706
0,5035
75
0,704
VADIM(MIN) (V)
VADIM(EN) (V)
50
Figure 42. VREF(PFC)CLP vs. Temperature
0,5055
0,5025
0,5015
0,5005
0,4995
0,702
0,7
0,698
0,696
0,4985
0,4975
−50
25
TEMPERATURE (°C)
0,694
−25
0
25
50
75
100
−50
125
TEMPERATURE (°C)
−25
0
25
50
75
100
TEMPERATURE (°C)
Figure 43. VADIM(EN) vs. Temperature
Figure 44. VADIM(MIN) vs. Temperature
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15
125
NCL30486
TYPICAL CHARACTERISTICS (continued)
71,6
153,2
IPDIM(THD) (mA)
IPDIM(THR) (mA)
152,7
71,1
70,6
70,1
152,2
151,7
151,2
150,7
150,2
149,7
69,6
149,2
−50
−25
0
25
50
75
100
125
−50
−25
0
TEMPERATURE (°C)
Figure 45. IPDIM(THR) vs. Temperature
50
75
100
125
Figure 46. IPDIM(THD) vs. Temperature
3,013
1,086
3,008
VPDIM (V)
1,081
IPDIM(LIM) (mA)
25
TEMPERATURE (°C)
1,076
1,071
1,066
3,003
2,998
2,993
2,988
1,061
2,983
1,056
−50
−25
0
25
50
75
100
2,978
125
−50
−25
0
TEMPERATURE (°C)
25
50
75
100
125
100
125
TEMPERATURE (°C)
Figure 47. IPDIM(LIM) vs. Temperature
Figure 48. VPDIM vs. Temperature
108,9
3,011
108,7
3,006
VHVBO(on)OPN1 (V)
108,5
VADIM100 (V)
3,001
2,996
2,991
2,986
108,3
108,1
107,9
107,7
107,5
107,3
2,981
107,1
106,9
2,976
−50
−25
0
25
50
75
100
−50
125
TEMPERATURE (°C)
−25
0
25
50
75
TEMPERATURE (°C)
Figure 49. VADIM100 vs. Temperature
Figure 50. VHVBO(on)ONP1 vs. Temperature
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16
NCL30486
TYPICAL CHARACTERISTICS (continued)
99,6
472
99,4
471
470
VHV(OVP) (V dc)
VHVBO(off)OPN1 (V)
99,2
99
98,8
98,6
98,4
469
468
467
466
98,2
465
98
97,8
464
−50
−25
0
25
50
75
100
−50
125
TEMPERATURE (°C)
VHV(OVP)RST (V dc)
445
444
443
442
441
440
439
0
25
50
75
25
50
75
100
Figure 52. VHV(OVP) vs. Temperature
446
−25
0
TEMPERATURE (°C)
Figure 51. VHVBO(off)ONP1 vs. Temperature
−50
−25
100
125
TEMPERATURE (°C)
Figure 53. VHV(OVP)RST vs. Temperature
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125
NCL30486
Application Information
The NCL30486 implements a current−mode architecture
operating in quasi−resonant mode. Thanks to proprietary
circuitry, the controller is able to accurately regulate the
secondary side current and voltage of the fly−back converter
without using any opto−coupler or measuring directly the
secondary side current or voltage. The controller provides
near unity power factor correction
• Quasi−Resonance
Current−Mode
Operation:
implementing quasi−resonance operation in peak
current−mode control, the NCL30486 optimizes the
efficiency by switching in the valley of the MOSFET
drain−source voltage. Thanks to an internal algorithm
control, the controller locks−out in a selected valley and
remains locked until the input voltage or the output
current set point significantly changes.
• Primary Side Constant Current Control: thanks to a
proprietary circuit, the controller is able to take into
account the effect of the leakage inductance of the
transformer and allows an accurate control of the
secondary side current regardless of the input voltage and
output load variation.
• Primary Side Constant Voltage Regulation: By
monitoring the auxiliary winding voltage, it is possible to
regulate accurately the output voltage. The output voltage
regulation is typically within ±2%.
• Load Transient Compensation: Since PFC has low loop
bandwidth, abrupt changes in the load may cause
excessive over or under−shoot. The slow Over Voltage
Protection contains the output voltage when it tends to
become excessive. In addition, the NCL30486 speeds up
the constant voltage regulation loop when the output
voltage goes below 80% or 85% of its regulation level.
• Power Factor Correction: A proprietary concept allows
achieving high power factor correction and low THD
while keeping accurate constant current and constant
voltage control.
• Line Feed−forward: allows compensating the variation of
the output current caused by the propagation delay.
• VCC Over Voltage Protection: if the VCC pin voltage
exceeds an internal limit, the controller shuts down and
waits 4 seconds before restarting pulsing.
• Fast Over Voltage Protection: If the voltage of ZCD pin
exceeds 130% of its regulation level, the controller shuts
down and waits 4 s before trying to restart.
• Brown−Out: the controller includes a brown−out circuit
which safely stops the controller in case the input voltage
is too low. The device will automatically restart if the line
recovers.
• Cycle−by−cycle peak current limit: when the current
sense voltage exceeds the internal threshold VILIM, the
MOSFET is turned off for the rest of the switching cycle.
• Winding Short−Circuit Protection: an additional
comparator senses the CS signal and stops the controller
•
•
•
•
if VCS reaches 1.5 x VILIM (after a reduced LEB of tBCS).
This additional comparator is enabled only during the
main LEB duration tLEB, for noise immunity reason.
Output Under Voltage Protection: If a too low voltage is
applied on ZCD pin for 90 ms time interval, the
controllers assume that the output or the ZCD pin is
shorted to ground and shutdown. After waiting 4 seconds,
the IC restarts switching.
Analog Dimming: the ADIM pin is dedicated to analog
dimming. There are several options for the minimum
dimming level. Pulling the pin voltage lower than
VADIM(EN) disables the controller.
PWM dimming: the PDIM pin is dedicated to PWM
dimming. The controller measures the duty ratio of a
signal applied to the pin and reduces the output current
accordingly. If this pin is left open, the controller delivers
the maximum output current. If the pin is pulled down, the
controller is disabled.
Thermal Shutdown: an internal circuitry disables the gate
drive when the junction temperature exceeds 150°C
(typically). The circuit resumes operation once the
temperature drops below approximately 100°C.
POWER FACTOR AND CONSTANT CURRENT
CONTROL
The NCL30486 embeds an analog/digital block to control
the power factor and regulate the output current by
monitoring the ZCD, CS and HV pin voltages (signals
VZCD, VHV_DIV, VCS). This circuit generates the current
setpoint signal and compares it to the current sense signal to
turn the MOSFET off. The HV pin provides the sinusoidal
reference necessary for shaping the input current. The
obtained current reference is further modulated so that when
averaged over a half line period, it is equal to the output
current reference (VREFX). The modulation and averaging
process is made internally by a digital circuit. If the HV pin
properly conveys the sinusoidal shape, power factor will be
close to 1. Also, the Total Harmonic Distortion (THD) will
be low especially if the output voltage ripple is small.
I OUT +
V REF
2N spR sense
(eq. 1)
Where:
• Nsp is the secondary to primary transformer turns ratio:
Nsp = NS / NP
• Rsense is the current sense resistor
• VREFX is the output current reference: VREFX = VREF if
no dimming
The output current reference (VREFX) is VREF unless the
constant voltage mode is activated or ADIM pin voltage is
below VADIM(100) or a PWM signal with a duty−cycle below
95% is applied on PDIM.
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18
NCL30486
PRIMARY SIDE CONSTANT VOLTAGE CONTROL
The auxiliary winding voltage is sampled internally
through the ZCD pin.
A precise internal voltage reference VREF(CV) sets the
voltage target for the CV loop.
The sampled voltage is applied to the negative input of the
constant voltage (CV) operational transconductance
amplifier (OTA) and compared to VREFCV.
RZCDU
ZCD
A type 2 compensator is needed at the CV OTA output to
stabilize the loop. The COMP pin voltage modify the the
output current internal reference in order to regulate the
output voltage.
When VCOMP ≥ 4 V, VREFX = VREF.
When VCOMP < 0.9 V, VREFX = 0 V.
VZCDsamp
ZCD & signal
sampling
Gm
COMP
.
RZCDL
VREF(CV)
Aux.
OTA
R1
C2
C1
Figure 54. Constant Voltage Feedback Circuit
Secondary Side Regulation Compatible
The NCL30486 features a high voltage startup circuit that
allows charging VCC capacitor very fast.
When the power supply is first connected to the mains
outlet, the internal current source is biased and charges up
the VCC capacitor. When the voltage on this VCC capacitor
reaches the VCC(on) level, the current source turns off. At this
time, the controller is only supplied by the VCC capacitor,
and the auxiliary supply should take over before VCC
collapses below VCC(off).
The HV startup circuitry is made of two startup current
levels, IHV(start1) and IHV(start1). This helps to protect the
controller against short−circuit between VCC and GND. At
power−up, as long as VCC is below VCC(TH), the source
delivers IHV(start1) (around 300 mA typical). Then, when
VCC reaches VCC(TH), the source smoothly transitions to
IHV(start2) and delivers its nominal value. As a result, in case
of short−circuit between VCC and GND occurring at high
line (Vin = 305 V rms), the maximum power dissipation will
be 431 x 300 m = 130 mW instead of 1.5 W if there was only
one startup current level.
To speed−up the output voltage rise, the following is
implemented:
• The digital OTA output is increased until VREF(PFC)
signal reaches VREFX. Again, this is to speed−up the
control signal rise to their steady state value.
• At the beginning of each operating phase of a VCC cycle,
the digital OTA output is set to 0. Actually, the digital
OTA output is set to 0 in the case of a cold start−up or in
the case of a start−up sequence following an operation
interruption due to a fault. On the other hand, if the VCC
hiccups just because the system fails to start−up in one
VCC cycle, the digital OTA output is not reset to ease the
second (or more) attempt.
The NCL30486 is able to support secondary−side
regulation as well. The controller features an option to
provide a pullup resistor Rpullup on COMP pin instead of the
CV OTA output. This allows connecting directly an
optocoupler collector and properly biases it. The internal
voltage biasing Rpullup is around 5 V.
In secondary side regulation, the slow and fast OVP on
ZCD pin are still active thus providing an additional over
voltage protection. In this case, the ZCD pin resistors should
be calculated to trigger VOVP2 at the output voltage of
interest.
VDD
CV OTA Boost
Rpullup
COMP
−
+
VREF(CV)
Figure 55. COMP Pin Configuration for Secondary
Side Regulation
STARTUP PHASE (HV STARTUP)
It is generally requested that the LED driver starts to emit
light in less than 1 s and possibly within 300 ms. It is
challenging since the start−up consists of the time to charge
the VCC capacitor and that necessary to charge the output
capacitor until sufficient current flows into the LED string.
This second phase can be particularly long in dimming cases
where the secondary current is a portion of the nominal one.
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19
NCL30486
• If the load is shorted, the circuit will operate in hiccup
The application note ANDXXXX gives more details about
strategies to decrease the power dissipation of the HV
startup circuit.
mode with VCC oscillating between VCC(off) and VCC(on)
until the output under voltage protection (UVP) trips.
UVP is triggered if the ZCD pin voltage does not exceed
VZCD(short) within a 90 ms operation of time. This
indicates that the ZCD pin is shorted to ground or that an
excessive load prevents the output voltage from rising.
Cycle−by−Cycle Current Limit
When the current sense voltage exceeds the internal
threshold VILIM, the MOSFET is turned off for the rest of the
switching cycle.
HV Startup Power Dissipation
Winding and Output Diode Short−Circuit Protection
At high line (305 V rms and above) the power dissipated
by the HV startup in case of fault or when the controller is
disabled with PDIM becomes high. Indeed, in case of fault,
the NCL30486 is directly supplied by the HV rail. When the
controller is disabled with PDIM, the optocoupler collector
current is also supplied by the controller, since the
NCL30486 allows directly connecting the optocoupler
transistor to PDIM pin. Thus, the HV startup circuit also
supplies the optocoupler transistor in case of faults. The
current flowing through the HV startup will heat the
controller. It is highly recommended adding enough copper
around the controller to decrease the RqJA of the controller.
Adding a minimum pad area of 215 mm2 of 35 mm copper
(1 oz) drops the RqJA to around 120°C/W (no air flow, RqJA
measured at ADIM pin)
The PCB layout shown in Figure 56 is a layout example
to achieve low RqJA.
In parallel to the cycle−by−cycle sensing of the CS pin,
another comparator with a reduced LEB (tBCS ) and a
threshold of (VCS(stop) = 140% x VILIM ) monitors the CS pin
to detect a winding or an output diode short circuit. The
controller shuts down if it detects 4 consecutives pulses
during which the CS pin voltage exceeds VCS(stop).
The controller goes into auto−recovery mode.
PWM Dimming
The NCL30486 has a dedicated pin for PWM dimming.
The controller directly measures the duty ratio of a PWM
signal applied to PDIM.
Two counters with a high frequency clock are used for this
purpose. A first counter measure the high state duration of
the PWM signal (ton_PDIM) and the second counter measures
its period (Tsw_PDIM). A divider computes (ton_PDIM /
Tsw_PDIM) and the result is directly the output current
setpoint (VREFX set point). A filter is added after the digital
divider to remove the ripple of the signal. A cascode
configuration on PDIM pin allows decreasing the fall time
of the signal.
Thanks to this circuit, the LED current is controlled in an
analog way, even if a PWM signal is used for dimming. This
allows having a good PF during dimming.
Figure 56. PCD Layout Example
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20
NCL30486
VDIM_sec
IPDIM
IPDIM(THD)
IPDIM(THR)
VPDIM_int
Ton
Tsw
Figure 57. PDIM Internal Waveforms
Analog Dimming
Practically, the controller extracts the duty−cycle by
measuring the current inside PDIM pin which is directly the
opto coupler collector current.
If PDIM pin is left open, the controller delivers 100% of
Iout. If the pin is pulled down for longer than 25 ms, the
controller is disabled.
If the PWM dimming signal is removed during dimming,
the controller delivers 100% of Iout.
The NCL30486 set 100% of output current when the
duty−cycle of the signal applied on PDIM is above 93%.
The pin ADIM pin allows implementing analog dimming
of the LED light.
If the power supply designer applies an analog signal
varying from VDIM(EN) to VDIM100 to the DIM pin, the
output current will increase or decrease proportionally to the
voltage applied. For VDIM = VDIM100, the power supply
delivers the maximum output current (VREFX = 1 V).
If a voltage lower than VADIM(MIN) is applied to ADIM
pin, the output current is clamped to the selected dimming
clamp value (see Dimming clamp section below)
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21
NCL30486
If a voltage lower than VADIM(EN) is applied to the DIM
pin, the DRV pulses are disabled for controllers without the
dimming CV mode option.
The DIM pin is pulled up internally by a small current
source or resistor. Thus, if the pin is left open, the controller
is able to start.
NOTE:
• Interaction between ADIM and PDIM: if ADIM and
•
PDIM are both used at the same time, the resulting
dimming set point if a multiplication of VADIM and the
duty−ratio of PDIM signal.
During dimming, when the “Enable” signal is OK, the
controller starts pulsing after 1 time−out pulse, even if a
higher valley number is selected by VREFX. This is to
avoid too long startup time while dimming at low output
current value.
VREF
100% VREF
5% VREF
1% VREF
8% VREF
VADIM(EN) VADIM(MIN)
VADIM100
VADIM
Figure 58. ADIM Pin Dimming Curves
Dimming Clamp
For smart dimming applications, need to bias the
secondary−side MCU. This can be achieved by clamping
VREFX when the dimming setpoint is small.
•
•
•
•
There are 4 options for the dimming clamp:
No dimming clamp
1%
5%
8%
VREFX (%)
100%
8%
5%
1%
0.01 0.05 0.08
1.0
Scaled dimming voltage or
dimming duty−ratio
Figure 59. Dimming Clamp Options
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22
NCL30486
Dimming Curves
By default, there is a linear relationship between the
voltage applied on ADIM pin and VREFX setpoint. In the
same way, there is a linear relationship between the
duty−ratio of the signal applied on PDIM and VREFX
setpoint.
An internal memory allows selecting a root square
relationship between dimming and VREFX.
The square like curve is based on CIE 1931 lightness
formula.
Output Current vs. Dimming
100
90
Output Current (%)
80
70
60
50
linear
CIE 1931
40
30
20
10
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Scaled Dimming Voltage or Dimming Duty Ratio
Figure 60. Dimming Curves
Valley Lockout
is varied during dimming. This limits the frequency
excursion.
By default, when the output current is not dimmed, the
controller operates in the first valley at low line and in the
second valley at high line.
There is an option to have the valley thresholds
incremented by 1 at high line for better Iout control at
305 V rms.
Quasi−Square wave resonant systems have a wide
switching frequency excursion. The switching frequency
increases when the output load decreases or when the input
voltage increases. The switching frequency of such systems
must be limited.
The NCL30486 changes valley as VREFX decreases and as
the input voltage increases and as the output current setpoint
Table 1. VALLEY SELECTION
VHV_DIV Voltage for Valley Change
0
Iout decreases
100%
80%
65%
50%
35%
25%
0%
0
−−LL−−
2.3 V
−−HL−−
1st
2nd (3rd)
2nd
3rd (4th)
3rd
4th (5th)
4th
5th (6th)
5th
6th (7th)
FF mode
FF mode
−−LL−−
2.3 V
−−HL−−
5V
100%
80%
65%
50%
35%
25%
0%
5V
Internal VHV_DIV Voltage for Valley Change
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23
VREFX Value at Which the Controller
Changes Valley(Iout Increasing)
Iout decreases
VREFX value at which the Controller
Changes Valley (Iout Decreasing)
NCL30486
Zero Crossing Detection Block
The Time−out also acts as a substitute clock for the valley
detection and simulates a missing valley in case of too
damped free oscillations.
At startup, the output voltage reflected on the auxiliary
winding is low. Because of the ZCD resistor bridge setting
the constant voltage regulation target, the voltage on the
ZCD pin is very low and the ZCD comparator might be
unable to detect the valleys. In this condition, setting the
DRV latch with the 6.5 ms time−out leads to a continuous
conduction mode operation (CCM) at the beginning of the
soft−start. This CCM operation only last a few cycles until
the voltage on ZCD pin becomes high enough and trips the
ZCD comparator.
The ZCD pin allows detecting when the drain−source
voltage of the power MOSFET reaches a valley.
A valley is detected when the ZCD pin voltage crosses
below the 55 mV internal threshold.
At startup or in case of extremely damped free
oscillations, the ZCD comparator may not be able to detect
the valleys. To avoid such a situation, Optimus Prime
features a Time−Out circuit that generates pulses if the
voltage on ZCD pin stays below the 55 mV threshold for
6.5 ms.
VZCD
VZCD(th)
low
3
4
high
14
Iout decreases or Vin
increases
high
12
ZCD comp
high
low
15
TimeOut
low
16
2nd ,
3 rd
high
VVIN
increases
Clock
low
17
Figure 61. Valley Detection and Time−out Chronograms
If the ZCD pin or the auxiliary winding happen to be
shorted the time−out function would normally make the
controller keep switching and hence lead to improper
regulation of the LED current.
The Under Voltage Protection (UVP) is implemented to
avoid these scenarios: a secondary timer starts counting
when the ZCD voltage is below the VZCD(short) threshold. If
this timer reaches 90 ms, the controller detects a fault and
enters the auto−recovery fault mode.
Slow OVP
If ZCD voltage exceeds VOVP1 for 4 consecutive
switching cycles, the controller stops switching during
1.4 ms. The PFC loop is not reset. After 1.4 ms, the
controller initiates a new DRV pulse to refresh ZCD
sampling voltage. If VZCD is still too high (VZCD > 110%
VREF(CV)), the controller continues to switch with a 1.4 ms
period. The controller resumes its normal operation when
VZCD < 110% VREF(CV).
During slow OVP, the peak current setpoint is COMP pin
voltage scaled down by a fixed ratio.
ZCD Over Voltage Protection
Because of the power factor correction, it is necessary to
set the crossover frequency of the CV loop very low (target
10 Hz, depending on power stage phase shift). Because the
loop is slow, the output voltage can reach high value during
startup or during an output load step. It is necessary to limit
the output voltage excursion. For this, the NCL30486
features a slow OVP and a fast OVP on ZCD pin.
Fast OVP
If ZCD voltage exceeds VZCD(OVP2) (130% of VREF(CV))
for 4 consecutive switching cycles (slow OVP not triggered)
or for 2 switching cycles if the slow OVP has already been
triggered, the controller detects a fault and starts the
auto−recovery fault mode (cf: Fault Management Section)
www.onsemi.com
24
NCL30486
Line Feedforward
HV
v DD
v VS
CS
I CS(offset)
R LFF
K LFF
R sense
Q_drv
+
25 ms
Blanking
−
BO_NOK
1 V / 0.9 V
Figure 62. Line Feed−Forward and Brown−out Schematic
The line voltage is sensed by the HV pin and converted
into a current. By adding an external resistor in series
between the sense resistor and the CS pin, a voltage offset
proportional to the line voltage is added to the CS signal. The
offset is applied only during the MOSFET on−time in order
to not influence the detection of the leakage inductance
reset.
The offset is always applied even at light load in order to
improve the current regulation at low output load.
below VHVBO(off) for 25 ms typical. Exiting a brown−out
condition overrides the hiccup on VCC (VCC does not wait
to reach VCC(off)) and the IC immediately goes into startup
mode.
An option with higher brown−out levels is also available
(see ordering table and electricals parameters)
Line OVP
In order to protect the power supply in case of too high
input voltage, the NCL30486 features a line over voltage
protection. When the voltage on HV pin exceeds VHV(OVP)
the controller stops switching; VCC hiccups.
When VHV becomes lower than VHV(OVP)RST for more
than 25 ms, the controller initiates a clean startup sequence
and re−starts switching.
Brown−out
In order to protect the supply against a very low input
voltage, the controller features a brown−out circuit with a
fixed ON/OFF threshold. The controller is allowed to start
if a voltage higher than VHVBO(on) is applied to the HV pin
and shuts−down if the HV pin voltage decreases and stays
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25
NCL30486
V HV
V HV(OVP)
V HV(OVP)RST
t LOVP(blank)
V CC
V CC(on)
V CC(off)
V DRV
I out
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
Figure 63. Line OVP Chronograms
Protections
• Winding or Output Diode Short Circuit protection
The circuit incorporates a large variety of protections to
make the LED driver very rugged.
Among them, we can list:
• Fault of the GND connection
If the GND pin is properly connected, the supply current
drawn from the positive terminal of the VCC capacitor,
flows out of the GND pin to return to the negative terminal
of the VCC capacitor. If the GND pin is not connected, the
circuit ESD diodes offer another return path. The
accidental non connection of the GND pin can hence be
detected by detecting that one of this ESD diode is
conducting. Practically, the ESD diode of CS pin is
monitored. If such a fault is detected for 200 ms, the circuit
stops generating DRV pin.
• Output short circuit situation (Output Under Voltage
Protection)
Overload is detected by monitoring the ZCD pin voltage:
if it remains below VZCD(short) for 90 ms, an output short
circuit is detected and the circuit stops generating pulses
for 4 s. When this 4 s delay has elapsed, the circuit
attempts to restart.
• ZCD pin incorrect connection:
♦ If the ZCD pin grounded, the circuit will detect an
output short circuit situation when 90 ms delay has
elapsed.
♦ A 200 kW resistor pulls down the ZCD pin so that
the output short circuit detection trips if the ZCD pin
is not connected (floating).
•
•
•
•
The circuit detects this failure when 4 consecutive DRV
pulses occur within which the CS pin voltage exceeds
(VCS(stop) = 140% x VILIM). In this case, the controller
enters auto−recovery mode (4−s operation interruption
between active bursts).
VCC Over Voltage Protection
The circuit stops generating pulses if the VCC exceeds
VCC(OVP) and enters auto−recovery mode. This feature
protects the circuit if output LEDs happen to be
disconnected.
ZCD fast OVP
If ZCD voltage exceeds VZCD(OVP2) for 4 consecutive
switching cycles (slow OVP not triggered) or for 2
switching cycles if the slow OVP has already been
triggered, the controller detects a fault and enters
auto−recovery mode (4 s operation interruption between
active bursts).
Die Over Temperature (TSD)
The circuit stops operating if the junction temperature
(TJ) exceeds 150°C typically. The controller remains off
until TJ goes below nearly 130°C.
Brown−Out Protection (BO)
The circuit prevents operation when the line voltage is too
low to avoid an excessive stress of the LED driver.
Operation resumes as soon as the line voltage is high
enough and VCC is higher than VCC(on).
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26
NCL30486
• CS pin short to ground
The CS pin is checked at start−up (cold start−up or after
a brown−out event). A current source (Ics(short)) is applied
to the pin and no DRV pulse is generated until the CS pin
exceeds Vcs(low). Ics(short) and Vcs(low) are 500 mA and
60 mV typically (VCS rising). The typical minimum
impedance to be placed on the CS pin for operation is then
120 W. In practice, it is recommended to place more than
•
250 W to take into account possible parametric deviations.
Also, along the circuit operation, the CS pin could happen
to be grounded. If it is grounded, the MOSFET
conduction time is limited by the 20 ms maximum
on−time. If such an event occurs, a new pin impedance
test is made.
Line overvoltage protection
(see Line OVP section)
ORDERING TABLE OPTION
Maximum Dead−time
OPN #
NCL30486_ _
250 ms
VREF
1.4 ms 200 mV 333 mV
687 ms
Max. On−time
ZCD Blanking
20 ms
1 ms
33 ms
1.5 ms
Valley
Transition
from LL to HL
1st to
2nd
1st to
3rd
Standby Mode
On
Line Range
Detector
Off
On
NCL30486A1
x
x
x
x
x
x
x
NCL30486A2
x
x
x
x
x
x
x
Frozen Peak Current
During Standby Mode
VCS(SBY)
Line OVP
OPN #
NCL30486_ _
On
NCL30486A1
x
NA
NCL30486A2
x
NA
Off
380 mV 330 mV 280 mV
Brown−out Levels
On: 108 V
Off: 98 V
On: 138 V
Off: 129 V
Dimming
Curve
Dimming Clamp
0%
x
x
1%
5%
Off
8%
Linear
x
x
x
x
Square
ORDERING INFORMATION
Marking
Package type
Shipping†
NCL30486A1
L30486A1
NCL30486A2
L30486A2
SOIC9 – P7 COMP VHV PBFH
(Pb−Free)
2500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
27
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−9 NB
CASE 751BP
ISSUE A
9
1
SCALE 1:1
DATE 21 NOV 2011
2X
0.10 C A-B
D
D
A
0.20 C
2X
4 TIPS
F
0.10 C A-B
10
6
H
E
1
5
0.20 C
9X
B
5 TIPS
L2
b
0.25
A3
L
DETAIL A
M
C
SEATING
PLANE
C A-B D
TOP VIEW
9X
h
0.10 C
0.10 C
X 45 _
M
A
e
A1
C
SIDE VIEW
SEATING
PLANE
DETAIL A
END VIEW
1
6.50
9X
1.18
1
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON52301E
SOIC−9 NB
MILLIMETERS
MIN
MAX
1.25
1.75
0.10
0.25
0.17
0.25
0.31
0.51
4.80
5.00
3.80
4.00
1.00 BSC
5.80
6.20
0.37 REF
0.40
1.27
0.25 BSC
0_
8_
9
1.00
PITCH
0.58
DIM
A
A1
A3
b
D
E
e
H
h
L
L2
M
GENERIC
MARKING DIAGRAM*
RECOMMENDED
SOLDERING FOOTPRINT*
9X
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.10mm TOTAL IN EXCESS OF ’b’
AT MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS. MOLD FLASH, PROTRUSIONS, OR
GATE BURRS SHALL NOT EXCEED 0.15mm
PER SIDE. DIMENSIONS D AND E ARE DETERMINED AT DATUM F.
5. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM F.
6. A1 IS DEFINED AS THE VERTICAL DISTANCE
FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
XXXXX
ALYWX
G
XXXXX = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer
to device data sheet for actual part
marking. Pb−Free indicator, “G”, may
or not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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