NCL30105
Constant Off Time PWM
Current-Mode Controller for
LED Applications
The NCL30105 is a peak current controlled fixed off time controller
designed for LED driver applications in which the LEDs are operated
in deep Continuous Conduction Mode (CCM) without requiring slope
compensation. Featuring an adjustable off time generator, the
controller can drive a MOSFET up to a 500 kHz switching frequency.
A dedicated dimming pin enables the use of a pulse−width
modulated logic signal to dim the LEDs directly. The soft−start pin
creates a startup sequence that slowly ramps up the peak current and
enables the adjustment of the peak current setpoint for analog
dimming control. The device features robust protection features to
detect switch overcurrent faults and to detect maximum on time
events.
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1
SOIC−8
D SUFFIX
CASE 751
MARKING DIAGRAM
8
Features
•
•
•
•
•
•
•
•
L0105
ALYW
G
Constant Off Time Current−Mode Control Operation
Adjustable Off Time (0.5 ms to 10 ms)
Internal Leading Edge Blanking
Source 250 mA / Sink 500 mA Peak Drive Capability
±3.2% Current Sense Accuracy at 25°C
Internal Startup Delay
3.3 V Logic Level Dimming Input
This is a Pb−Free Device
1
L0105
A
L
Y
W
G
Safety Features
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
PIN CONNECTIONS
• Thermal Shutdown
• Maximum On Time Protection
• Overcurrent Protection
DIM
SSTART
Typical Application
VCC
GND
CS
DRV
•
•
•
•
toff
LED Backlight Drivers for LCD Panels
LED Light Bars
LED Street Lighting
LED Bulbs
1
NC
(Top View)
ORDERING INFORMATION
Device
NCL30105DR2G
Package
Shipping†
SOIC−8 2500 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2012
May, 2012 − Rev. 2
1
Publication Order Number:
NCL30105/D
NCL30105
Vin
LED1
CLED
LEDN
D
L
NCL30105
toff
DIM
VCC
Rtoff
NC
DIM
SSTART
VCC
GND
CS
DRV
Soft−Start /
Ipeak Adjustment
CSSTART
M
Rsense
CVCC
Figure 1. Typical Application Diagram
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NCL30105
Vcc
VCC
UVLO
Von = VCC(on)
Voff = VCC(off)
Vtoff(open)
NC
ok = 1, else 0
ref
1 = reset
1 = reset
tstart(delay)
VSSTART(open)
set current
high
= rst
toff
SET
start
pulse
Q
R
S
Q
Q
R
Q
/ Iratio
OVRI
+
ton >
ton(MAX)
VILIM
VILIM(fault)
tLEB(fault)
GND
−
+
+
OVRI
−
S
Q
RDIM
DIM
SSTART
SET
toff
generator
Q
VDIM(open)
ISSTART
Vcc
tLEB
down Nfault
up
count to Nfault
CS
DRV
Figure 2. Internal Circuit Architecture
Table 1. PIN FUNCTION DESCRIPTION
Pin
Number
Pin Name
Function
1
toff
Adjusts the Off Time
Duration
2
DIM
Dimming Input
3
VCC
Supplies the Controller
4
CS
Current Sense Input
5
DRV
Driver Output
6
GND
−
7
SSTART
Soft−start / Peak Current
Adjustment
8
NC
Non−connected Pin
Pin Description
A resistor to ground sets the off time duration.
This pin is used for PWM dimming or to enable/disable the controller.
An external auxiliary voltage connected to this pin supplies the controller.
This pin monitors the peak current. When the peak current reaches the
internal threshold, the DRV is turned off.
The output of the driver is connected to an external MOSFET gate.
The controller ground.
A capacitor connected to this pin sets the soft−start duration. The voltage
of this pin adjusts the peak current set point for analog dimming.
Non−connected pin
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NCL30105
Table 2. MAXIMUM RATINGS TABLE (Notes 1 – 4)
Symbol
Value
Unit
toff Voltage
Vtoff
−0.3 to 5.5
V
toff Current
Itoff
±10
mA
DIM Voltage
VDIM
−0.3 to 7
V
Rating
DIM Current
IDIM
±10
mA
SSTART Voltage
VSSTART
−0.3 to 5.5
V
SSTART Current
ISSTART
±10
mA
CS Voltage
VCS
−0.3 to 7
V
CS Current
ICS
±10
mA
VDRV
−0.3 to VCC
V
DRV Voltage
DRV Sink Current
IDRV(sink)
500
mA
IDRV(source)
250
mA
Supply Voltage
VCC
−0.3 to 22
V
Supply Current
ICC
±20
mA
Power Dissipation (SO−8)
(TA = 70°C, 2.0 Oz Cu, 55 mm2 Printed Circuit Copper Clad)
PD
450
mW
DRV Source Current
Thermal Resistance Junction−to−Ambient (SO−8)
(2.0 Oz Cu, 55 mm2 Printed Circuit Copper Clad)
Junction−to−Air, Low conductivity PCB (Note 3)
Junction−to−Air, High conductivity PCB (Note 4)
RqJA
Operating Junction Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 s)
178
168
127
°C/W
TJ
−40 to 150
°C
TSTG
−60 to 150
°C
TL
300
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device series contains ESD protection and exceeds the following tests:
Pins 1 − 8: Human Body Model 2000 V per JEDEC Standard JESD22−A114E.
Pins 1 − 8: Machine Model Method 200 V per JEDEC Standard JESD22−A115−A.
Pins 1 − 8: Charged Device Model 2000 V per JEDEC Standard JESD22−C101C.
2. This device contains Latch−Up protection and exceeds ± 100 mA per JEDEC Standard JESD78.
3. As mounted on a 40x40x1.5 mm FR4 substrate with a single layer of 80 mm2 of 2 oz copper traces and heat spreading area. As specified
for a JEDEC 51 low conductivity test PCB. Test conditions were under natural convection or zero air flow.
4. As mounted on a 40x40x1.5 mm FR4 substrate with a single layer of 650 mm2 of 2 oz copper traces and heat spreading area. As specified
for a JEDEC 51 high conductivity test PCB. Test conditions were under natural convection or zero air flow.
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NCL30105
Table 3. ELECTRICAL CHARACTERISTICS (Rtoff = 40.2 kW, VDIM = 3 V, CSSTART = 100 nF, VCS = 0 V, CDRV = 1 nF, VCC = 12 V,
unless otherwise specified (For typical values, TJ = 25°C. For min/max values, TJ = −40°C to 125°C, unless otherwise specified))
Test Conditions
Symbol
Min
Typ
Max
Unit
Startup Voltage Threshold
VCC Increasing
VCC(on)
9
10
11
V
Minimum Operating Voltage
VCC Decreasing
VCC(off)
8
8.8
10
V
Supply Voltage Hysteresis
VCC(on) − VCC(off)
VCC(HYS)
1
1.2
1.5
V
ICC(latch)
−
510
900
mA
VCC < VCC(on) − 500 mV
ICC1
−
250
390
mA
Device Disabled Current Consumption
VDIM = 0 V
ICC2
−
0.71
1.7
mA
Device Switching Current Consumption
fSW = 60 kHz
ICC3
−
1.84
2.49
mA
Drive Sink Resistance
ISNK = 25 mA
RSNK
−
6.0
13.2
W
Drive Source Resistance
ISRC = 25 mA
RSRC
−
24
44
W
Rise Time
VDRV = 10% to 90%
tr
−
80
140
ns
Fall Time
VDRV = 90% to 10%
tf
−
25
60
ns
Current Sense Voltage Threshold
TJ =−40°C to 125°C
TJ =25°C
VILIM
0.95
0.977
1.01
1.01
1.05
1.042
V
Current Sense Propagation Delay
VCS = 0 V to 1.2 V Step,
dV/dt = 10 V/ms
VCS = VILIM to VDRV = 10%
tILIM
−
60
150
ns
tLEB
470
545
670
ns
Characteristic
STARTUP AND SUPPLY CIRCUITS
Current Consumption in Latch Mode
Startup Current Consumption
GATE DRIVE
CURRENT SENSE
Leading Edge Blanking Duration
CONSTANT OFF TIME GENERATOR (Note 5)
Off Time (Note 6)
Rtoff = 5 kW
Recommended Off Time Resistor Range
toff1
0.87
1.02
1.13
ms
Rtoff(range)
2.5
−
60
kW
Minimum Off Time
Rtoff = 0 W
toff(MIN)
0.3
0.37
0.5
ms
Maximum Off Time
Rtoff = open
toff(MAX)
10
11.77
14.5
ms
Vtoff(REG)
0.95
1
1.05
V
Rtoff = 0 W
f(MAX)
500
−
−
kHz
VSSTART = 3 V
ISSTART
17
20
23
mA
VSSTART = VILIM * Iratio
Iratio
2.85
3
3.15
−
VSSTART(open)
4.5
5
5.5
V
ISSTART = 5 mA
RDS(on)SSTART
200
350
500
W
Dimming Enable Voltage Threshold
VDIM Increasing
VDIM(H)
1.8
2
2.2
V
Dimming Disable Voltage Threshold
VDIM Decreasing
VDIM(L)
0.8
1
1.2
V
VDIM(open)
4
4.5
5.5
V
VDIM = 0 V
RDIM
50
90
150
kW
VDIM = 0 V to 3 V Step,
dV/dt = 10 V/ms
VDIM = VDIM(H) to VDRV = 90%
twake
−
0.28
1
ms
toff Pin Regulated Voltage
Maximum Switching Frequency (Note 7)
SOFT−START
Soft−Start Charge Current
Soft−Start Voltage to Peak Current Set
Point Ratio
Soft−Start Pin Open Voltage
Soft−Start Internal Discharge Switch
Resistance
DIMMING INPUT
DIM Pin Open Voltage
DIM Pin Internal Pull−Up Resistor
Dimming Wake−Up Time
5. See Figure 17.
6. The tolerance of toff is guaranteed by design.
7. The thermal limitation of the device specified by the Maximum Ratings Table must not be exceeded.
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NCL30105
Table 3. ELECTRICAL CHARACTERISTICS (Rtoff = 40.2 kW, VDIM = 3 V, CSSTART = 100 nF, VCS = 0 V, CDRV = 1 nF, VCC = 12 V,
unless otherwise specified (For typical values, TJ = 25°C. For min/max values, TJ = −40°C to 125°C, unless otherwise specified))
Characteristic
Test Conditions
Symbol
Min
Typ
Max
Unit
ton(MAX)
29.8
34
42.1
ms
Nfault
−
8
−
−
VILIM(fault)
1.5
1.6
1.7
V
tILIM(fault)
10
70
150
ns
tLEB(fault)
170
220
280
ns
tLEB(fault)/tLEB
tLEB(ratio)
0.3
0.4
0.8
−
VCC = VCC(on) to VDRV = 90%
tstart(delay)
100
130
172
ms
Thermal Shutdown
TJ = Increasing
TSHDN
155
°C
Thermal Shutdown Hysteresis
TJ = Decreasing
TSHDN(HYS)
40
°C
TSHDN(delay)
75
ms
PROTECTION
Maximum On Time
Number of Consecutive Maximum On
Time Events or Overcurrent Events
Overcurrent Current Sense Voltage
Threshold
Overcurrent Propagation Delay
VCS = 0 V to 2 V Step,
dV/dt = 10 V/ms
VCS = VILIM(fault) to VDRV = 10%
Overcurrent Leading Edge Blanking Duration
Leading Edge Blanking Duration Ratio
Startup Delay
Thermal Shutdown Delay
5. See Figure 17.
6. The tolerance of toff is guaranteed by design.
7. The thermal limitation of the device specified by the Maximum Ratings Table must not be exceeded.
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NCL30105
TYPICAL CHARACTERISTICS
9.8
VCC(off), MINIMUM OPERATING
VOLTAGE (V)
10.0
VCC(on), STARTUP VOLTAGE
THRESHOLD (V)
11.0
10.8
10.6
10.4
10.2
10.0
9.8
9.6
9.4
9.2
9.0
−50
−25
0
25
50
75
100
125
150
9.6
9.4
9.2
9.0
8.8
8.6
8.4
8.2
8.0
−50
−25
TJ, JUNCTION TEMPERATURE (°C)
310
1.3
ICC1, STARTUP CURRENT
CONSUMPTION (mA)
VCC(HYS), SUPPLY VOLTAGE
HYSTERESIS (V)
330
1.4
1.2
75
100
125
150
1.1
1.0
0.9
0.8
0.7
290
270
250
230
210
190
170
0.6
−25
0
25
50
75
100
125
150
150
−50
−25
TJ, JUNCTION TEMPERATURE (°C)
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. Supply Voltage Hysteresis vs.
Junction Temperature
Figure 6. Startup Current Consumption vs.
Junction Temperature
2.6
1.0
0.9
ICC3, DEVICE SWITCHING
CURRENT CONSUMPTION (mA)
ICC2, DEVICE DISABLED CURRENT
CONSUMPTION (mA)
50
Figure 4. Minimum Operating Voltage vs.
Junction Temperature
1.5
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
−50
25
TJ, JUNCTION TEMPERATURE (°C)
Figure 3. Startup Voltage Threshold vs.
Junction Temperature
0.5
−50
0
−25
0
25
50
75
100
125
150
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
−50
TJ, JUNCTION TEMPERATURE (°C)
−25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
Figure 7. Device Disabled Current
Consumption vs. Junction Temperature
Figure 8. Device Switching Current
Consumption vs. Junction Temperature
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150
NCL30105
1.10
600
1.08
590
tLEB, LEADING EDGE BLANKING
DURATION (ns)
VILIM, CURRENT SENSE VOLTAGE
THRESHOLD (V)
TYPICAL CHARACTERISTICS
1.06
1.04
1.02
1.00
0.98
0.96
0.94
0.92
0.90
−50
−25
0
25
50
75
100
125
580
570
560
550
540
530
520
510
500
−50
150
−25
TJ, JUNCTION TEMPERATURE (°C)
50
75
100
125
150
Figure 10. Leading Edge Blanking Duration vs.
Junction Temperature
100
24
90
ISSTART, SOFT−START CHARGE
CURRENT (mA)
tILIM, CURRENT SENSE
PROPAGATION DELAY (ns)
25
TJ, JUNCTION TEMPERATURE (°C)
Figure 9. Current Sense Voltage Threshold vs.
Junction Temperature
80
70
60
50
40
30
20
−50
−25
0
25
50
75
100
125
23
22
21
20
19
18
17
16
−50
150
−25
TJ, JUNCTION TEMPERATURE (°C)
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (°C)
Figure 11. Current Sense Propagation Delay
vs. Junction Temperature
Figure 12. Soft−Start Charge Current vs.
Junction Temperature
3.15
1.15
Rtoff = 5 kW
3.10
1.10
toff, OFF TIME (ms)
Iratio, SOFT−START VOLTAGE TO
PEAK CURRENT SET POINT RATIO
0
3.05
3.00
2.95
2.90
1.05
1.00
0.95
0.90
2.85
−50
−25
0
25
50
75
100
125
150
0.85
−50
TJ, JUNCTION TEMPERATURE (°C)
−25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (°C)
Figure 13. Soft−Start Voltage to Peak Current
Set Point Ratio vs. Junction Temperature
Figure 14. Off Time vs. Junction Temperature
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NCL30105
TYPICAL CHARACTERISTICS
14.0
toff(MAX), MAXIMUM OFF TIME (ms)
0.6
0.5
0.4
0.3
0.2
−25
0
25
50
75
100
13.0
12.5
12.0
11.5
11.0
10.5
10.0
9.0
−50
150
125
9.5
−25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 15. Minimum Off Time vs. Junction
Temperature
Figure 16. Maximum Off Time vs. Junction
Temperature
13
12
11
10
9
8
7
6
5
4
3
2
1
0
2.5
VILIM(fault), OVERCURRENT CURRENT
SENSE VOLTAGE THRESHOLD (V)
150
50
ton(MAX), MAXIMUM ON TIME (ms)
toff, OFF TIME (ms)
0.1
−50
13.5
12.5
22.5
32.5
42.5
52.5
45
40
35
30
25
20
−50
62.5
−25
0
25
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
Figure 17. Off Time vs. toff Pin Resistor
Figure 18. Maximum On Time vs. Junction
Temperature
1.80
150
2.5
1.75
1.70
1.65
1.60
1.55
1.50
1.45
1.40
−50
50
Rtoff, toff PIN RESISTOR (kW)
VDIM, DIMMING VOLTAGE
THRESHOLDS (V)
toff(MIN), MINIMUM OFF TIME (ms)
0.7
−25
0
25
50
75
100
125
150
VDIM(H)
2.0
1.5
VDIM(L)
1.0
0.5
0.0
−50
TJ, JUNCTION TEMPERATURE (°C)
−25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (°C)
Figure 19. Overcurrent Current Sense Voltage
Threshold vs. Junction Temperature
Figure 20. Dimming Thresholds vs. Junction
Temperature
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NCL30105
TYPICAL CHARACTERISTICS
3.0
toff, OFF TIME (ms)
2.5
2.0
1.5
1.0
0.5
0.0
2.5
3.5
4.5
5.5
6.5
7.5
8.5
9.5
Rtoff, toff PIN RESISTOR (kW)
Figure 21. Zoomed In Off Time vs. toff Pin
Resistor
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10.5
NCL30105
Application Information
Introduction
NCL30105 implements a current−mode architecture
operated with a constant off time. The internal current set
point and the external sense resistor determine the on time
duration. The off time duration is adjusted with a resistor
connected from the toff pin to ground. The constant off time
operation enables deep continuous conduction mode
operation without requiring slope compensation. The DIM
pin enables the use of a PWM signal to modulate the
switching pattern and adjust the average luminosity. The
SSTART pin creates a soft−start that reduces the stress on the
power components during startup and enables the use of an
analog dimming signal to set the peak current by adjusting
the SSTART pin voltage.
• Constant Off Time Peak Current−Mode Operation:
The constant off time technique enables the controller
to operate a converter in deep continuous conduction
mode without requiring slope compensation. The
constant off time technique is inherently immune to
sub−harmonic oscillations.
• Off Time Adjustment: A pull−down resistor
connected to the toff pin sets the off time duration.
• Maximum On Time Protection: an internal circuit
monitors the drive signal on time duration. If the drive
on time duration reaches ton(MAX), the fault up/down
counter is incremented by 1. If the drive on time
duration reaches ton(MAX) during the next clock cycle,
the counter is incremented again. If the drive on time
duration does not reach ton(MAX) due to the current
comparator being triggered during the next drive on
time, the counter is decremented by 1. This sequence
continues until the counter reaches 8. If the counter
reaches 8, the NCL30105 is immediately latched off.
When VCC is forced below VCC(off) and then above
VCC(on), the latch is reset.
• LED Short−Circuit Protection: If the CS pin voltage
increases above VILIM(fault), the overcurrent comparator
is triggered, which turns off the drive and increments
the fault up/down counter by 1. If the overcurrent
comparator is triggered again during the next drive on
time, the counter is incremented again. If the
overcurrent comparator is not triggered due to the
current comparator being triggered during the next
drive on time, the counter is decremented by 1. This
sequence continues until the counter reaches 8. If the
counter reaches 8, the part is immediately latched off.
When VCC is forced below VCC(off) and then above
VCC(on), the latch is reset.
• Power On Delay: When VCC reaches VCC(on), the
tstart(delay) timer begins counting, during which the
drive is disabled. When tstart(delay) elapses, the SSTART
•
•
•
•
•
pin current source is enabled and the soft−start
sequence begins.
Soft−Start Operation: A capacitor connected to the
SSTART pin is charged by an internal current source
after the tstart(delay) timer period has elapsed. The
soft−start period is completed when the SSTART pin
voltage reaches VILIM*Iratio. The soft−start capacitor is
discharged during the tstart(delay) to ensure the SSTART
pin voltage begins charging from zero.
Peak Adjustment: Analog dimming is achieved by
forcing the SSTART pin below VILIM*Iratio, which
lowers the peak current set point. Note: even if the
SSTART pin is forced to 0 V, there is still a minimum
on time every switching cycle. Under this condition, the
minimum on time is the current sense leading edge
blanking time plus the propagation delay to turn off the
MOSFET and the off time is determined by the toff
resistor value.
Leading Edge Blanking: an internal circuit blinds the
current sense comparator for a few hundred
nanoseconds when the output drive goes high. The LEB
ensures that controller remains insensitive to the
turn−on voltage spikes observed on the CS pin due to
the free−wheel diode recovery time.
Dimming Input: a dedicated pin is provided to PWM
modulate the LED current to reduce the LED
luminosity. The circuit is driven on and off via a 3.3−V
logic level signal. The DIM pin can also be used as an
enable/disable pin, since the switching is disabled when
there is a logic low signal applied to this pin.
Thermal Shutdown: if the junction temperature of the
controller exceeds an internal threshold, the drive is
disabled. The drive remains disabled until the junction
temperature decreases below the internal hysteresis
threshold. The disabling of the drive protects the
controller from destruction due to overheating.
Startup Sequence
When VCC reaches VCC(on), the NCL30105 maintains the
drive low and the soft−start capacitor (CSSTART, connected
to the SSTART pin) remains pulled to ground by the internal
pull−down switch until the startup delay (tstart(delay))
elapses. Once the tstart(delay) period has elapsed, the drive is
enabled and a soft−start sequence begins. The internal
current source begins charging CSSTART and the voltage on
the SSTART pin (VSSTART) begins increasing. The peak
current set point is equal to VSSTART divided by Iratio. When
VSSTART reaches the voltage that sets the maximum peak
current (VSSTART = VILIM*Iratio), the soft−start sequence is
complete and the peak current set point is equal to VSSTART
divided by Iratio. Figure 22 describes a typical start−up
sequence.
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NCL30105
VCC
VCC(on)
VCC(off)
Internal
timer
tstart(delay)
reset
reset
VDRV
VSSTART
VSSTART(open)
VSSTART = VILIM * Iratio
User changes
the setpoint
VCS
Soft−Start
Sequence
VILIM
Constant Peak
Soft−Start
Sequence
Variable Peak
Figure 22. A Typical Startup Sequence
Soft−Start Pin
source, the current into the SSTART pin must be limited to
ensure that the maximum current rating is not exceeded. It
is recommended to set VSSTART by connecting a diode as
shown in Figure 23. Using this configuration, the SSTART
capacitor value to set a 15 ms soft−start duration (tSSTART)
is calculated using Equation 1:
The soft−start internal section is shown in Figure 23. The
soft−start sequence is implemented using a current source
that charges an external capacitor. The relationship between
the capacitor voltage and the peak current voltage set point
is Iratio. The maximum peak current set point is
VSSTART/Iratio. For luminosity balancing purposes, it is
possible to force the voltage on the SSTART pin from an
external source. When forcing VSSTART with an external
(eq. 1)
I
@t
20 m @ 15 m
C SSTART + SSTART SSTART +
+ 0.1 mF
3
I ratio
http://onsemi.com
12
NCL30105
latch reset
VSSTART(open)
Current
comparator
ISSTART
−
+
SSTART
/
Iratio
sensed
current
D2
1N4148
peak current
setpoint control
CSSTART
VILIM
tstart(delay)
Timer reset
UVLO reset
Figure 23. The Soft−start Block Configuration to Set the Peak Current Setpoint
Constant Off time Generator
peak current threshold, the inductor value, and the input
voltage. Unlike traditional peak current mode control, the
fixed off time technique is not susceptible to sub−harmonic
instability as shown in Figure 24:
The controller operates with a constant off time technique.
The off time technique is implemented by forcing a constant
off time with the on time being set by the combination of the
IL(t)
constant
DIL
constant
on
off
Figure 24. The Constant Off Time Technique is Immune to
Sub−Harmonic Instabilities without Ramp Compensation
The constant off time generator follows the principle
sketched in Figure 25 where an internal timer is started at the
end of each on time. Once the off time generator has elapsed,
it begins the next DRV pulse. The off time is programmed
by connecting a resistor from the toff pin to ground. The off
time range is from 0.5 ms to 10 ms.
In Figure 24, the perturbation is corrected in one switching
cycle, despite a duty ratio greater than 50%. This benefit
enables the designer to exclude slope compensation when
operating the inductor in a deep continuous conduction
mode.
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13
NCL30105
on
Drive
off
Internal
timer
adjustable
constant
Figure 25. A Timer is Started at the End of the On Time Duration
Protection
ton(MAX). The maximum on time limitation may occur if the
input voltage is too low or if the CS pin is shorted to ground.
After 8 consecutive maximum on times events, the
controller is latched as shown in Figure 26.
The NCL30105 includes several methods of protection.
One of the protection features is the maximum on time
limitation, which protects the system if the CS pin does not
receive a signal. The on time is internally limited to
Fault
occurs
here
ton(MAX)
Count 1
Controller is
latched after
the 8th event
Smaller pulse:
countdown
2
1
2
3
4
5
6
7
8
Figure 26. The Protection Feature Limits the Maximum On Time
and Disables the Controller During a Fault
in the circuit. The LEB circuit “blanks” the noise to ensure
that the current and overcurrent comparators are not
inadvertently triggered. If the LEB circuit is omitted, the
noise causes the DRV to turn off before the required peak
current is reached as shown in Figure 28. This causes the
system to operate erratically. When the LEB circuit is
included, the noise is “blanked” by blinding the current
comparator for the LEB duration (tLEB) and the required
peak current is reached as shown in Figure 29. The inclusion
of the LEB circuits prevents the erratic operation of the
system.
Another protection feature is the overcurrent detection.
The overcurrent detection activates when a short−circuit
occurs in the inductor and LED string. To prevent false
In latched mode, the controller consumes a low current
and waits for a complete VCC cycle (VCC decreases to less
than VCC(off) and then increased to greater than VCC(on)) to
resume operation. The tracking of the fault events is
implemented with an up/down counter. The counter is
incremented by 1 when the ton(MAX) duration ends the
driving pulse. The counter is decremented by 1 when a
normal reset occurs via the current comparator. When the
counter reaches 0, it stores this value and waits for an up
pulse to change state.
The NCL30105 includes Leading Edge Blanking (LEB)
circuits to prevent inadvertent triggering of the current and
overcurrent comparators. When the DRV pin goes high,
noise is generated on the CS pin due to the parasitic elements
http://onsemi.com
14
NCL30105
detection during surge tests, the controller uses the same
counter as the maximum on time limitation. Due to the two
different LEB circuits (tLEB and tLEB(fault)) configuration, if
there is a severe overload, the overcurrent comparator is
triggered first and the counter is incremented. If the
overcurrent comparator is not triggered during the next
clock cycle, the counter is decremented by the current
comparator. Figure 27 depicts the logical arrangement
inside the controller. In the presence of a fast rising signal,
the overcurrent comparator is triggered first since tLEB(fault)
VILIM
< tLEB. When the overcurrent comparator output goes high,
it resets the PWM latch and increments the counter. The
counter can no longer increment or decrement until the next
switching cycle. If during the time the overcurrent
comparator output is high, tLEB elapses and causes the
current comparator output to go high, the output of the
current comparator is ignored due to the AND gate
connection. Figure 30 illustrates the operation of the CS
logic during an overcurrent fault. Only one up count or one
down count is made per switching cycle.
Current
Comparator
−
latch
off
+
CS
tLEB
tLEB(fault)
Overcurrent
Comparator
+
down
Nfault
up
Count to Nfault
−
VILIM(fault)
ton >
ton(MAX)
Q
PWM reset
Figure 27. CS Internal Logic
VCS(t)
VCS(t)
Required peak current
Noise “blanked”
tILIM
VILIM
tILIM
t
VILIM
Comparator
Output
DRV
t
down
Inadvertant trigger
tLEB
VILIM
VILIM
Comparator
Output
t
DRV
DRV turned off
before required
peak current is
reached
down
tLEB
t
t
t
Figure 29. Circuit with Leading Edge Blanking
Figure 28. Circuit without Leading Edge Blanking
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15
NCL30105
VCS(t)
VILIM(fault)
tILIM(fault)
VILIM
tILIM
t
VILIM(fault)
Comparator
up
tLEB(fault)
VILIM
Comparator
t
Ignored
down
tLEB
tLEB
t
DRV
off
t
Figure 30. The Overcurrent Comparator Increments the Counter during a Fault
Minimum Dimming Duty Cycle
combination. The minimum dimming duty cycle is
described in Figure 31 shown below. The first DRV pulse
during the dimming duty cycle reaches the maximum on
time, but the second DRV pulse does not and is turned off by
the current comparator. If the dimming on time (duty cycle)
is reduced, the second DRV pulse is turned off by the DIM
pin voltage, the current comparator is not triggered, and the
NCL30105 latches after 8 dimming cycles.
During each DIM cycle if the max on time limit is reached
a certain number of times, the current comparator must be
triggered the same number of times to reset the fault counter.
For each DIM cycle, if the maximum on time limit is reached
a greater number of times than the number of times the
current comparator is triggered, the fault counter is not reset
and is incremented each DIM cycle until the fault count is
reached (Nfault = 8). This results in a minimum dimming
duty cycle for a particular LED string voltage and inductor
Figure 31. Minimum Dimming Duty Cycle
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16
NCL30105
Example Calculation
R toff [kW] +
The design begins with the system requirements. The
following are the system requirements of an example
system:
Input Voltage (Vin) = 80 V
Number of LEDs = 18
LED forward Voltage = 3.33 V
LED string Voltage (VLED) = 60 V
LED average current (ILED) = 350 mA
Where toff is entered in ms and Rtoff is calculated in kW.
R toff + 2.5 * 0.1214 + 12.76 kW
0.1864
Rtoff is selected as 12.7 kW.
The inductor value is calculated using the off time:
L+
LED ripple current (DILED) = 150 mA (±75 mA)
Operating frequency = 100 kHz
The switching period is calculated using the target
operating frequency:
T SW + 1
f SW
L+
(eq. 1)
Ǔ
ǒ
(eq. 3)
60 @ 2.5 m
+ 1 mH
150m
I LED(peak) + I LED ) dILED
2
(eq. 4)
I LED(peak) + 350m ) 150m + 425 mA
2
The off time (toff) is calculated using the LED string
voltage, input voltage, and switching period:
ǒ
V LED @ t off
dILED
The LED peak current (ILED(peak)) is also the inductor
peak current and is calculated using the average LED current
and the LED ripple current:
T SW + 1 + 10 ms
100k
V
t off + 1 * LED @ T SW
V in
t off [ms] * 0.1214
0.1864
It is critical that the inductor saturation current is greater
than the peak current. Sufficient margin is generally set to
20%. For 20% margin, the inductor should be selected to
have a saturation current greater than 510 mA. The sense
resistor (Rsense) value is calculated using the peak current:
(eq. 2)
Ǔ
t off + 1 * 60 @ 10 ms + 2.5 ms
80
R sense +
To set toff, the following calculation is used based on the
on the approximation of the linear region of the toff vs. Rtoff
transfer function as shown in Figure 17:
R sense +
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17
V ILIM
I LED(peak)
1 + 2.35 W
0.425
(eq. 5)
NCL30105
Typical Application Schematic:
Figure 32. Typical Application Schematic
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18
NCL30105
Thermal Considerations:
Layout Tips:
The designer must ensure that the junction temperature of
the NCL30105 remains less than the value of the maximum
operating junction temperature in the Maximum Ratings
Table for the worst−case operating conditions. The
maximum junction temperature is calculated using the
estimated current consumption. The estimated current
consumption is calculated using the following assumptions:
1. The switching frequency is at the maximum of
500 kHz (fSW(MAX)).
2. The Vcc is at the maximum of 22 V (VCC(MAX))
3. The gate of the MOSFET is modeled using a 1 nF
capacitor (Cg)
4. The non−switching bias current is at the maximum
of 1.56 mA (ICC2)
Using these assumptions, the current consumption is
calculated:
Careful layout is critical for all switch−mode power
supply design. Successful layout includes special
consideration for noise sensitive pins of the controller IC.
For the NCL30105 the following pins should be carefully
routed:
1. Vcc: This pin requires a ceramic decoupling
capacitor (typically 100 nF) and a electrolytic
capacitor (typically 10 mF) to ensure that IC supply
is constant and decoupled from high frequency
noise generated by switching currents.
2. toff: This pin requires a resistor connected to
ground to set the off time. It is not recommended
to leave this pin open or shorted to ground to set
the off time. The connection from the toff pin to
the resistor and from the resistor to ground must be
made as short as possible and connected directly to
the NCL30105 GND pin. High noise nodes and
traces must be routed as far away from this pin as
possible.
3. SSTART: A capacitor is connected to this pin to
set the Soft−Start time. The connection from the
SSTART pin to the capacitor and from the
capacitor to ground must be made as short as
possible.
4. DIM: A decoupling capacitor may need to be
connected to this pin if it coupled to high noise
traces. The connection from the DIM pin to the
capacitor and from the capacitor to ground must be
made as short as possible. The addition of the
capacitor may affect the response of time of the
DIM signal to the DRV output.
5. CS: If LEB period is not long enough to ensure
predictable operation, a small RC filter may need
to be connected to this pin. The addition of the RC
filter affects the current set point accuracy.
6. DRV: The trace that connects the DRV pin to the
MOSFET must be made as short as possible to
reduce the parasitic inductance of the trace. The
DRV pin switches high currents and the parasitic
inductance can cause higher than expected
voltages to be applied to the gate of the MOSFET.
A small resistor is recommended to be connected
in series with the DRV pin to the gate. The resistor
reduces the effect of the parasitic inductance. The
addition of the resistor may affect the switching
losses of the MOSFET.
I CC(TJMAX) + ǒC g @ V CC @ f SW(MAX)Ǔ ) I CC2
I CC(TJMAX) + (1 n @ 22 @ 500 k) ) 1.56 m + 12.56 mA
The power dissipation of the NCL30105 is calculated:
P (TJMAX) + I CC(TJMAX) @ V CC(MAX)
P (TJMAX) + 12.56 m @ 22 + 276 mW
The junction temperature is calculated using the
maximum thermal resistance (RqJA(MAX)) with the
minimum PCB copper area from the maximum ratings table:
T J(rise) + P (TJMAX) @ R qJA(MAX)
T J(rise) + 0.276 @ 178 + 40 oC
Assuming a maximum ambient temperature of 70°C
(Tambient), the maximum junction temperature is calculated:
T J(MAX) + T J(rise) ) T ambient
T J(MAX) + 49 ) 70 + 119 oC
Since this is less than the TSHDN parameter with sufficient
margin, the design is acceptable.
http://onsemi.com
19
NCL30105
Recommended Layout:
Figure 33. Top Layout
Figure 34. Bottom Layout
http://onsemi.com
20
NCL30105
The critical components for layout are the following:
1. R2 (Rtoff): This resistor sets the off time. The
placement of this resistor is such that the distance
to the pin and IC ground is minimized. The
footprints R1 and R3 are optional to increase the
precision of the resistance value.
2. C5 (CVCC): This is the Vcc supply decoupling
capacitor. The placement of this capacitor is such
that the distance to the pin and IC ground is
minimized. The recommended minimum value for
this capacitor is 100 nF.
3. C8 (CSSTART): This capacitor sets the soft−start
time. The placement of this capacitor is such that
the distance to the pin and IC ground is
minimized.
The layout includes options to use a surface mount
inductor (footprint L2) and MOSFET (footprint M2).
http://onsemi.com
21
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
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