NCP1612A2DR2G

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Other names and brands may be claimed as the property of others. NCP1612A, NCP1612B, NCP1612A1, NCP1612A2, NCP1612A3, NCP1612B2 Enhanced, High‐Efficiency Power Factor Controller www.onsemi.com The NCP1612 is designed to drive PFC boost stages based on an innovative Current Controlled Frequency Fold-back (CCFF) method. In this mode, the circuit classically operates in Critical conduction Mode (CrM) when the inductor current exceeds a programmable value. When the current is below this preset level, the NCP1612 linearly decays the frequency down to about 20 kHz when the current is null. CCFF maximizes the efficiency at both nominal and light load. In particular, the stand-by losses are reduced to a minimum. Like in FCCrM controllers, an internal circuitry allows near-unity power factor even when the switching frequency is reduced. Housed in a SO−10 package, the circuit also incorporates the features necessary for robust and compact PFC stages, with few external components. SOIC−10 CASE 751BQ MARKING DIAGRAM 10 1612x ALYW G General Features 1 • Near-unity Power Factor • Critical Conduction Mode (CrM) • Current Controlled Frequency Fold-back (CCFF): Low Frequency 1612x A L Y W G Operation is Forced at Low Current Levels • On-time Modulation to Maintain a Proper Current Shaping in CCFF • • • • • • • • • • Mode Skip Mode Near the Line Zero Crossing Fast Line/Load Transient Compensation (Dynamic Response Enhancer) Valley Turn On High Drive Capability: −500 mA/+800 mA VCC Range: from 9.5 V to 35 V Low Start-up Consumption Six Versions: NCP1612A, B, A1, A2, A3 and B2 (see Table 1) Line Range Detection pfcOK Signal This is a Pb-Free Device Safety Features • Separate Pin for Fast Over-voltage Protection (FOVP) • • • • • • • January, 2018 − Rev. 11 PIN CONNECTIONS FOVP Feedback 1 pfcOK VCC Vcontrol DRV Vsense GND CS/ZCD FFcontrol (Top View) ORDERING INFORMATION See detailed ordering and shipping information on page 30 of this data sheet. • Low Duty-cycle Operation if the Bypass Diode is for Redundancy Soft Over-voltage Protection Brown-out Detection Soft-start for Smooth Start-up Operation (A, A1, A2 and A3 Versions) Over Current Limitation Disable Protection if the Feedback is Not Connected Thermal Shutdown Latched Off Capability © Semiconductor Components Industries, LLC, 2016 = Specific Device Code x = A, A1, A2, A3, B or B2 = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package • • • shorted Open Ground Pin Fault Monitoring Saturated Inductor Protection Detailed Safety Testing Analysis (Refer to Application Note AND9079/D) Typical Applications • PC Power Supplies • All Off Line Appliances Requiring Power Factor Correction 1 Publication Order Number: NCP1612/D NCP1612A, NCP1612B, NCP1612A1, NCP1612A2, NCP1612A3, NCP1612B2 Figure 1. Typical Application Schematic Table 1. FIVE NCP1612 VERSIONS Part Number Typical UVLO Hysteresis Condition for BUV Tripping (typical threshold) Maximum Dead-time (typical value) Condition for Latching-off (typical threshold) UVP2 if VFOVP 7.5 V YES Disabled until pfcOK turns high NCP1612A1 1.5 V VFOVP < 40%.VREF 48.5 ms VpfcOK > 7.5 V YES Disabled until pfcOK turns high NCP1612A2 1.5 V VFB < 76%.VREF 48.5 ms VFOVP > 107%.VREF NO Disabled until pfcOK turns high NCP1612A3 1.5 V VFOVP < 40%.VREF 41.5 ms VpfcOK > 7.5 V YES Disabled until pfcOK turns high NCP1612B 8.0 V VFOVP < 76%.VREF 48.5 ms VpfcOK > 7.5 V YES Enabled as soon as the circuit turns on to speed-up the startup phase NCP1612B2* 8.0 V VFB < 76%.VREF 48.5 ms VFOVP > 107%.VREF NO Enabled as soon as the circuit turns on to speed-up the startup phase *Please contact local sales representative for availability Recommended Applications: • The NCP1612B and NCP1612B2 large UVLO hysteresis (6 V minimum) avoids the need for large VCC capacitors and • • help shorten the start-up time without the need for too dissipative start-up elements in self-powered PFC applications (where high-impedance start-up resistors are generally implemented to pre-charge the VCC capacitor). The A, A1, A2 and A3 versions are preferred in applications where the circuit is fed by an external power source (from an auxiliary power supply or from a downstream converter). Its maximum start-up level (11.25 V) is set low enough so that the circuit can be powered from a 12-V voltage rail. A2 and B2 versions are to be preferred when a signal other than a portion of the output voltage is applied to the FOVP pin (e.g., a voltage representative of the output voltage provided by an auxiliary winding) and/or if the pfcOK pin voltage must be able to rise up to the VCC level without latching the part. Note that with the A2 and B2 versions, the fast OVP protection latches-off the circuit when triggered. www.onsemi.com 2 NCP1612A, NCP1612B, NCP1612A1, NCP1612A2, NCP1612A3, NCP1612B2 Table 2. MAXIMUM RATINGS (Note 1) Symbol Pin Value Unit VCC 9 Power Supply Input −0.3, +35 V FOVP 1 FOVP Pin −0.3, +10 V Rating Feedback 2 Feedback Pin VCONTROL 3 VCONTROL Pin (Note 2) −0.3, +10 V −0.3, VCONTROLMAX V Vsense 4 Vsense Pin (Note 3) −0.3, +10 V FFcontrol 5 FFcontrol Pin −0.3, +10 V CS/ZCD 6 Input Voltage (Note 4) Current Injected to Pin 4 (Note 5) −0.3, +35 +5 V mA DRV 8 Driver Voltage (Note 2) Driver Current −0.3, VDRV −500, +800 V mA pfcOK 10 pfcOK Pin −0.3, VCC V 550 145 mW °C/W −40 to +125 °C PD RqJA TJ Power Dissipation and Thermal Characteristics Maximum Power Dissipation @ TA = 70°C Thermal Resistance Junction-to-Air Operating Junction Temperature Range 150 °C −65 to 150 °C 300 °C 1 − ESD Capability, Human Body Model (Note 6) > 2000 V ESD Capability, Machine Model (Note 6) > 200 V ESD Capability, Charged Device Model (Note 6) 1000 V TJmax Maximum Junction Temperature TSmax Storage Temperature Range TLmax Lead Temperature (Soldering, 10s) MSL Moisture Sensitivity Level Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. This device contains latch-up protection and exceeds 100 mA per JEDEC Standard JESD78. 2. “VCONTROLMAX” is the pin3 clamp voltage and “VDRV” is the DRV clamp voltage (VDRVhigh). If VCC is below VDRVhigh, “VDRV” is VCC. 3. Recommended maximum Vsense voltage for optimal operation is 4.5 V. 4. The recommended maximum voltage not to exceed remains −0.3 V but Figure 2 short negative spike on the CS/ZCD pin is typically acceptable. However, it implies the full characterization of the circuit embedding the NCP1612, including at maximum temperature conditions, during which no erratic operation is observed. If otherwise noted, we recommend to clamp the negative voltage on the CS/ZCD pin to avoid carrier injection within the die. 5. Maximum CS/ZCD current that can be injected into pin6 (see Figure 3). 6. This device(s) contains ESD protection and exceeds the following tests: Human Body Model 2000 V per JEDEC Standard JESD22−A114E Machine Model Method 200 V per JEDEC Standard JESD22−A115−A Charged Device Model Method 1000 V per JEDEC Standard JESD22−C101E VCS/ZCD (t) 0V −0.3 V −1.0 V 250 ns Figure 2. www.onsemi.com 3 NCP1612A, NCP1612B, NCP1612A1, NCP1612A2, NCP1612A3, NCP1612B2 NCP1612 VCC R1 Ipin6 ESD Diode 2 kW CS/ZCD Maintain Ipin6 below 5 mA ESD Diode GND CS/ZCD Circuitry 7.4 V Figure 3. Table 3. TYPICAL ELECTRICAL CHARACTERISTICS (Conditions: VCC = 15 V, TJ from −40°C to +125°C, unless otherwise specified) Symbol Rating Min Typ Max 9.75 15.80 10.50 17.00 11.25 18.20 Minimum Operating Voltage, VCC falling 8.5 9.0 9.5 Hysteresis (VCC (on ) − VCC (off )) A, A1, A2 and A3 versions B and B2 versions 0.75 6.00 1.50 8.00 − − VCC level below which the circuit resets 2.5 4.0 6.0 Unit START-UP AND SUPPLY CIRCUIT VCC(on) VCC(off) VCC(HYST) VCC(reset) Start-up Threshold, VCC increasing: A, A1, A2 and A3 versions B and B2 versions V V V V ICC(start) Start-up Current, VCC = 9.4 V − 20 50 mA ICC(op)1 Operating Consumption, no switching (VSENSE pin being grounded) − 0.5 1.0 mA ICC(op)2 Operating Consumption, 50 kHz switching, no load on DRV pin − 2.0 3.0 mA CURRENT CONTROLLED FREQUENCY FOLD-BACK TDT1 Dead-time, VFFcontrol = 2.60 V (Note 7) − − 0 ms TDT2 Dead-time, VFFcontrol = 1.75 V 14 18 22 ms TDT3 Dead-time, VFFcontrol = 1.00 V 32 38 44 ms TDT4 Dead-time, VFFcontrol = VSKIP_L + 30 mV (NCP1612A3 Only) @ 25°C Over the Temperature Range 34.0 32.0 41.5 41.5 45.0 47.0 ms IDT1 FFcontrol Pin current, Vsense = 1.4 V and Vcontrol maximum 180 200 220 mA IDT2 FFcontrol Pin current, Vsense = 2.8 V and Vcontrol maximum 110 135 160 mA VSKIP−H FFcontrol pin Skip Level, VFFcontrol rising All Versions Except NCP1612A3 NCP1612A3 − − 0.75 1.00 0.85 1.05 V VSKIP−L FFcontrol pin Skip Level, VFFcontrol falling All Versions Except NCP1612A3 NCP1612A3 0.55 0.85 0.65 0.90 − − V HSKIP−L FFcontrol pin Skip Hysteresis 50 − − mV GATE DRIVE (Note 8) TR Output voltage rise-time @ CL = 1 nF, 10−90% of output signal − 30 − ns TF Output voltage fall-time @ CL = 1 nF, 10−90% of output signal − 20 − ns ROH Source resistance − 10 − W ROL Sink resistance − 7.0 − W Peak source current, VDRV = 0 V (guaranteed by design) − 500 − mA ISOURCE − 800 − mA VDRVlow ISINK Peak sink current, VDRV = 12 V (guaranteed by design) DRV pin level at VCC close to VCC (off ) with a 10 kW resistor to GND 8.0 − − V VDRVhigh DRV pin level at VCC = 35 V (RL = 33 kW, CL = 220 pF) 10 12 14 V www.onsemi.com 4 NCP1612A, NCP1612B, NCP1612A1, NCP1612A2, NCP1612A3, NCP1612B2 Table 3. TYPICAL ELECTRICAL CHARACTERISTICS (continued) (Conditions: VCC = 15 V, TJ from −40°C to +125°C, unless otherwise specified) Symbol Rating Min Typ Max 2.44 2.42 2.50 2.50 2.54 2.54 Unit REGULATION BLOCK VREF Feedback Voltage Reference: @ 25°C Over the temperature range IEA Error Amplifier Current Capability GEA Error Amplifier Gain V VCONTROL VCONTROL Pin Voltage: − @ VFB = 2 V −VCONTROLMAX −VCONTROLMIN − @ VFB = 3 V − ±20 − mA 110 220 290 mS − − 4.5 0.5 − − V VOUTL/VREF Ratio (VOUT Low Detect Threshold/VREF ) (guaranteed by design) 95.0 95.5 96.0 % HOUTL/VREF Ratio (VOUT Low Detect Hysteresis/VREF ) (guaranteed by design) − − 0.5 % 180 220 250 mA Current Sense Voltage Reference 450 500 550 mV TLEB,OCP Over-current Protection Leading Edge Blanking Time (guaranteed by design) 100 200 350 ns TLEB,OVS “OverStress” Leading Edge Blanking Time (guaranteed by design) 50 100 170 ns TOCP Over-current Protection Delay from VCS/ZCD > VCS(th) to DRV low (dVCS/ZCD / dt = 10 V/ms) − 40 200 ns IBOOST VCONTROL Pin Source Current when (VOUT Low Detect) is activated CURRENT SENSE AND ZERO CURRENT DETECTION BLOCKS VCS(th) VZCD(th)H Zero Current Detection, VCS/ZCD rising 675 750 825 mV VZCD(th)L Zero Current Detection, VCS/ZCD falling 200 250 300 mV VZCD(hyst) Hysteresis of the Zero Current Detection Comparator 375 500 − mV RZCD/CS VZCD(th)H over VCS(th) Ratio 1.4 1.5 1.6 − VCL(pos) CS/ZCD Positive Clamp @ ICS/ZCD = 5 mA − 15.6 − V IZCD(bias) Current Sourced by the CS/ZCD Pin, VCS/ZCD = VZCD (th )H 0.5 − 2.0 mA IZCD(bias) Current Sourced by the CS/ZCD Pin, VCS/ZCD = VZCD (th )L 0.5 − 2.0 mA TZCD (VCS/ZCD < VZCD (th )L ) to (DRV high) − 60 200 ns TSYNC Minimum ZCD Pulse Width − 110 200 ns TWDG Watch Dog Timer 80 200 320 ms Watch Dog Timer in “Overstress” Situation 400 800 1200 ms Time-out Timer 20 30 50 ms Source Current for CS/ZCD pin impedance Testing − 250 − mA Duty Cycle, VFB = 3 V, Vcontrol pin open − − 0 % TWDG(OS) TTMO IZCD(gnd) STATIC OVP DMIN ON-TIME CONTROL TON(LL) Maximum On Time, Vsense = 1.4 V and Vcontrol maximum (CrM) 22.0 25.0 29.0 ms TON(LL)2 On Time, Vsense = 1.4 V and Vcontrol = 2.5 V (CrM) 10.5 12.5 14.0 ms TON(HL) Maximum On Time, Vsense = 2.8 V and Vcontrol maximum (CrM) 7.3 8.5 9.6 ms TON(LL)(MIN) Minimum On Time, Vsense = 1.4 V (not tested, guaranteed by characterization) − − 200 ns TON(HL)(MIN) Minimum On Time, Vsense = 2.8 V (not tested, guaranteed by characterization) − − 100 ns Ratio (soft OVP Threshold, VFB rising) over VREF (VsoftOVP /VREF ) (guaranteed by design) 104 105 106 % Ratio (Soft OVP Hysteresis) over VREF (guaranteed by design) 1.5 2.0 2.5 % 8 12 16 % FEED-BACK OVER AND UNDER-VOLTAGE PROTECTION (SOFT OVP AND UVP) RsoftOVP RsoftOVP(HYST) RUVP Ratio (UVP Threshold, VFB rising) over VREF (VUVP /VREF ) (guaranteed by design) RUVP(HYST) Ratio (UVP Hysteresis) over VREF (guaranteed by design) − − 1 % FB Pin Bias Current @ VFB = VsoftOV P and VFB = VUVP 50 200 450 nA (IB)FB www.onsemi.com 5 NCP1612A, NCP1612B, NCP1612A1, NCP1612A2, NCP1612A3, NCP1612B2 Table 3. TYPICAL ELECTRICAL CHARACTERISTICS (continued) (Conditions: VCC = 15 V, TJ from −40°C to +125°C, unless otherwise specified) Symbol Rating Min Typ Max Unit FAST OVER VOLTAGE PROTECTION AND BULK UNDER-VOLTAGE PROTECTION (FAST OVP AND BUV) VfastOVP Fast OVP Threshold, VFOVP rising 2.560 2.675 2.750 V RfastOVP1 Ratio (Fast OVP Threshold, VFOVP rising) over (soft OVP Threshold, VFB rising) (VfastOVP /VsoftOVP ) (guaranteed by design) 101.5 102.0 102.5 % RfastOVP2 Ratio (Fast OVP Threshold, VFOVP rising) over VREF (VfastOVP /VREF ) (guaranteed by design) 106 107 108 % 1.80 0.90 1.80 1.90 1.00 1.90 2.00 1.10 2.00 Ratio (BUV Threshold) over VREF (VBUV/VREF) NCP1612A, NCP1612B, VFOVP falling NCP1612A1, NCP1612A3, VFOVP falling NCP1612A2 and NCP1612B2, VFB falling 74 37 74 76 40 76 78 43 78 Pin1 Bias Current @ Vpin1 = VfastOVP (all versions) @ Vpin1 = VBUV (NCP1612A, NCP1612A1, NCP1612B, NCP1612A3 only) 50 50 200 200 450 450 0.2 0.3 0.4 V VBUV RBUV (IB)FOVP/BUV VUVP2 BUV Threshold: NCP1612A, NCP1612B, VFOVP falling NCP1612A1, NCP1612A3, VFOVP falling NCP1612A2 and NCP1612B2, VFB falling V % UVP2 Threshold for Floating Pin Detection (NCP1612A, NCP1612A1, NCP1612A3 and NCP1612B only) nA BROWN-OUT PROTECTION AND FEED-FORWARD VBOH Brown-out Threshold, Vsense rising 0.96 1.00 1.04 V VBOL Brown-out Threshold, Vsense falling 0.86 0.90 0.94 V VBO(HYST) Brown-out Comparator Hysteresis 60 100 − mV TBO(blank) Brown-out Blanking Time 35 50 65 ms VCONTROL Pin Sink Current, Vsense < VBOL 40 50 60 mA VHL High-line Detection Comparator Threshold, Vsense rising 2.1 2.2 2.3 V VLL ICONTROL(BO) High-line Detection Comparator Threshold, Vsense falling 1.6 1.7 1.8 V VHL(hyst) High-line Detection Comparator Hysteresis 400 500 600 mV THL(blank) Blanking Time for Line Range Detection 15 25 35 ms Brown-out Pin Bias Current, Vsense = VBO −250 − 250 nA (VpfcOK)L pfcOK low state voltage @ IpfcOK = 5 mA − − 250 mV VSTDWN Shutdown Threshold Voltage (NCP1612A, NCP1612A1, NCP1612A3 and NCP1612B only) 7.0 7.5 8.0 V Impedance of the pfcOK pin in high state (all versions) 150 300 − kW IBO(bias) pfcOK SIGNAL RpfcOK THERMAL SHUTDOWN TLIMIT Thermal Shutdown Threshold − 150 − °C HTEMP Thermal Shutdown Hysteresis − 50 − °C Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 7. There is actually a minimum dead-time that is the delay between the core reset detection and the DRV turning on (TZCD parameter of the “Current Sense and Zero Current Detection Blocks” section). 8. Guaranteed by design, the VCC pin can handle the double of the DRV peak source current, that is, 1 A typically. www.onsemi.com 6 NCP1612A, NCP1612B, NCP1612A1, NCP1612A2, NCP1612A3, NCP1612B2 Table 4. DETAILED PIN DESCRIPTION Pin Number Name Function 1 FOVP Vpin1 is the input signal for the Fast Over-voltage (FOVP). The circuit disables the driver if Vpin1 exceeds the FOVP threshold which is set 2% higher than the reference for the soft OVP comparator (that monitors the feedback pin) so that pins 1 and 2 can receive the same portion of the output voltage. With the NCP1612A, NCP1612A1, NCP1612A3 and NCP1612B, Vpin1 is also used for under-voltage detection (UVP2) and Bulk Under Voltage (BUV) detection. The BUV comparator disables the driver and grounds the pfcOK pin when Vpin1 drops below 76% of the 2.5 V reference voltage in the A and B versions and below 40% of the 2.5 V reference voltage in the A1/A3 version. The BUV function has no action whenever the pfcOK pin is in low state. A 250 nA sink current is built-in to ground the pin if the pin is accidentally open. 2 Feedback This pin receives a portion of the PFC output voltage for the regulation and the Dynamic Response Enhancer (DRE) that drastically speeds-up the loop response when the output voltage drops below 95.5% of the desired output level. Vpin2 is also the input signal for the Over-voltage (OVP) and Under-voltage (UVP) comparators. The UVP comparator prevents operation as long as Vpin2 is lower than 12% of the reference voltage (VREF). A soft OVP comparator gradually reduces the duty-ratio to zero when Vpin2 exceeds 105% of VREF (soft OVP). With the NCP1612A2 and the NCP1612B2, Vpin2 is used for Bulk Under Voltage (BUV) detection. A 250 nA sink current is built-in to trigger the UVP protection and disable the part if the feedback pin is accidentally open. 3 VCONTROL The error amplifier output is available on this pin. The network connected between this pin and ground adjusts the regulation loop bandwidth that is typically set below 20 Hz to achieve high Power Factor ratios. Pin3 is grounded when the circuit is off so that when it starts operation, VCONTROL slowly charges up to provide a soft-start function with the A, A1, A2 and A3 versions which disables the dynamic response enhancer (DRE) until the startup phase is completed. With the versions optimized for self-powered PFC stages (NCP1612B and NCP1612B2), DRE speeds-up the VCONTROL charge for a shortened startup phase. 4 VSENSE A portion of the instantaneous input voltage is to be applied to pin4 in order to detect brown-out conditions. If Vpin 4 is lower than 0.9 V for more than 50 ms, the circuit stops pulsing until the pin voltage rises again and exceeds 1 V. This pin also detects the line range. By default, the circuit operates the “low-line gain” mode. If Vpin4 exceeds 2.2 V, the circuit detects a high-line condition and reduces the loop gain by 3. Conversely, if the pin voltage remains lower than 1.7 V for more than 25 ms, the low-line gain is set. Connecting the pin 4 to ground disables the part once the 50-ms blanking time has elapsed. 5 FFCONTROL This pin sources a current representative to the line current. Connect a resistor between pin5 and ground to generate a voltage representative of the line current. When this voltage exceeds the internal 2.5 V reference (VREF), the circuit operates in critical conduction mode. If the pin voltage is below 2.5 V, a dead-time is generated that approximately equates [66 ms • (1 − (Vpin5/VREF))]. By this means, the circuit forces a longer dead-time when the current is small and a shorter one as the current increases. The circuit skips cycles whenever Vpin5 is below 0.65 V to prevent the PFC stage from operating near the line zero crossing where the power transfer is particularly inefficient. This does result in a slightly increased distortion of the current. If superior power factor is required, offset pin 5 by more than 0.75 V offset to inhibit the skip function. 6 CS/ZCD This pin monitors the MOSFET current to limit its maximum current. This pin is also connected to an internal comparator for Zero Current Detection (ZCD). This comparator is designed to monitor a signal from an auxiliary winding and to detect the core reset when this voltage drops to zero. The auxiliary winding voltage is to be applied through a diode to avoid altering the current sense information for the on-time (see application schematic). 7 Ground Connect this pin to the PFC stage ground. 8 Drive The high-current capability of the totem pole gate drive (−0.5/+0.8 A) makes it suitable to effectively drive high gate charge power MOSFETs. 9 VCC This pin is the positive supply of the IC. The circuit starts to operate when VCC exceeds 10.5 V (A, A1, A2 and A3 versions, 17.0 V for the B and B2 versions) and turns off when VCC goes below 9.0 V (typical values). After start-up, the operating range is 9.5 V up to 35 V. The A, A1, A2 and A3 versions are preferred in applications where the circuit is fed by an external power source (from an auxiliary power supply or the downstream converter). Its maximum start-up level (11.25 V) is set low enough so that the circuit can be powered from a 12 V rail. The B and B2 versions are optimized for applications where the PFC stage is self-powered. 10 pfcOK This pin is grounded until the PFC output has reached its nominal level. It is also grounded if the NCP1612 detects a fault. For the rest of the time, i.e., when the PFC stage outputs the nominal bulk voltage, pin10 is in high-impedance state. The NCP1612A, NCP1612A1, NCP1612A3 and NCP1612B latch off if Vpin10 exceeds 7.5 V. www.onsemi.com 7 NCP1612A, NCP1612B, NCP1612A1, NCP1612A2, NCP1612A3, NCP1612B2 BUVcomp BUVcomp2 BUV BUVcomp2 − BUVcomp1 + V BUV NCP1612A pfcOK NCP1612A1 FB NCP1612A3 12%*Vref hyst