NCP3155B

NCP3155A, NCP3155B 3 A Synchronous Buck Regulator The NCP3155 is a DC/DC synchronous switching regulator with fully integrated power switches and full fault protection. The switching frequency of 1 MHz and 500 kHz allows the use of small filter components, which results in smaller board space and reduced BOM cost. Available in a SOIC-8 package. Features http://onsemi.com 8 1 SOIC−8 NB CASE 751 • • • • • • • • • • • • • • • • Input Voltage Range from 4.7 V to 24 V Adjustable Output Voltage 1 MHz Operation (NCP3155A – 500 kHz) Internally Programmed 1.2 ms Soft−Start (NCP3155A – 2.4 ms) 0.8 ± 1.0% Reference Voltage 48 mW HS−FET and 18 mW LS−FET Current Limit Protection Transconductance Amplifier with External Compensation Input Undervoltage Lockout Output Overvoltage and Undervoltage Detection These are Pb−Free Devices Set Top Boxes DVD Drives and HDD LCD Monitors and TVs Cable Modems Telecom/Networking/Datacom Equipment MARKING DIAGRAM 8 3155x ALYW G 1 3155x A L Y W G = Specific Device Code x = A or B = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package Typical Applications PIN CONNECTIONS PGND VIN VOUT BST COMP (Top View) VSW ISET AGND FB 4.7 V − 24 V VIN BST VSW PGND NCP3155 ISET COMP FB1 AGND ORDERING INFORMATION Device NCP3155ADR2G NCP3155BDR2G Package Shipping† SOIC−8 2500 / Tape & Reel (Pb−Free) SOIC−8 2500 / Tape & Reel (Pb−Free) Figure 1. Typical Application Circuit †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2011 February, 2011 − Rev. 1 1 Publication Order Number: NCP3155/D NCP3155A, NCP3155B BST VIN VIN INTERNAL BIAS POR/STARTUP THERMAL SD VC ACTIVE BOOST OSCILLATOR CLK/ DMAX/ SOFT START RAMP 1.5 V + − GATE DRIVE LOGIC LEVEL SHIFT VIN CURRENT LIMIT ISET VC HSDRV VSW SAMPLE & HOLD COMP REF LSDRV PGND FB + − + − ISET OOV OUV AGND Figure 2. NCP3155 Block Diagram PIN FUNCTION DESCRIPTION Pin 1 2 Pin Name PGND VIN Description The PGND pin is the high current ground pin for the lower MOSFET and drivers which should be soldered to a large copper area to reduce thermal resistance. The VIN pin powers the internal control circuitry and is monitored by an undervoltage comparator. The VIN pin is also connected to the internal power NMOS switch. It is also used in conjunction with the VSW pin to sense current in the high side MOSFET. The VIN pin has high dI/dt edges and must be decoupled to PGND pin close to the pin of the device. Supply rail for the floating top gate driver. Connect a capacitor (CBST) between this pin and the VSW pin. Typical values for CBST range from 1 nF to 10 nF. Compensation pin. The comp pin is the output of the transconductance amplifier and the non−inverting input of the PWM comparator. The comp pin in conjunction with the FB pin are used to compensate the voltage−control feedback loop. Inverting input to the Operational Transconductance Amplifier (OTA). The FB pin in conjunction with the external compensation serves to stabilize and achieve the desired output voltage with voltage mode compensation. The AGND pin serves as small−signal ground. All small−signal ground paths should connect to the AGND pin at a single point to avoid any high current ground returns. Bottom gate MOSFET driver pin and the internal current set pin. Place a resistor to ground to set the current limit of the converter. The VSW pin is the connection of the drain and source of the internal N MOSFETS. The VSW pin swings from VIN when the high side switch is on to small negative voltages when the low side switch is on with high dV/dt transitions. 3 4 BST COMP 5 6 7 8 FB AGND ISET VSW http://onsemi.com 2 NCP3155A, NCP3155B ABSOLUTE MAXIMUM RATINGS (measured vs. GND pin 8, unless otherwise noted) Rating Main Supply Voltage Input Boost to VSW differential voltage High Side Drive Boost Pin Switch Voltage Node Transconductance Amplifier Output Feedback Current Limit Set Operating Junction Temperature Range (Note 1) Maximum Junction Temperature Storage Temperature Range Thermal Characteristics − SOIC−8 Package Thermal Resistance Junction−to−Air Lead Temperature Soldering (10 sec): Reflow (SMD styles only) Pb−Free (Note 3) (Note 2) (Note 3) Symbol VCC BST−VSW BST VSW COMP FB ISET TJ TJ(MAX) Tstg RqJA RF VMAX 26.4 13.2 45 30 5.5 6.0 13.2 VMIN −0.3 −0.3 −0.3 −0.6 −0.3 −0.3 −0.3 Unit V V V V V V V °C °C °C °C/W °C −40 to +125 +150 −55 to +150 110 170 260 Peak Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. The maximum package power dissipation limit must not be exceeded. PD + TJ(max) * T A R qJA 2. The value of qJA is measured with the device mounted on 1 in2 FR*4 board with 1 oz. copper, in a still air environment with TA = 25°C. The value in any given application depends on the user’s specific board design. 3. The value of qJA is measured with the device mounted on minimum footprint, in a still air environment with TA = 25°C. The value in any given application depends on the user’s specific board design. http://onsemi.com 3 NCP3155A, NCP3155B ELECTRICAL CHARACTERISTICS (−40°C < TJ < +125°C, VCC = 12 V, for min/max values unless otherwise noted) Characteristic Input Voltage Range SUPPLY CURRENT VCC Supply Current VCC Supply Current NCP3155A NCP3155B VFB = 0.8 V, Switching, VCC = 4.7 V VFB = 0.8 V, Switching, VCC = 24 V VFB = 0.8 V, Switching, VCC = 4.7 V VFB = 0.8 V, Switching, VCC = 24 V UNDER VOLTAGE LOCKOUT UVLO Rising Threshold UVLO Falling Threshold OSCILLATOR Oscillator Frequency Oscillator Frequency Ramp−Amplitude Voltage Ramp Valley Voltage PWM Minimum Duty Cycle Maximum Duty Cycle Soft Start Ramp Time NCP3155A NCP3155B VFB = VCOMP (Note 4) − 80 − − 0.9 (Notes 4 and 6) VFB = 750 mV VFB = 850 mV TJ = 25 C 4.7 V < VIN < 28 V, −40°C < TJ < +125°C VFB = 750 mV VFB = 850 mV − 45 45 − 0.792 0.784 4.0 − 0.91 0.56 VIN = 12 V VIN = 4.7 V VIN = 12 V VIN = 4.7 V − − − − 7 RSET = 22.1 kW (Notes 4 and 7) (Notes 4 and 7) − − − 7.0 84 2.4 1.2 1.3 70 70 70 0.5 0.8 0.8 4.4 72 1.00 0.60 48 65 18 21 13.5 298 175 20 − − − − 1.9 − 100 100 500 0.808 0.816 5.0 250 1.09 0.64 63 85 35 50 18 − − − % % ms NCP3155A NCP3155B TJ = +25°C, 4.7 V v VCC v 28 V TJ = −40°C to +125°C, 4.7 V v VCC v 28 V TJ = +25°C, 4.7 V v VCC v 28 V TJ = −40°C to +125°C, 4.7 V v VCC v 28 V Vpeak − Valley 415 400 830 820 − 0.46 500 500 1000 1000 1.5 0.71 585 600 1170 1180 − 0.85 kHz kHz kHz kHz V V VCC Rising Edge VCC Falling Edge 4.0 3.5 4.3 3.9 4.7 4.3 V V − − − − 11.1 31.5 16.5 54.7 − − − − mA mA mA mA Conditions − Min 4.7 Typ Max 24 Unit V ERROR AMPLIFIER (GM) Transconductance Open Loop dc Gain Output Source Current Output Sink Current FB Input Bias Current Feedback Voltage COMP High Voltage COMP Low Voltage OUTPUT VOLTAGE FAULTS Feedback OOV Threshold Feedback OUV Threshold PWM OUTPUT STAGE High−Side Switch On Resistance Low−Side Switch On Resistance OVERCURRENT ISET Source Current Current Limit Set Voltage (Note 5) THERMAL SHUTDOWN Thermal Shutdown Hysteresis 4. 5. 6. 7. °C °C mA mV mW mW V V mS dB mA mA nA V V V mV Guaranteed by design. The voltage sensed across the high side MOSFET during conduction. This assumes 100 pF capacitance to ground on the COMP Pin and a typical internal Ro of > 10 MW. This is not a protection feature. http://onsemi.com 4 NCP3155A, NCP3155B TYPICAL PERFORMANCE CHARACTERISTICS 100 90 80 EFFICENCY (%) 70 60 50 40 30 20 10 0 0 0.5 NCP3155A, Vin = 12 V Typical Application Circuit Figure 45 1 1.5 2 Iout, OUTPUT CURRENT (A) 2.5 3 1.5 V 100 90 80 EFFICENCY (%) 1.2 V 70 60 50 40 30 20 10 0 0 0.5 NCP3155B, Vin = 12 V Typical Application Circuit Figure 45 1 1.5 2 Iout, OUTPUT CURRENT (A) 2.5 3 1.5 V Vout = 5.0 V 3.3 V 1.2 V Vout = 5.0 V 3.3 V Figure 3. Efficiency vs Output Current and Output Voltage Figure 4. Efficiency vs Output Current and Output Voltage 100 90 80 EFFICENCY (%) 70 60 50 40 30 20 10 0 0 Vin = 12 V Vin = 24 V VOUT (V) Vin = 18 V 5.1 5.08 5.06 5.04 5.02 5 4.98 4.96 4.94 4.92 3 4.9 0 NCP3155A, Vout = 5 V Typical Application Circuit Figure 45 0.4 0.8 1.2 1.6 Vin = 18 V Vin = 12 V Vin = 24 V NCP3155A, Vout = 5 V Typical Application Circuit Figure 45 0.5 1 1.5 2 Iout, OUTPUT CURRENT (A) 2.5 2.0 2.4 2.8 Iout, OUTPUT CURRENT (A) Figure 5. Efficiency vs Output Current and Input Voltage Figure 6. Load Regulation vs Input Voltage Input = 12 V, Output = 5.0 V, Load = 2 A, CH3 (Purple) = VIN, (CH2) Green = VOUT, CH1 (Yellow) = VSW CH3: 200 mVac/div; CH2: 50 mVac/div; CH1: 5.0 V/div Time Scale: 2.0 ms/div; Figure 45 Input = 18 V, Output = 5.0 V, Load = 2 A, CH3 (Purple) = VIN, (CH2) Green = VOUT, CH1 (Yellow) = VSW CH3: 200 mVac/div; CH2: 50 mVac/div; CH1: 5.0 V/div Time Scale: 2.0 ms/div; Figure 45 Figure 7. Switching Waveforms (NCP3155A) Figure 8. Switching Waveforms (NCP3155A) http://onsemi.com 5 NCP3155A, NCP3155B TYPICAL PERFORMANCE CHARACTERISTICS 808 806 804 VFB (mV) 802 800 798 796 794 Input = 12 V, Output = 1.8 V, Load = 2 A, CH3 (Purple) = VIN, (CH2) Green = VOUT, CH1 (Yellow) = VSW CH3: 200 mVac/div; CH2: 50 mVac/div; CH1: 5.0 V/div Time Scale: 1.0 ms/div; Figure 46 792 −40 −25 −10 5 20 35 50 65 TEMPERATURE (°C) 80 95 110 125 Figure 9. Switching Waveforms (NCP3155B) 570 NCP3155A 560 550 540 530 520 510 Vin = 12 V − 24 V 500 490 Vin = 4.7 V 480 470 460 450 440 430 −40 −25 −10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) Figure 10. Feedback Reference Voltage vs Temperature 1120 1100 1080 1060 1040 1020 1000 980 960 940 920 900 880 860 −40 −25 −10 NCP3155B fSW (kHz) fSW (kHz) Vin = 12 V − 24 V Vin = 4.7 V 5 20 35 50 65 80 TEMPERATURE (°C) 95 110 125 Figure 11. Switching Frequency vs Input Voltage and Temperature Figure 12. Switching Frequency vs Input Voltage and Temperature 1.5 1.48 1.46 1.44 1.4 1.38 1.36 1.34 1.32 1.3 −40 −25 −10 5 20 35 50 65 80 TEMPERATURE (°C) 95 110 125 UVLO (V) gm (mS) 1.42 4.5 4.4 4.3 4.2 4.1 4 3.9 3.8 3.7 3.6 3.5 40 25 10 5 UVLO Falling 20 35 50 65 80 TEMPERATURE (°C) 95 110 125 UVLO Rising Figure 13. Transconductance vs Temperature Figure 14. Input Undervoltage vs Temperature http://onsemi.com 6 NCP3155A, NCP3155B TYPICAL PERFORMANCE CHARACTERISTICS 1200 THRESHOLD VOLTAGE (mV) 1000 950 VALLEY VOLTAGE (mV) Output Overvoltage Threshold 900 850 800 750 700 650 600 550 500 450 400 −40 −25 −10 1100 1000 900 800 700 600 500 400 −40 −25 −10 5 20 35 50 65 80 95 110 125 Output Undervoltage Threshold 5 TEMPERATURE (°C) 20 35 50 65 80 TEMPERATURE (°C) 95 110 125 Figure 15. Output Protection vs Temperature 17 16 15 ISET (mA) 14 13 12 11 10 −40 −25 −10 5 20 35 50 65 80 TEMPERATURE (°C) 95 110 125 Figure 16. Ramp Valley Voltage vs Temperature Figure 17. ISET Current vs Temperature Input = 12 V, Output = 1.8 V, Load = 2 A, CH3 (Purple) = VIN, (CH2) Green = VOUT, CH1 (Yellow) = VSW CH3: 10 V/div; CH2: 2.0 V/div; CH1: 5.0 V/div Time Scale: 1.0 ms/div; Figure 45 Figure 18. Startup Waveforms (NCP3155A) Input = 12 V, Output = 1.8 V, Load = 2 A, CH3 (Purple) = VIN, (CH2) Green = VOUT, CH1 (Yellow) = VSW CH3: 10 V/div; CH2: 1.0 V/div; CH1: 5.0 V/div Time Scale: 0.5 ms/div; Figure 46 Input = 12 V (CH2) Green = VOUT, CH1 (Yellow) = VSW CH2: 0.5 V/div; CH1: 5.0 V/div Time Scale: 2.0 ms/div; Figure 45 Figure 19. Startup Waveforms (NCP3155B) Figure 20. Current Limit Waveforms (NCP3155A) http://onsemi.com 7 NCP3155A, NCP3155B TYPICAL PERFORMANCE CHARACTERISTICS 110 100 90 80 RDS(on) (mW) 70 60 50 40 30 20 10 0 Input = 12 V (CH2) Green = VOUT, CH1 (Yellow) = VSW CH2: 0.5 V/div; CH1: 5.0 V/div Time Scale: 2.0 ms/div; Figure 46 40 25 10 5 20 35 50 65 80 95 110 125 Vin = 10 V − 24 V Vin = 5.0 V TEMPERATURE (°C) Figure 21. Current Limit Waveforms (NCP3155B) 30 25 OUTPUT CURRENT (A) 20 15 10 5 0 −40 −25 −10 Vin = 10 V − 24 V Vin = 5.0 V 3.5 3 2.5 2 1.5 1 0.5 Figure 22. High−Side MOSFET RDS(on) vs Temperature 1.0 V < Vout < 1.8 V 3.3 V 2.5 V Vout = 5.0 V RDS(on) (mW) NCP3155A 5 20 35 50 65 80 95 110 125 0 25 30 35 40 45 50 55 60 65 70 75 80 85 TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C) Figure 23. Low−Side MOSFET RDS(on) vs Temperature 3.5 3 2.5 2 1.5 1 0.5 NCP3155A 0 25 30 35 40 45 50 55 60 65 70 75 80 85 0 25 TA, AMBIENT TEMPERATURE (°C) Vout = 5.0 V 3.3 V 2.5 V 1.8 V OUTPUT CURRENT (A) 3.5 3 2.5 2 1.5 1 0.5 Figure 24. Derating Curve, 12 V Input OUTPUT CURREENT (A) 12 V 2.5 V Vout = 5.0 V 3.3 V NCP3155A 30 35 40 45 50 55 60 65 70 75 80 85 TA, AMBIENT TEMPERATURE (°C) Figure 25. Derating Curve, 18 V Input Figure 26. Derating Curve, 24 V Input http://onsemi.com 8 NCP3155A, NCP3155B TYPICAL PERFORMANCE CHARACTERISTICS 3.5 3 OUTPUT CURRENT (A) 2.5 2 1.5 1 0.5 NCP3155B 0 25 30 35 40 45 50 55 60 65 70 75 80 85 TA, AMBIENT TEMPERATURE (°C) Vout = 5.0 V 1.0 to 1.2 V 3.5 3 OUTPUT CURRENT (A) 2.5 2 1.5 1 0.5 0 25 NCP3155B 30 35 40 45 50 55 60 65 70 75 80 85 TA, AMBIENT TEMPERATURE (°C) Vout = 5.0 V 3.3 V 2.5 V 1.8 V 3.3 V 2.5 V 1.8 V Figure 27. Derating Curve, 12 V Input Figure 28. Derating Curve, 18 V Input 3.5 3 OUTPUT CURRENT (A) 2.5 2 1.5 1 0.5 NCP3155B 0 25 30 35 40 45 50 55 60 65 70 75 80 85 TA, AMBIENT TEMPERATURE (°C) 12 V Vout = 5.0 V 3.3 V 2.5 V Figure 29. Derating Curve, 24 V Input http://onsemi.com 9 NCP3155A, NCP3155B DETAILED DESCRIPTION OVERVIEW The NCP3155A/B operates as a 500 kHz/1.0 MHz, voltage mode, pulse width modulated, (PWM) synchronous buck converter. It drives high−side and low−side N−channel power MOSFETs. The NCP3155 incorporates an internal boost circuit consisting of a boost clamp and boost diode to provide supply voltage for the high side MOSFET gate driver. The NCP3155 also integrates several protection features including input undervoltage lockout (UVLO), output undervoltage (OUV), output overvoltage (OOV), adjustable high−side current limit (ISET and ILIM), and thermal shutdown (TSD). The operational transconductance amplifier (OTA) provides a high gain error signal from Vout which is compared to the internal 1.5 V pk-pk ramp signal to set the duty cycle converter using the PWM comparator. The high side switch is turned on by the positive edge of the clock cycle going into the PWM comparator and flip flop following a non-overlap time. The high side switch is turned off when the PWM comparator output is tripped by the modulator ramp signal reaching a threshold level established by the error amplifier. The gate driver stage incorporates fixed non− overlap time between the high−side and low−side MOSFET gate drives to prevent cross conduction of the power MOSFET’s. POR and UVLO The device contains an internal Power On Reset (POR) and input Undervoltage Lockout (UVLO) that inhibits the internal logic and the output stage from operating until VCC reaches its respective predefined voltage levels (4.3 V typical). Startup and Shutdown Once VCC crosses the UVLO rising threshold the device begins its startup process. Closed−loop soft−start begins after a 400 ms delay wherein the boost capacitor is charged, and the current limit threshold is set. During the 400 ms delay the OTA output is set to just below the valley voltage of the internal ramp. This is done to reduce delays and to ensure a consistent pre−soft−start condition. The device increases the internal reference from 0 V to 0.8 V in 32 discrete steps while maintaining closed loop regulation at each step. Each step contains 32 switching cycles. Some overshoot may be evident at the start of each step depending on the voltage loop phase margin and bandwidth. The total soft−start time is 2.4 ms for the NCP3155A and 1.2 ms for the NCP3155B. 0.8 V Output Voltage 25 mV Steps 32 Voltage Steps Internal Reference Voltage Internal Ramp OTA Output 0 .7V 0V Figure 30. Soft−Start Details http://onsemi.com 10 NCP3155A, NCP3155B OOV and OUV The output voltage of the buck converter is monitored at the feedback pin of the output power stage. Two comparators are placed on the feedback node of the OTA to monitor the operating window of the feedback voltage as shown in Figures 31 and 32. All comparator outputs are ignored during the soft−start sequence as soft−start is regulated by the OTA and false trips would be generated. After the soft−start period has ended, if the feedback is below the reference voltage of comparator 2 (VFB < 0.6 V), the output is considered “undervoltage” and the device will initiate a restart. When the feedback pin voltage rises between the reference voltages of comparator 1 and comparator 2 (0.6 < VFB < 1.0), then the output voltage is considered “Power Good.” Finally, if the feedback voltage is greater than comparator 1 (VFB > 1.0 V), the output voltage is considered “overvoltage,” and the device will latch off. To clear a latch fault, input voltage must be recycled. Graphical representation of the OOV and OUV is shown in Figures 33 and 34. Soft Start Complete Vref*125% Comparator 1 Restart LOGIC FB Latch off Vref*75% Vref = 0.8 V Comparator 2 Figure 31. OOV and OUV Circuit Diagram OOVP & Power Good = 0 Hysteresis = 5 mV Power Good = 1 Voov = Vref * 125% Power Not good High Vref = 0.8 V Power Good = 1 Hysteresis = 5 mV OUVP & Power Good = 0 Power Not Good Low Vouv = Vref * 75% Figure 32. OOV and OUV Window Diagram http://onsemi.com 11 NCP3155A, NCP3155B 1.0 V (vref *125%) 0.8 V (vref *100%) 0.6 V (vref *75%) FB Voltage Latch off Reinitiate Softstart Softstart Complete Figure 33. Powerup Sequence and Overvoltage Latch 1.0 V (vref *125%) 0.8 V (vref *100%) 0.6 V (vref * 75%) FB Voltage Latch off Reinitiate Softstart Softstart Complete Figure 34. Powerup Sequence and Undervoltage Soft−Start http://onsemi.com 12 NCP3155A, NCP3155B CURRENT LIMIT AND CURRENT LIMIT SET Overview The NCP3155 uses the voltage drop across the High Side MOSFET during the on time to sense inductor current. The ILimit block consists of a voltage comparator circuit which compares the differential voltage across the VCC Pin and the VSW Pin with a resistor settable voltage reference. The sense portion of the circuit is only active while the HS MOSFET is turned ON. VIN VCC Ilim Out VSense Itrip Ref Switch Cap CONTROL VSW Iset 13 uA 6 DAC / COUNTER Vset ISET RSet PGND Itrip Ref−63 Steps, 6.51 mV/step Figure 35. Iset / ILimit Block Diagram Current Limit Set The ILimit comparator reference is set during the startup sequence by forcing a typically 13 mA current through the low side gate drive resistor. The gate drive output will rise to a voltage level shown in the equation below: V set + I set * R set (eq. 1) Where ISET is 13 mA and RSET is the gate to source resistor on the low side MOSFET. This resistor is normally installed to prevent MOSFET leakage from causing unwanted turn on of the low side MOSFET. In this case, the resistor is also used to set the ILimit trip level reference through the ILimit DAC. The Iset process takes approximately 350 ms to complete prior to Soft−Start stepping. The scaled voltage level across the ISET resistor is converted to a 6 bit digital value and stored as the trip value. The binary ILimit value is scaled and converted to the analog ILimit reference voltage through a DAC counter. The DAC has 63 steps in 6.51 mV increments equating to a maximum sense voltage of 403 mV. During the Iset period prior to Soft−Start, the DAC counter increments the reference on the ISET comparator until it crosses the VSET voltage and holds the DAC reference output to that count value. This voltage is translated to the ILimit comparator during the ISense portion of the switching cycle through the switch cap circuit. See Figure 35. Exceeding the maximum sense voltage results in no current limit. Steps 0 to 10 result in an effective current limit of 0 mV. Current Sense Cycle Figure 36 shows how the current is sampled as it relates to the switching cycle. Current level 1 in Figure 36 represents a condition that will not cause a fault. Current level 2 represents a condition that will cause a fault. The sense circuit is allowed to operate below the 3/4 point of a given switching cycle. A given switching cycle’s 3/4 Ton time is defined by the prior cycle’s Ton and is quantized in 10 ns steps. A fault occurs if the sensed MOSFET voltage exceeds the DAC reference within the 3/4 time window of the switching cycle. http://onsemi.com 13 NCP3155A, NCP3155B Trip: Vsense > Itrip Ref at 3/4 Point No Trip: Vsense < Itrip Ref at 3/4 Point Itrip Ref Vsense Ton−2 ¾ Ton−1 ¾ Current Level 1 Current Level 2 3/4 Point Determined by Prior Cycle 1/4 1/2 3/4 1/4 1/2 3/4 Ton−1 Ton Each switching cycle’s Ton is counted in 10 nS time steps. The 3/4 sample time value is held and used for the following cycle’s limit sample time Figure 36. ILimit Trip Point Description Soft−Start Current limit During soft−start the ISET value is doubled to allow for inrush current to charge the output capacitance. The DAC reference is set back to its normal value after soft−start has completed. The ILimit block can lose accuracy if there is excessive VSW voltage ringing that extends beyond the 1/2 point of the high−side transistor on−time. Proper snubber design and keeping the ratio of ripple current and load current in the 10−30% range can help alleviate this as well. Current Limit VSW Ringing VOUT = Output Voltage (V) FSW = Switching Frequency (Hz) Boost Clamp Functionality A current limit trip results in completion of one switching cycle and subsequently half of another cycle Ton to account for negative inductor current that might have caused negative potentials on the output. Subsequently the power MOSFETs are both turned off and a 4 soft−start time period wait passes before another soft−start cycle is attempted. The average load trip current versus RSET value is shown the equation below: I AveTRIP + Iset R set R DS(on) * 1 V IN * V OUT 4 L V OUT V IN 1 FSW (eq. 2) The boost circuit requires an external capacitor connected between the BST and VSW pins to store charge for supplying the high and low−side gate driver voltage. This clamp circuit limits the driver voltage to typically 7.5 V when VIN > 9 V, otherwise this internal regulator is in dropout and typically VIN − 1.25 V. The boost circuit regulates the gate driver output voltage and acts as a switching diode. A simplified diagram of the boost circuit is shown in Figure 37. While the switch node is grounded, the sampling circuit samples the voltage at the boost pin, and regulates the boost capacitor voltage. The sampling circuit stores the boost voltage while the VSW is high and the linear regulator output transistor is reversed biased. VIN Iave vs Trip Point 8.9V Switch Sampling Circuit BST VSW LSDR Where: L = Inductance (H) ISET = 13 mA RSET = Gate to Source Resistance (W) RDS(on) = On Resistance of the HS MOSFET (48 mW) VIN = Input Voltage (V) Figure 37. Boost Circuit http://onsemi.com 14 NCP3155A, NCP3155B Reduced sampling time occurs at high duty cycles where the low side MOSFET is off for the majority of the switching period. Reduced sampling time causes errors in the regulated voltage on the boost pin. High duty cycle / input voltage induced sampling errors can result in increased boost ripple voltage or higher than desired DC boost voltage. Figure 38 outlines all operating regions. The recommended operating conditions are shown in Region 1 (Green) where a 0.1 mF, 25 V ceramic capacitor can be placed on the boost pin without causing damage to the device or MOSFETS. Larger boost ripple voltage occurring over several switching cycles is shown in Region 2 (Yellow). The boost ripple frequency is dependent on the output capacitance selected. The ripple voltage will not damage the device or $12 V gate rated MOSFETs. Conditions where maximum boost ripple voltage could damage the device or $12 V gate rated MOSFETs can be seen in Region 3 (Orange). Placing a boost capacitor that is no greater than 3.3 nF on the boost pin limits the maximum boost voltage < 12 V. The typical drive waveforms for Regions 1, 2 and 3 (green, yellow, and orange) regions of Figure 38 are shown in Figure 39. BOOST VOLTAGE LEVELS Normal Operation (Region 1) Increased Boost Ripple (Still in Specification) (Region 2) Increased Boost Ripple Capacitor Optimization Required (Region 3) 24 Region 3 22 20 18 INPUT VOLTAGE 16 14 12 10 8 6 4 2 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 71% 11.5V Region 1 Region 2 Max Duty Cycle 22V DUTY CYCLE Figure 38. Safe Operating Area for Boost Voltage with a 0.1 mF Capacitor http://onsemi.com 15 NCP3155A, NCP3155B 7.5V VIN VBOOST 7.5V 0V Maximum Normal VIN 7.5V VBOOST 7.5V 0V Maximum Normal VIN 7.5V VBOOST 7.5V 0V Figure 39. Typical Waveforms for Region 1 (top), Region 2 (middle), and Region 3 (bottom) To illustrate, a 0.1 mF boost capacitor operating at > 80% duty cycle and > 22.5 V input voltage will exceed the specifications for the driver supply voltage. See Figure 40. http://onsemi.com 16 NCP3155A, NCP3155B Boost Voltage 18 16 14 12 Boost Voltage (V) 10 8 6 4 2 0 4.5 Voltage Ripple Maximum Allowable Voltage Maximum Boost Voltage 6.5 8.5 10.5 12.5 14.5 16.5 18.5 Input Voltage (V) 20.5 22.5 24.5 26.5 Figure 40. Boost Voltage at 80% Duty Cycle Inductor Selection V OUT ) V LSD V IN * V HSD ) V LSD 3.3 V 12 V V OUT V IN (eq. 5) When selecting the inductor, it is important to know the input and output requirements. Some example conditions are listed below to assist in the process. Table 1. DESIGN PARAMETERS Design Parameter Input Voltage Nominal Input Voltage Output Voltage Input ripple voltage Output ripple voltage Output current rating Operating frequency (VIN) (VIN) (VOUT) (VINRIPPLE) (VOUTRIPPLE) (IOUT) (Fsw) Example Value 9 V to 16 V 12 V 3.3 V 300 mV 50 mV 3A 500 kHz D+ [D+ ³ 27.5% + The ratio of ripple current to maximum output current simplifies the equations used for inductor selection. The formula for this is given in Equation 6. ra + DI I OUT (eq. 6) A buck converter produces input voltage (VIN) pulses that are LC filtered to produce a lower dc output voltage (VOUT). The output voltage can be changed by modifying the on time relative to the switching period (T) or switching frequency. The ratio of high side switch on time to the switching period is called duty cycle (D). Duty cycle can also be calculated using VOUT, VIN, the low side switch voltage drop VLSD, and the High side switch voltage drop VHSD. F+ D+ T ON T 1 T T OFF T (eq. 3) The designer should employ a rule of thumb where the percentage of ripple current in the inductor lies between 10% and 40%. When using ceramic output capacitors the ripple current can be greater thus a user might select a higher ripple current, but when using electrolytic capacitors a lower ripple current will result in lower output ripple. Now, acceptable values of inductance for a design can be calculated using Equation 7. L+ V OUT I OUT @ ra @ F SW 3.3 V 3 A @ 20% @ 500 MHz @ (1 * D) ³ 8.2 mH (eq. 7) + @ (1 * 27.5%) The relationship between ra and L for this design example is shown in Figure 41. (* D + (eq. 4) http://onsemi.com 17 NCP3155A, NCP3155B 20 18 L, INDUCTANCE (mH) 16 14 12 10 8 6 4 2 0 10% 15% 20% 25% VIN, (V) 30% 35% 40% 9 V−In 18 V−In Vout = 3.3 V I PP + V OUT(1 * D) L OUT @ FSW (eq. 11) 12 V−In Ipp is the peak to peak current of the inductor. From this equation it is clear that the ripple current increases as LOUT decreases, emphasizing the trade−off between dynamic response and ripple current. The power dissipation of an inductor consists of both copper and core losses. The copper losses can be further categorized into dc losses and ac losses. A good first order approximation of the inductor losses can be made using the DC resistance as they usually contribute to 90% of the losses of the inductor shown below: LP CU + I RMS 2 @ DCR (eq. 12) Figure 41. Ripple Current Ratio vs. Inductance To keep within the bounds of the parts maximum rating, calculate the RMS current and peak current. I RMS + I OUT @ +3A@ I PK + IOUT @ 1 ) 1 ) ra ³ 3.01 A 12 (0.2) 2 1) 12 2 The core losses and ac copper losses will depend on the geometry of the selected core, core material, and wire used. Most vendors will provide the appropriate information to make accurate calculations of the power dissipation then the total inductor losses can be capture buy the equation below: LP tot + LP CU_DC ) LP CU_AC ) LP Core (eq. 13) Input Capacitor Selection (eq. 8) (0.2) ra ³ 3.3 A + 3 A @ 1 ) 2 2 (eq. 9) An inductor for this example would be around 8.2 mH and should support an rms current of 3.01 A and a peak current of 3.3 A. The final selection of an output inductor has both mechanical and electrical considerations. From a mechanical perspective, smaller inductor values generally correspond to smaller physical size. Since the inductor is often one of the largest components in the regulation system, a minimum inductor value is particularly important in space−constrained applications. From an electrical perspective, the maximum current slew rate through the output inductor for a buck regulator is given by Equation 10. SlewRate LOUT + V IN * V OUT L OUT ³ 1.1 12 V * 3.3 V A + ms 8.2 mH (eq. 10) The input capacitor has to sustain the ripple current produced during the on time of the upper MOSFET, so it must have a low ESR to minimize the losses. The RMS value of this ripple is: Iin RMS + I OUT @ D @ (1 * D) (eq. 14) D is the duty cycle, IinRMS is the input RMS current, and IOUT is the load current. The equation reaches its maximum value with D = 0.5. Loss in the input capacitors can be calculated with the following equation: P CIN + ESR CIN @ I IN*RMS 2 (eq. 15) PCIN is the power loss in the input capacitors and ESRCIN is the effective series resistance of the input capacitance. Due to large dI/dt through the input capacitors, electrolytic or ceramics should be used. If a tantalum must be used, it must by surge protected. Otherwise, capacitor failure could occur. Input Start−up Current This equation implies that larger inductor values limit the regulator’s ability to slew current through the output inductor in response to output load transients. Consequently, output capacitors must supply the load current until the inductor current reaches the output load current level. This results in larger values of output capacitance to maintain tight output voltage regulation. In contrast, smaller values of inductance increase the regulator’s maximum achievable slew rate and decrease the necessary capacitance, at the expense of higher ripple current. The peak−to−peak ripple current for the NCP3155A is given by the following equation: To calculate the input startup current, the following equation can be used. I INRUSH + C OUT @ V OUT tSS (eq. 16) Iinrush is the input current during startup, COUT is the total output capacitance, VOUT is the desired output voltage, and tSS is the soft start interval. If the inrush current is higher than the steady state input current during max load, then the input fuse should be rated accordingly, if one is used. http://onsemi.com 18 NCP3155A, NCP3155B Output Capacitor Selection The important factors to consider when selecting an output capacitor is dc voltage rating, ripple current rating, output ripple voltage requirements, and transient response requirements. The output capacitor must be rated to handle the ripple current at full load with proper derating. The RMS ratings given in datasheets are generally for lower switching frequency than used in switch mode power supplies but a multiplier is usually given for higher frequency operation. The RMS current for the output capacitor can be calculated below: Co RMS + I O @ ra 12 (eq. 17) DV OUT−DISCHG + I TRAN 2 @ L OUT (eq. 22) C OUT @ V IN * V OUT The maximum allowable output voltage ripple is a combination of the ripple current selected, the output capacitance selected, the equivalent series inductance (ESL) and ESR. The main component of the ripple voltage is usually due to the ESR of the output capacitor and the capacitance selected. V ESR_C + I O @ ra @ ESR Co ) 1 8 @ FSW @ Co (eq. 18) In a typical converter design, the ESR of the output capacitor bank dominates the transient response. It should be noted that DVOUT−DISCHARGE and DVOUT−ESR are out of phase with each other, and the larger of these two voltages will determine the maximum deviation of the output voltage (neglecting the effect of the ESL). Conversely during a load release, the output voltage can increase as the energy stored in the inductor dumps into the output capacitor. The ESR contribution from Equation 18 still applies in addition to the output capacitor charge which is approximated by the following equation: DV OUT−CHG + I TRAN 2 @ L OUT (eq. 23) C OUT @ V OUT The ESL of capacitors depends on the technology chosen but tends to range from 1 nH to 20 nH where ceramic capacitors have the lowest inductance and electrolytic capacitors then to have the highest. The calculated contributing voltage ripple from ESL is shown for the switch on and switch off below: V ESLON + ESL @ IPP @ F SW D ESL @ I PP @ F SW (1 * D) (eq. 19) As with any power design, proper laboratory testing should be performed to insure the design will dissipate the required power under worst case operating conditions. Variables considered during testing should include maximum ambient temperature, minimum airflow, maximum input voltage, maximum loading, and component variations. Feedback and Compensation V ESLOFF + (eq. 20) The output capacitor is a basic component for the fast response of the power supply. In fact, during load transient, for the first few microseconds it supplies the current to the load. The controller immediately recognizes the load transient and sets the duty cycle to maximum, but the current slope is limited by the inductor value. During a load step transient the output voltage initially drops due to the current variation inside the capacitor and the ESR (neglecting the effect of the effective series inductance (ESL)). DV OUT−ESR + DI TRAN @ ESR Co (eq. 21) The NCP3155 is a voltage mode buck convertor with a transconductance error amplifier compensated by an external compensation network. Compensation is needed to achieve accurate output voltage regulation and fast transient response. The goal of the compensation circuit is to provide a loop gain function with the highest crossing frequency and adequate phase margin (minimally 45°). The transfer function of the power stage (the output LC filter) is a double pole system. The resonance frequency of this filter is expressed as follows: f P0 + 1 2 @ p @ L @ C OUT (eq. 24) Parasitic Equivalent Series Resistance (ESR) of the output filter capacitor introduces a high frequency zero to the filter network. Its value can be calculated by using the following equation: f Z0 + 1 2 @ p @ C OUT @ ESR (eq. 25) A minimum capacitor value is required to sustain the current during the load transient without discharging it. The voltage drop due to output capacitor discharge is approximated by the following equation: Table 2. COMPENSATION TYPES Zero Crossover Frequency Condition fP0 < fZ0 < f0 < fS/2 fP0 < f0 < fZ0 < fS/2 fP0 < f0 < fS/2 < fZ0 The main loop zero crossover frequency f0 can be chosen to be 1/10 − 1/5 of the switching frequency. Table 2 shows the three methods of compensation. Compensation Type Type II Type III Method I Type III Method II Typical Output Capacitor Type Electrolytic, Tantalum Tantalum, Ceramic Ceramic http://onsemi.com 19 NCP3155A, NCP3155B Compensation Type II This compensation is suitable for electrolytic capacitors. Components of the Type II (Figure 42) network can be specified by the following equations: f Z1 + 0.75 @ f P0 f Z2 + f P0 f P2 + f Z0 f P3 + fS 2 (eq. 30) (eq. 31) (eq. 32) (eq. 33) Method II is better suited for ceramic capacitors that typically have the lowest ESR available: f Z2 + f 0 @ f P2 + f 0 @ 1 * sinq max 1 ) sin q max 1 ) sin q max 1 * sin q max (eq. 34) (eq. 35) (eq. 36) (eq. 37) f Z1 + 0.5 @ f Z2 Figure 42. Type II Compensation R C1 + C C1 + C C2 + R1 + 2 @ p @ f 0 @ L @ V RAMP @ V OUT ESR @ V IN @ V ref @ gm 1 0.75 @ 2 @ p @ f P0 @ R C1 1 p @ R C1 @ f S V ref @ R2 (eq. 26) f P3 + 0.5 @ f S qmax is the desired maximum phase margin at the zero crossover frequency, ƒ0. It should be 45° − 75°. Convert degrees to radians by the formula: q max + q max degress @ 2 @ p : Units + radians 360 2 gm (eq. 38) (eq. 27) (eq. 28) The remaining calculations are the same for both methods. R C1 u u (eq. 39) (eq. 40) V OUT * V ref (eq. 29) VRAMP is the peak−to−peak voltage of the oscillator ramp and gm is the transconductance error amplifier gain. Capacitor CC2 is optional. Compensation Type III C C1 + C C2 + C FB1 + R FB1 + R1 + 1 2 @ p @ f Z1 @ R C1 1 2 @ p @ f P3 @ R C1 V IN @ R C1 1 (eq. 41) Tantalum and ceramics capacitors have lower ESR than electrolytic, so the zero of the output LC filter goes to a higher frequency above the zero crossover frequency. This requires a Type III compensation network as shown in Figure 43. There are two methods to select the zeros and poles of this compensation network. Method I is ideal for tantalum output capacitors, which have a higher ESR than ceramic: 2 @ p @ f 0 @ L @ V RAMP @ C OUT (eq. 42) 2p @ C FB1 @ f P2 1 * R FB1 (eq. 43) 2 @ p @ C FB1 @ f Z2 V ref (eq. 44) R2 + V OUT * V ref @ R1 (eq. 45) If the equation in Equation 46 is not true, then a higher value of RC1 must be selected. R1 @ R2 @ R FB1 R1 @ R FB1 ) R2 @ R FB1 ) R1 @ R2 u 1 (eq. 46) gm Figure 43. Type III Compensation http://onsemi.com 20 NCP3155A, NCP3155B Output Current Derating 14 VOUT, OUTPUT VOLTAGE (V) 12 10 8 6 4 2 0 4 6 8 10 12 14 16 18 20 22 24 The NCP3155 has a wide input voltage and output voltage capability. It also operates in a variety of thermal environments. These thermal conditions limit the maximum output current for a given input and output voltage. Therefore, proper output current derating must be considered, taking into account ambient temperature, airflow, the input and output conditions, and the need for increased reliability. Figures 24 − 29 show safe operating conditions vs. output current for input voltages of 12 V, 18 V, and 24 V. These curves assumed 300 mm2 of 2 oz copper. Sufficient cooling could also be provided to ensure reliable operation. Finally, to maintain operation in the safe operating areas shown in the curves, it is recommended to use the NCP3155 with input to output conditions as shown in Figure 44. VIN, INPUT VOLTAGE (V) Figure 44. Recommended Maximum Output Voltage vs Input Voltage http://onsemi.com 21 NCP3155A, NCP3155B 0.1m 10.8 – 24 V VIN 150m 22m VIN BST VSW 680p 1.5 47m 820p 47m 19.62k 649 8.2m 5V VOUT NCP3155A ISET PGND FB1 1.8n 24k 18.2k 33p R1 COMP AGND VOUT (V) 1.2 1.5 3.3 5.0 R1 (kW) 39.2k 22.1k 6.19k 3.74k Figure 45. Typical Application Circuit 0.1m 9 − 16 V VIN 150m 22m VIN BST VSW 680p 1.5 220m 2.2n 220m 6.21k 649 4.7m 1.8 V VOUT NCP3155B ISET PGND FB1 12n 22.1k 4.7k COMP 220p 4.99k AGND Figure 46. Typical Application Circuit http://onsemi.com 22 NCP3155A, NCP3155B 0.1m 10.8 − 14 V VIN 150m 22m VIN BST VSW 680p 1.5 22m 560p 22m 19.62k 270 4.7m 3.3 V VOUT NCP3155B ISET PGND FB1 1.2n 24k 27k 10p 6.19k COMP AGND Figure 47. Typical Application Circuit 0.1m 10 − 14 V VIN 150m 22m VIN BST VSW 680p 1.5 220m 680p 10m 15.8k 580 4.7m 3.3 V VOUT NCP3155B ISET PGND FB1 8.2n 22.1k 6.8k COMP 150p 4.99k AGND Figure 48. Typical Application Circuit http://onsemi.com 23 NCP3155A, NCP3155B PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AJ −X− A 8 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244 B 1 S 4 0.25 (0.010) M Y M −Y− G K C −Z− H D 0.25 (0.010) M SEATING PLANE N X 45 _ 0.10 (0.004) M J ZY S X S DIM A B C D G H J K M N S SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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