NCP349MNTBG

NCP349 Positive Overvoltage Protection Controller with Internal Low RON NMOS FET The NCP349 is able to disconnect the systems from its output pin when wrong input operating conditions are detected. The system is positive overvoltage protected up to +28 V. This device uses an internal NMOS and therefore, no external device is necessary, reducing the system cost and the PCB area of the application board. The NCP349 is able to instantaneously disconnect the output from the input, due to integrated Low RON Power NMOS (65 mW), if the input voltage exceeds the overvoltage threshold (OVLO) or falls below the undervoltage threshold (UVLO). At powerup (EN pin = low level), the Vout turns on ton time after the Vin exceeds the undervoltage threshold. The NCP349 provides a negative going flag (FLAG) output, which alerts the system that a fault has occurred. In addition, the device has ESD−protected input (15 kV Air) when bypassed with a 1.0 mF or larger capacitor. Features • • • • • • • • • • • • http://onsemi.com 6 1 DFN6 MN SUFFIX CASE 506BM MARKING DIAGRAM 1 XX MG G XX = Specific Device Code M = Date Code G = Pb−Free Package Overvoltage Protection up to 28 V On−Chip Low RDS(on) NMOS Transistor: 65 mW Internal Charge Pump Overvoltage Lockout (OVLO) Undervoltage Lockout (UVLO) Soft−Start Alert FLAG Output Shutdown EN Input Compliance to IEC61000−4−2 (Level 4) 8.0 kV (Contact) 15 kV (Air) ESD Ratings: Machine Model = B Human Body Model = 2 DFN6 1.6x2 mm Package This is a Pb−Free Device PIN CONNECTIONS IN 1 GND 2 FLAG 3 PAD1 IN 6 EN 5 OUT 4 OUT (Top View) ORDERING INFORMATION See detailed ordering, marking and shipping information in the package dimensions section on page 11 of this data sheet. Applications • • • • • Cell Phones Camera Phones Digital Still Cameras Personal Digital Applications MP3 Players Q © Semiconductor Components Industries, LLC, 2012 September, 2012 − Rev. 3 1 Publication Order Number: NCP349/D NCP349 Wall Adapter − AC/DC − USB 1 mF NCP349 7 IN OUT 5 1 4 IN OUT 6 FLAG EN CC/CV Charger or System VBat 3 BATTERY 10 k ENABLE/ GND Microprocessor 2 mP 0 0 Figure 1. Typical Application Circuit 7 4 INPUT OUTPUT 5 Gate Driver 1 VREF Charge Pump EN Block UVLO OVLO Control Logic and Timer 3 EN FLAG 6 2 GND Figure 2. Functional Block Diagram http://onsemi.com 2 NCP349 PIN FUNCTION DESCRIPTION Pin No. Symbol Function 1, 7 IN INPUT Description Input Voltage Pins. These pins are connected to the Wall Adapoter (AC−DC, Vbus ..). A 1 mF low ESR ceramic capacitor, or larger, must be connected between these pins and GND, as close as possible to the DUT. The two IN pins must be connected together to power supply. (See PCB recommendation for the pin7). 2 GND POWER Ground 3 FLAG OUTPUT Fault Indication Pin. This pin allows an external system to detect a fault on the IN pins. The FLAG pin goes low when input voltage exceeds OVLO threshold or drops below UVLO threshold. Since the FLAG pin is open drain functionality, an external pull−up resistor to VCC must be added. (Minimum 10 kW). 4, 5 OUT OUTPUT Output Voltage Pins. These pins follow IN pins when “no fault” is detected. The two OUT pins must be hardwired together. 6 EN INPUT Enable Pin. The device enters in shutdown mode when this pin is tied to a high level. In this case the output is disconnected from the input. To allow normal functionality, the EN pin shall be connected to GND to a pull down or to a I/O pin. This pin does not have an impact on the fault detection. MAXIMUM RATINGS Rating Symbol Value Unit Vminin −0.3 V Vmin −0.3 V Vmaxin 30 V Maximum Voltage (All others to GND) Vmax 7.0 V Maximum Current (UVLO UVLO to Vout = 0.3 V (See Figures 3 & 7) 1.0 6.0 30 1.8 10 55 2.7 14 70 tstart From Vout = 0.3 V to FLAG = 1.2 V (See Figures 3 & 9) 0.4 6.0 30 1.2 10 55 2.1 14 70 toff From Vin > OVLO to Vout < = 0.3 V (See Figures 4 & 8) Vin increasing from 5.0 V to 8.0 V at 3.0 V/ms Rload connected on Vout − 1.5 5.0 ms Alert Delay tstop From Vin > OVLO to FLAG < = 0.4 V (See Figures 4 & 10) Vin increasing from 5.0 V to 8.0 V at 3.0 V/ms Rload connected on Vout − 1.0 − ms Disable Time tdis From EN > = 1.2 V to Vout < 0.3 V Rload = 5.0 W (See Figures 5 & 12) − 1.0 5.0 ms FLAG Leakage Current EN Leakage Current TIMINGS Startup Delay NCP349MN NCP349MNAE NCP349MNBG, NCP349MNBK, NCP349MNAM FLAG Going Up Delay NCP349MN NCP349MNAE NCP349MNBG, NCP349MNBK, NCP349MNAM Output Turn Off Time ms ms NOTE: Electrical parameters are guaranteed by correlation across the full range of temperature. 4. Additional UVLO and OVLO thresholds ranging from UVLO and from OVLO can be manufactured. Contact your ON Semiconductor representative for availability. http://onsemi.com 4 NCP349 TIMING DIAGRAMS OVLO 0 < VIN < UVLO And/Or VOLTAGE DETECTION /EN = 1 Figure 16. Simplified Diagram CONDITIONS IN OUT /EN = 0 & UVLO < VIN < OVLO VOLTAGE DETECTION Figure 17. Simplified Diagram Operation overtaking undervoltage UVLO (Figure 3). The NCP349 provides a FLAG output, which alerts the system that a fault has occurred. A tstart additional delay, regarding available output (Figure 3) is added between output signal rising up and to FLAG signal rising up. FLAG pin is an open drain output. The NCP349 provides overvoltage protection for positive voltage, up to 28 V. A low RDS(on) NMOSFET protects the systems (i.e.: charger) connected on the Vout pin, against positive overvoltage. At powerup, with EN pin = low, the output is rising up ton soft−start after the input http://onsemi.com 8 NCP349 Vout = 0 FLAG = Low Reset Timer Vin < UVLO or Vin > OVLO Vout = 0 FLAG = Low Timer Count OVLO > Vin > UVLO Timer Check T < ton T = ton Reset Timer Vin < UVLO or Vin > OVLO Check Vin FLAG = Low Timer Count UVLO < Vin < OVLO EN = 1 EN = 0 Check EN Vout = Open Vin < UVLO or Vin > OVLO Vout = Vin T < ton Timer Check T = ton Check EN UVLO < Vin < OVLO EN = 1 Vout = Open FLAG = High Check Vin UVLO < Vin < OVLO EN = 0 Vout = Vin FLAG = High Check Vin Vin < UVLO or Vin > OVLO Figure 18. State Machine http://onsemi.com 9 NCP349 Undervoltage Lockout (UVLO) ESD Tests To ensure proper operation under any conditions, the device has a built−in undervoltage lockout (UVLO) circuit. During Vin positive going slope, the output remains disconnected from input until Vin voltage is below UVLO, plus hysteresis, nominal. The FLAG output is tied to low as long as Vin does not reach UVLO threshold. This circuit has a built−in hysteresis to provide noise immunity to transient condition. Additional UVLO thresholds ranging from UVLO can be manufactured. Contact your ON Semiconductor representative for availability. The NCP349 input pin fully supports the IEC61000−4−2. 1.0 mF (minimum) must be connected between Vin and GND, close to the device. That means, in Air condition, Vin has a ±15 kV ESD protected input. In Contact condition, Vin has ±8.0 kV ESD protected input. Please refer to Figure 19 to see the IEC 61000−4−2 electrostatic discharge waveform. Overvoltage Lockout (OVLO) To protect connected systems on Vout pin from overvoltage, the device has a built−in overvoltage lockout (OVLO) circuit. During overvoltage condition, the output remains disabled as long as the input voltage exceeds typical OVLO. Additional OVLO thresholds ranging from OVLO can be manufactured. Contact your ON Semiconductor representative for availability. FLAG output is tied to low until Vin is higher than OVLO. This circuit has a built−in hysteresis to provide noise immunity to transient conditions. FLAG Output The NCP349 provides a FLAG output, which alerts external systems that a fault has occurred. This pin is tied to low as soon the OVLO threshold is exceeded or when the Vin level is below the UVLO threshold. When Vin level recovers normal condition, FLAG is held high, keeping in mind that an additional tstart delay has been added between available output and FLAG = high. The pin is an open drain output, thus a pull up resistor (typically 1 MW, minimum 10 kW) must be added to Vbat. Minimum Vbat supply must be 2.5 V. The FLAG level will always reflects Vin status, even if the device is turned off (EN = 1). Figure 19. Electrostatic Discharge Waveform PCB Recommendations The NCP349 integrates a 2 A rated NMOSFET, and the PCB rules must be respected to properly evacuate the heat out of the silicon. The pin 7 (exposed pad) is internally connected to the internal NMOS Drain (Input). This exposed pad must be used to increase heat transfer and must be connected to Pin 1. Of course, in any case, this pad shall be not connected to any other potential. Theta JA curve with PCB cu thk 1.0 oz Theta JA curve with PCB cu thk 2.0 oz Power curve with PCB cu thk 2.0 oz Power curve with PCB cu thk 1.0 oz EN Input Internal NMOS FET The NCP349 includes an internal Low RDS(on) NMOS FET to protect the systems, connected on OUT pin, from positive overvoltage. Regarding electrical characteristics, the RDS(on), during normal operation, will create low losses on Vout pin. As example: Rload = 8.0 W, Vin = 5.0 V Typical RDS(on) = 65 mW, Iout = 618 mA Vout = 8 x 0.618 = 4.95 V 200 1.75 180 1.5 160 1.25 140 1 120 0.75 100 0.5 80 60 0 NMOS losses = RDS(on) x Iout2 = 0.065 x 0.6182 = 25 mW 100 200 300 400 http://onsemi.com 500 600 Copper heat spreader area (mm^2) Figure 20. 10 Max Power (W) Theta JA (C/W) To enable normal operation, the EN pin shall be forced to low or connected to ground. A high level on the pin, disconnects OUT pin from IN pin. EN does not overdrive an OVLO or UVLO fault. 0.25 700 NCP349 ORDERING INFORMATION Device Marking NCP349MNTBG AC NCP349MNAETBG AE NCP349MNBGTBG AG NCP349MNBKTBG AK NCP349MNAMTBG AM Package Shipping† DFN6 (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. SELECTION GUIDE The NCP349 can be available in several undervoltage and overvoltage thresholds versions. Part number is designated as follows: NCP349MNxxTxG ab c Code Contents a UVLO Typical Threshold a: − = 2.95 V a: A = 2.95 V a: B = 3.25 V b OVLO Typical Threshold b: E = 5.68 V b: G = 6.02 V b: K = 6.40 V b: − = 6.85 V b: M = 7.2 V c Tape & Reel Type c: B = 3000 http://onsemi.com 11 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DFN6 1.6x2.0, 0.5P CASE 506BM−01 ISSUE O 6 DATE 11 NOV 2008 1 SCALE 4:1 A B D PIN ONE REFERENCE 2X 0.10 C 2X 0.10 C L L1 ÉÉ ÉÉ DETAIL A OPTIONAL CONSTRUCTIONS E MOLD CMPD EXPOSED Cu TOP VIEW DETAIL B 0.05 C A (A3) A1 ÇÇÇ ÉÉÉ DETAIL B OPTIONAL CONSTRUCTION 0.05 C NOTE 4 C SIDE VIEW A1 D2 DETAIL A 1 6X 3 SEATING PLANE 6 5 6X XX MG G XX = Specific Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) 0.10 C A B 0.05 C BOTTOM VIEW MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.20 0.40 1.60 BSC 1.10 1.30 2.00 BSC 0.95 1.15 0.50 BSC 0.20 −−− 0.15 0.35 −−− 0.10 1 L b e A3 DIM A A1 A3 b D D2 E E2 e K L L1 GENERIC MARKING DIAGRAM* E2 K NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.20 mm FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. NOTE 3 MOUNTING FOOTPRINT 1.30 6X 0.43 1.15 2.30 1 6X 0.36 0.50 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON35759E DFN6, 1.6X2.0, 0.5P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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