NCP81253
5 V MOSFET Driver
Compatible with
Single-Phase IMVP8
Controllers
The NCP81253 is a high performance dual MOSFET gate driver in
a small 2 mm x 2 mm package, optimized to drive the gates of both
high−side and low−side power MOSFETs in a synchronous buck
converter. The driver outputs can be placed into a high−impedance
state via the tri−state PWM and EN inputs. The NCP81253 comes
packaged with an integrated boost diode to minimize external
components. A VCC UVLO function guarantees the outputs are low
when the supply voltage is low.
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MARKING
DIAGRAM
•
•
•
Space−efficient 2 mm x 2 mm DFN8 Thermally−enhanced Package
VCC Range of 4.5 V to 5.5 V
Internal Bootstrap Diode
5 V 3−stage PWM Input
Diode Braking Capability via EN Mid−state
Adaptive Anti−cross Conduction Circuit Protects against
Cross−conduction during FET Turn−on and Turn−off
Output Disable Control Turns Off both MOSFETs via Enable Pin
VCC Undervoltage Lockout
These devices are Pb−free, Halogen−free/BFR−free and are RoHS
compliant
Typical Applications
CGMG
G
DFN8
CASE 506AA
CG = Specific Device Code
M = Date Code
G
= Pb−Free Package
Features
•
•
•
•
•
•
1
1
(Note: Microdot may be in either location)
PINOUT DIAGRAM
BST
1
PWM
2
EN
3
VCC
4
• Power Solutions for Notebook and Desktop Systems
FLAG
9
8
DRVH
7
SW
6
GND
5
DRVL
(Top View)
ORDERING INFORMATION
Device
Package
Shipping†
NCP81253MNTBG
DFN8
(Pb−Free)
3000 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2014
December, 2014 − Rev. 0
1
Publication Order Number:
NCP81253/D
NCP81253
BST
VCC
DRVH
PWM
Logic
SW
Anti−Cross
Conduction
VCC
DRVL
EN
UVLO
VCC
Figure 1. Block Diagram
GND
Table 1. PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
Description
1
BST
Floating bootstrap supply pin for the high−side gate driver. Connect the external bootstrap
capacitor between this pin and SW.
2
PWM
Control input:
PWM = High ³ DRVH is high, DRVL is low.
PWM = Mid ³ DRVH and DRVL are low.
PWM = Low ³ DRVH is low, DRVL is high.
3
EN
3−state input:
EN = High ³ Driver is enabled; normal PWM operation.
EN = Mid ³ Driver is enabled; DRVH and DRVL are low (body diode braking).
EN = Low ³ Driver is disabled.
4
VCC
Power supply input. Connect a bypass capacitor from this pin to ground.
5
DRVL
Low−side gate drive output. Connect to the gate of the low−side MOSFET.
6
GND
Bias and reference ground. All signals are referenced to this node.
7
SW
8
DRVH
High−side gate drive output. Connect to the gate of the high−side MOSFET.
9
FLAG
Thermal flag. There is no electrical connection to the IC. Connect to the ground plane.
Switch node. Connect this pin to the source of the high−side MOSFET and drain of the
low−side MOSFET.
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2
NCP81253
Table 2. ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Min
Max
Main Supply Voltage (Note 1)
VCC
−0.3 V
6.5 V
Bootstrap Supply Voltage
BST
−0.3 V wrt/SW
35 V wrt/GND
40 V (v 50 ns) wrt/GND
6.5 V wrt/SW
Switch Node Voltage
SW
−5 V
−10 V (v 200 ns)
35 V
40 V (v 50 ns)
High−Side Driver Output
DRVH
−0.3 V wrt/SW
−2 V (v 200 ns) wrt/SW
BST + 0.3 V wrt/SW
Low−Side Driver Output
DRVL
−0.3 V
−5 V (v 200 ns)
VCC + 0.3 V
PWM, EN
−0.3 V
6.5 V
Ground
GND
0V
0V
Storage Temperature Range
TSTG
−55°C
150°C
TJ
−40°C
DRVH/DRVL Control Input, Enable Pin
Operating Junction Temperature Range
Moisture Sensitivity Level
150°C
MSL
1
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTIS and APPLICATION INFORMATION for Safe Operating Area.
Table 3. THERMAL CHARACTERISTICS
Rating
Symbol
Value
Unit
RqJA
119
°C/W
Thermal Characteristics, DFN8, 2x2 mm (Note 2)
Thermal Resistance, Junction−to−Air
2. Values based on copper area of 645 mm2 (or 1 in2) of 1 oz copper thickness and FR4 PCB substrate.
Table 4. OPERATING RANGES (Note 3)
Rating
Symbol
Min
Max
Unit
VCC
4.5
5.5
V
TA
−40
100
°C
Input Voltage
Ambient Temperature
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
3. Refer to ELECTRICAL CHARACTERISTIS and APPLICATION INFORMATION for Safe Operating Area.
Table 5. ELECTRICAL CHARACTERISTICS VCC = 4.5 V to 5.5 V, VBST−SWN = 4.5 V to 5.5 V, BST = 4.5 V to 30 V, SW = 0 V to
21 V; for typical values TA = 25°C, for min/max values TA = −40°C to 100°C; unless otherwise noted. (Notes 4, 5)
Test Conditions
Parameter
Symbol
Min
VCC
4.5
VUVLO
3.8
VUVLO_HYS
150
Typ
Max
Unit
5.5
V
4.35
4.5
V
200
250
mV
Ishutdown
1
20
mA
SUPPLY VOLTAGE
VCC Operation Voltage
UNDERVOLTAGE LOCKOUT
VCC Start Threshold
VCC rising
VCC UVLO Hysteresis
SUPPLY CURRENT
Shutdown Mode
ICC + IBST, EN = GND
Normal Mode
ICC + IBST, EN = 5 V, PWM = 400 kHz
No load on driver outputs.
Inormal
1.6
mA
Standby Current 1
ICC + IBST, EN = 5 V, PWM = 0 V
Istandby
0.9
mA
4. Refer to ABSOLUTE MAXIMUM RATINGS and APPLICATION INFORMATION for Safe Operating Area.
5. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at TJ = TA = 25°C. Low
duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
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3
NCP81253
Table 5. ELECTRICAL CHARACTERISTICS VCC = 4.5 V to 5.5 V, VBST−SWN = 4.5 V to 5.5 V, BST = 4.5 V to 30 V, SW = 0 V to
21 V; for typical values TA = 25°C, for min/max values TA = −40°C to 100°C; unless otherwise noted. (Notes 4, 5)
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
0.1
0.4
0.6
V
BOOTSTRAP DIODE
Forward Voltage
VCC = 5 V, Forward bias current = 2 mA
PWM INPUT
PWM Input High
PWMHI
3.4
PWM Mid−State
PWMMID
1.3
PWM Input Low
PWMLO
V
2.7
V
0.7
V
HIGH−SIDE DRIVER
Output Impedance, Sourcing Current
VBST – VSW = 5 V
0.9
1.7
W
Output Impedance, Sinking Current
VBST – VSW = 5 V
0.7
1.7
W
DRVH Rise Time
VCC = 5 V, Cload = 3 nF, VBST−VSW = 5 V,
DRVH−SW = 90% to 10%
trDRVH
16
25
ns
DRVH Fall Time
VCC = 5 V, Cload = 3 nF , VBST−VSW = 5 V,
DRVH−SW = 90% to 10%
tfDRVH
11
18
ns
DRVH Turn−Off Propagation Delay
Cload = 3 nF, PWM = PWMLO to DRVH = 90%
tpdlDRVH
10
18
30
ns
DRVH Turn−On Propagation Delay
Cload = 3 nF, DRVL = 1 V to DRVH−SW = 10%
tpdhDRVH
10
15
40
ns
SW Pull−down Resistance
SW to GND
45
kW
DRVH Pull−down Resistance
DRVH to SW
45
kW
Output Impedance, Sourcing Current
VCC = 5 V
0.9
1.7
Output Impedance, Sinking Current
VCC = 5 V
0.4
0.8
W
DRVL Rise Time
VCC = 5 V, Cload = 3 nF, VBST−VSW = 5 V,
DRVL = 90% to 10%
trDRVL
11
25
ns
DRVL Fall Time
VCC = 5 V, Cload = 3 nF , VBST−VSW = 5 V,
DRVL = 90% to 10%
tfDRVL
8
15
ns
DRVL Turn−Off Propagation Delay
Cload = 3 nF, PWM = PWMHI to DRVL = 90%
tpdlDRVL
10
15
30
ns
DRVL Turn−On Propagation Delay
Cload = 3 nF, DRVH−SW = 1 V to DRVL = 10%
tpdhDRVL
5
8
25
ns
DRVL Pull−down Resistance
DRVL to GND, VCC = GND
LOW−SIDE DRIVER
45
W
kW
EN INPUT
Enable Voltage High
ENHI
3.3
Enable Voltage Mid
ENMID
1.35
Enable Voltage Low
ENLO
Input Bias Current
EN High Propagation Delay Time
V
−1.0
PWM = 0 V, EN going from 0 V to ENHI to DRVL tpdEN_HI
rising to 10%
20
1.8
V
0.6
V
1.0
mA
40
ns
20
mA
SWITCH NODE
SW Node Leakage Current
4. Refer to ABSOLUTE MAXIMUM RATINGS and APPLICATION INFORMATION for Safe Operating Area.
5. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at TJ = TA = 25°C. Low
duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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4
NCP81253
TYPICAL CHARACTERISTICS
40
1.2
SUPPLY CURRENT (mA)
STANDBY CURRENT (mA)
35
1.1
1.0
0.9
0.8
30
25
20
15
10
5
0.7
−40
0
−20
0
20
40
60
80
100
100 200
700
800 900 1000
Figure 3. Supply Current vs. Switching
Frequency (VCC = 5 V, Cload = 3 nF)
1.5
PWM THRESHOLD, LOW/MID (V)
VCC UVLO (V)
600
Figure 2. Standby Current vs. Temperature
(VCC = 5 V, EN = 5 V, PWM = 0 V)
Rising
4.3
Falling
4.1
3.9
−20
0
20
40
60
80
1.3
Rising
1.1
Falling
0.9
0.7
0.5
−40
100
−20
0
20
40
60
80
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
Figure 4. VCC UVLO vs. Temperature
(EN = 5 V)
Figure 5. PWM Low/Mid Thresholds vs.
Temperature (VCC = 5 V)
3.5
100
1.5
PWM THRESHOLD LOW/MID (V)
PWM THRESHOLD MID/HIGH (V)
500
SWITCHING FREQUENCY (kHz)
4.5
3.3
Rising
3.1
Falling
2.9
2.7
2.5
−40
400
AMBIENT TEMPERATURE (°C)
4.7
3.7
−40
300
−20
0
20
40
60
80
1.3
1.1
Rising
0.9
Falling
0.7
0.5
−40
100
−20
0
20
40
60
80
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
Figure 6. PWM Mid/High Thresholds vs.
Temperature (VCC = 5 V)
Figure 7. Enable Low/Mid Thresholds vs.
Temperature (VCC = 5 V)
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5
100
NCP81253
TYPICAL CHARACTERISTICS
25
DRVH RISE/FALL TIMES (ns)
PWM THRESHOLD MID/HIGH (V)
3.4
3.2
Rising
3.0
Falling
2.8
2.6
−40
−20
0
20
40
60
80
10
5
−20
0
20
40
60
80
100
Figure 8. Enable Mid/High Thresholds vs.
Temperature (VCC = 5 V)
Figure 9. DRVH Rise/Fall Times vs.
Temperature (VBST − VSW = 5 V, Cload = 3 nF)
25
DRVL RISE/FALL TIMES (ns)
DRVH RISE/FALL TIMES (ns)
Fall Time
AMBIENT TEMPERATURE (°C)
15
Rise Time
10
Fall Time
5
−20
0
20
40
60
80
20
tpdhDRVH
15
10
tpdhDRVL
5
0
−40
100
−20
0
20
40
60
80
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
Figure 10. DRVL Rise/Fall Times vs.
Temperature (VCC = 5 V, Cload = 3 nF)
Figure 11. Dead Times vs. Temperature
(VCC = 5 V, Cload = 3 nF)
25
100
50
20
ENABLE MID PROP DELAYS (ns)
DRVH/DRVL PROP DELAYS (ns)
15
AMBIENT TEMPERATURE (°C)
20
tpdlDRVH
15
tpdlDRVL
10
5
0
−40
Rise Time
0
−40
100
25
0
−40
20
−20
0
20
40
60
80
45
40
High−to−Mid
35
30
Mid−to−High
25
20
15
10
−40
100
−20
0
20
40
60
80
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
Figure 12. DRVH/DRVL Prop Delays vs.
Temperature (VCC = 5 V, Cload = 3 nF)
Figure 13. Enable Mid Prop Delays vs.
Temperature (VCC = 5 V, Cload = 3 nF)
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100
NCP81253
5V_POWER
VIN
R2
C2
0.0
0.1 mF
R1
1.02
C4
4.7 mF
Q1
NTMFS4821N
NCP81253
C5
4.7 mF
C6
4.7 mF
C7
390 mF
R3
BST
DRVH
L
0.0
PWM
PWM
DRON
SW
EN
C1
1 mF
Q2
Q3
NTMFS4851N NTMFS4851N
GND
VCC
VCCP
235 nH
R4
2.2
C3
2700 pF
DRVL
PAD
Figure 14. Application Circuit
PWM
tpdlDRVL
tfDRVL
DRVL
90%
90%
1V
10%
10%
tpdhDRVH
tfDRVH
90%
DRVH−SW
trDRVL
tpdlDRVH
trDRVH
90%
10%
1V
10%
tpdhDRVL
Figure 15. Gate Timing Diagram
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NCP81253
PWM
EN
DRVH
DRVL
Figure 16. PWM/EN Logic Diagram
APPLICATIONS INFORMATION
Bootstrap Circuit
The NCP81253 gate driver is a single−phase MOSFET
driver designed for driving N−channel MOSFETs in a
synchronous buck converter topology. The NCP81253 is
designed to work with single−phase IMVP8 controllers such
as the NCP81206.
The bootstrap circuit relies on an external charge storage
capacitor (CBST) and an integrated diode to provide current
to the high−side driver. A multi−layer ceramic capacitor
(MLCC) with a value greater than 100 nF should be used for
CBST.
Low−Side Driver
Power Supply Decoupling
The low−side driver is designed to drive a
ground−referenced low−RDS(on) N−channel MOSFET. The
voltage supply for the low−side driver is internally
connected to the VCC and GND pins.
The NCP81253 can source and sink relatively large
currents to the gate pins of the MOSFETs. In order to
maintain a constant and stable supply voltage, a low−ESR
capacitor should be placed near the VCC and GND pins. A
MLCC between 1 mF and 4.7 mF is typically used.
High−Side Driver
The high−side driver is designed to drive a floating
low−RDS(on) N−channel MOSFET. The gate voltage for the
high−side driver is developed by a bootstrap circuit
referenced to the SW pin.
The bootstrap circuit is comprised of the integrated diode
and an external bootstrap capacitor. When the NCP81253 is
starting up, the SW pin is held at ground, allowing the
bootstrap capacitor to charge up to VCC through the
bootstrap diode. When the PWM input is driven high, the
high−side driver will turn on the high−side MOSFET using
the stored charge of the bootstrap capacitor. As the high−side
MOSFET turns on, the SW pin rises. When the high−side
MOSFET is fully turned on, SW will settle to VIN and BST
will settle to VIN + VCC (excluding parasitic ringing).
Undervoltage Lockout
DRVH and DRVL are low until VCC reaches the VCC
UVLO threshold, typically 4.35 V. Once VCC reaches this
threshold, the PWM signal will control DRVH and DRVL.
There is a 200 mV hysteresis on VCC UVLO. There are
pull−down resistors on DRVH, DRVL and SW to prevent the
gates of the MOSFETs from accumulating enough charge to
turn on when the driver is powered off.
Three−State EN Input
Placing EN into a logic−high and logic−low will turn the
driver on and off, respectively, as long as VCC is greater than
the UVLO threshold. The EN threshold limits are specified
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8
NCP81253
brought up, but require some time to rise to their proper
levels. To prevent a PWM signal from being interpreted
incorrectly during this time, there is a delay from EN rising
to the driver responding to PWM signals, which is set at a
typical value of 50 ms.
in the electrical characteristics table in this datasheet. Setting
the voltage on EN to a mid−state level will pull both DRVH
and DRVL low. Refer to Table 6 for the EN/PWM logic
table.
Setting EN to the mid−state level can be used for body
diode braking to quickly reduce the inductor current. By
turning the LS FET off and having the current conduct
through the LS FET body diode, the voltage at the switch
node will be at a greater negative potential compared to
having the LS FET on. This greater negative potential on
switch node allows there to be a greater voltage across the
output inductor, since the opposite terminal of the inductor
is connected to the converter output voltage. The larger
voltage across the inductor causes there to be a greater
inductor current slew rate, allowing the current to decrease
at a faster rate.
Table 6. EN/PWM LOGIC TABLE
EN
PWM
DRVH
DRVL
LOW
X
LOW
LOW
HIGH
LOW
LOW
HIGH
HIGH
MID
LOW
LOW
HIGH
HIGH
HIGH
LOW
MID
LOW
LOW
LOW
MID
MID
LOW
LOW
MID
HIGH
LOW
LOW
Three−State PWM Input
Switching PWM between logic−high and logic−low states
will allow the driver to operate in continuous conduction
mode as long as VCC is greater than the UVLO threshold
and EN is high. The threshold limits are specified in the
electrical characteristics table in this datasheet. Refer to
Figure 15 for the gate timing diagrams and Table 6 for the
EN/PWM logic table.
When PWM is set above PWMHI, DRVL will first turn off
after a propagation delay of tpdlDRVL. To ensure
non−overlap between DRVL and DRVH, there is a delay of
tpdhDRVH from the time DRVL falls to 1 V, before DRVH is
allowed to turn on.
When PWM falls below PWMLO, DRVH will first turn
off after a propagation delay of tpdlDRVH. To ensure
non−overlap between DRVH and DRVL, there is a delay of
tpdhDRVL from the time DRVH – SW falls to 1 V, before
DRVL is allowed to turn on.
When PWM enters the mid−state voltage range (and
thereby exiting the logic high or logic low states), both
DRVH and DRVL are pulled low for the non−overlap delay
(tpdh). If PWM is still in the mid−state at the conclusion of
the non−overlap delay, both DRVH and DRVL will remain
in the off states.
To minimize power consumption when the NCP81253 is
in a disabled state, the internal voltage rails that determine
the low/mid/high PWM logic states are shut down when EN
is low. When EN is brought high (while VCC is above the
UVLO threshold), the PWM internal voltage rails are
Thermal Considerations
As power in the NCP81253 increases, it might become
necessary to provide some thermal relief. The maximum
power dissipation supported by the device is dependent
upon board design and layout. Mounting pad configuration
on the PCB, the board material, and the ambient temperature
affect the rate of junction temperature rise for the part. When
the NCP81253 has good thermal conductivity through the
PCB, the junction temperature will be relatively low with
high power applications. The maximum dissipation the
NCP81253 can handle is given by:
P D(MAX) +
ƪTJ(MAX) * TAƫ
R qJA
(eq. 1)
Since TJ is not recommended to exceed 150°C, the
NCP81253, soldered on to a 645 mm2 copper area, using
1 oz. copper and FR4, can dissipate up to 1.05 W when the
ambient temperature (TA) is 25°C. The power dissipated by
the NCP81253 can be calculated from the following
equation:
(eq. 2)
P D [ VCC @ ƪ(n HS @ Qg HS ) n LS @ Qg LS) @ f ) I standbyƫ
Where nHS and nLS are the number of high−side and
low−side FETs, respectively, QgHS and QgLS are the gate
charges of the high−side and low−side FETs, respectively
and f is the switching frequency of the converter.
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN8 2x2, 0.5P
CASE 506AA
ISSUE F
DATE 04 MAY 2016
1
SCALE 4:1
D
PIN ONE
REFERENCE
2X
0.10 C
2X
0.10 C
A
B
L1
ÇÇ
ÇÇ
ÇÇ
DETAIL A
E
OPTIONAL
CONSTRUCTIONS
ÉÉ
ÇÇ
ÉÉ
ÇÇ
EXPOSED Cu
TOP VIEW
A
DETAIL B
0.10 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994 .
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.20 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L
L
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
ÉÉ
ÉÉ
ÇÇ
A3
MOLD CMPD
A1
DETAIL B
0.08 C
(A3)
NOTE 4
SIDE VIEW
DETAIL A
ALTERNATE
CONSTRUCTIONS
A1
C
D2
8X
4
1
SEATING
PLANE
RECOMMENDED
SOLDERING FOOTPRINT*
L
5
8
e/2
e
8X
0.90
b
0.05 C
8X
0.50
2.30
1
0.10 C A B
8X
0.30
NOTE 3
BOTTOM VIEW
0.50
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
GENERIC
MARKING DIAGRAM*
1
1.30
PACKAGE
OUTLINE
E2
K
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.20
0.30
2.00 BSC
1.10
1.30
2.00 BSC
0.70
0.90
0.50 BSC
0.30 REF
0.25
0.35
−−−
0.10
XXMG
G
XX = Specific Device Code
M = Date Code
G
= Pb−Free Device
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98AON18658D
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DFN8, 2.0X2.0, 0.5MM PITCH
PAGE 1 OF 1
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A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
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