NCP51200MNTXG

Linear Voltage Regulator 3A for DDR1, DDR2, DDR3, LPDDR3, DDR4 VTT Termination NCP51200, NCV51200 www.onsemi.com The NCP/NCV51200 is a source/sink Double Data Rate (DDR) termination regulator specifically designed for low input voltage and low−noise systems where space is a key consideration. The NCP/NCV51200 maintains a fast transient response and only requires a minimum output capacitance of 20 mF. The NCP/NCV51200 supports a remote sensing function and all power requirements for DDR VTT bus termination. The NCP/NCV51200 can also be used in low−power chipsets and graphics processor cores that require dynamically adjustable output voltages. The NCP/NCV51200 is available in the thermally−efficient DFN10 Exposed Pad wettable flank package, and is rated both Green and Pb−free. DFN10 CASE 485C MARKING DIAGRAMS 51200 XX ALYWG G Features • • • • • • • • • • • • • • • For Automotive Applications Input Voltage Rails: Supports 2.5 V, 3.3 V and 5 V Rails PVCC Voltage Range: 1.1 to 3.5 V Integrated Power MOSFETs Fast Load−Transient Response PGOOD − Logic output pin to Monitor VTT Regulation EN − Logic input pin for Shutdown mode VRI − Reference Input Allows for Flexible Input Tracking Either Directly or Through Resistor Divider Remote Sensing (VTTS) Built−in Soft Start, Under Voltage Lockout and Over Current Limit Thermal Shutdown Small, Low−Profile 10−pin, 3x3 DFN Package NCV51200MWTXG (SFS), NCV51200MLTXG (SLP); − Wettable Flank Options for Enhanced Optical Inspection NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable* These Devices are Pb−Free and are RoHS Compliant Applications • • • • • • • • June, 2021 − Rev. 14 XX A L Y W G = Specific Device Code = Assembly Location = Wafer Lot (Optional character ) = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) PIN CONNECTION VRI 1 PVCC 2 VTT 3 + 10 VCC 9 PGOOD 8 GND PGND 4 7 EN VTTS 5 6 VRO GND Exposed Pad ORDERING INFORMATION See detailed ordering, marking and shipping information in the package dimensions section on page 8 of this data sheet. DDR Memory Termination Desktop PC’s, Notebooks, and Workstations Servers and Networking equipment Telecom/Datacom, GSM Base Station Graphics Processor Core Supplies Set Top Boxes, LCD−TV/PDP−TV, Copier/Printers Chipset/RAM Supplies as Low as 0.5 V Active Bus Termination © Semiconductor Components Industries, LLC, 2016 DFNW10 CASE 507AM 1 Publication Order Number: NCP51200/D NCP51200, NCV51200 PIN FUNCTION DESCRIPTION Pin Number Pin Name 1 VRI 2 PVCC 3 VTT 4 PGND Power Ground. Internally connected to the output sink MOSFET. 5 VTTS VTT Sense Input. The VTTS pin provides accurate remote feedback sensing of VTT. Connect VTTS to the remote DDR termination bypass capacitors. 6 VRO Independent Buffered VTT Reference Output. Sources and sinks over 5 mA. Connect to GND thru 0.1 mF ceramic capacitor. 7 EN Shutdown Control Input. CMOS compatible input. Logic high = enable, logic low = shutdown. Connect to VDDQ for normal operation. 8 GND 9 PGOOD 10 VCC THERMAL PAD Pin Function VTT External Reference Input ( set to VDDQ / 2 thru resistor network ). Power input. Internally connected to the output source MOSFET. Power Output of the Linear Regulator. Common Ground. Power Good (Open Drain output). Analog power supply input. Connect to GND thru a 1 − 4.7 mF ceramic capacitor. Pad for thermal connection. The exposed pad must be connected to the ground plane using multiple vias for maximum power dissipation performance. ABSOLUTE MAXIMUM RATINGS Rating Symbol Value Unit −0.3 to 6.0 V EN, PGOOD (Note 1) −0.3 to 6.0 V PGND to GND (Note 1) −0.3 to +0.3 V TSTG −55 to 150 °C TJ 150 °C ESDHBM 2000 V VCC, PVCC, VTT, VTTS, VRI, VRO (Note 1) Storage Temperature Operating Junction Temperature Range ESD Capability, Human Body Model (Note 2) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area. 2. This device series incorporates ESD protection and is tested by the following method: ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114) ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115) Latchup Current Maximum Rating tested per JEDEC standard: JESD78. DISSIPATION RATINGS Package TA = 255C Power Rating Derating Factor above TA = 255C TA = +855C Power Rating 10−Pin DFN 1.92 W 19 mW/°C 0.79 W THERMAL INFORMATION NCP51200 (*) DFN 3x3mm 10 pins Unit Junction−to−ambient thermal resistance 53.9 °C/W Junction−to−case (top) thermal resistance 95.5 °C/W RqJB Junction−to−board thermal resistance (1mm from package) 32.3 °C/W YJT Junction−to−top thermal resistance 4.3 °C/W YJB Junction−to−board thermal resistance (1mm from package) 32.3 °C/W Junction−to−case (bot) thermal resistance 14.2 °C/W Symbol RqJA RqJC(top) RqJC(bot) Thermal Metric *1S2P JEDEC JESD51−7 PCB with 240 sqmm, 2 oz copper heat spreader. www.onsemi.com 2 NCP51200, NCV51200 RECOMMENED OPERATING CONDITIONS Symbol Value Unit Supply Voltage Rating VCC 2.375 to 5.5 V Voltage Range VRO −0.1 to 1.8 V VRI 0.5 to 1.8 PVCC, VTT, VTTS, EN, PGOOD −0.1 to 3.5 PGND −0.1 to +0.1 TA −40 to +125 Operating Free−Air Temperature °C Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. ELECTRICAL CHARACTERISTICS −40°C ≤ TA ≤ 125°C; VCC = 3.3 V; PVCC = 1.8 V; VRI = VTTS = 0.9 V; EN = VCC; COUT = 3 x 10 mF (Ceramic); unless otherwise noted. Conditions Parameter Symbol Min Typ Max Units IVCC 0.7 1 mA IVCC SHD 65 80 mA 200 400 2.3 2.375 Supply Current VCC Supply Current TA = +25°C, EN = 3.3 V, No Load VCC Shutdown Current TA = +25°C, EN = 0 V, VRI = 0 V, No Load TA = +25°C, EN = 0 V, VRI > 0.4 V, No Load VCC UVLO Threshold Wake−up, TA = +25°C VUVLO 2.15 Hysteresis 50 PVCC Supply Current TA = +25°C, EN = 3.3 V, No Load PVCC Shutdown Current V mV IPVCC 1 50 mA TA = +25°C, EN = 0 V, No Load IPVCC SHD 0.1 50 mA VRO = 1.25 V (DDR1), ITT = 0 A VOS −15 +15 mV VRO = 0.9 V (DDR2), ITT = 0 A −15 +15 AMN suffix, VRO = 0.6 V (DDR4), ITT = 0 A −15 +15 PVCC = 1.5 V, VRO = 0.75 V (DDR3), ITT = 0 A −15 +15 VTT Voltage Tolerance to VRO −2 A ≤ ITT ≤ +2 A −25 +25 mV Source Current Limit VTTS = 90% * VRO 3 4.5 A Sink Current Limit VTTS = 110% * VRO 3.5 5.5 A VTT Output VTT Output Offset Voltage Soft−start Current Limit Timeout Discharge MOSFET On−resistance VRI = 0 V, VTT = 0.3 V, EN = 0 V, TA = +25°C TSS 200 RDIS 18 ms 25 W 1.8 V +1 mA 435 mV VRI − Input Reference VRI Voltage Range VRI VRI Input−bias Current EN = 3.3 V VRI UVLO Voltage VRI rising VRI UVLO Hysteresis VRI HYS 0.5 IRI 360 390 60 VRO − Output Reference VRO Voltage VRO Voltage Tolerance to VRI VRI V mV IRO = ±10 mA, 0.6 V ≤ VRI ≤ 1.25 V −15 +15 AMN suffix, IRO = ±1 mA, VRI = 0.6 V −12 +12 VRO Source Current Limit VRO = 0 V 10 40 mA VRO Sink Current Limit VRO = 0 V 10 40 mA www.onsemi.com 3 NCP51200, NCV51200 ELECTRICAL CHARACTERISTICS −40°C ≤ TA ≤ 125°C; VCC = 3.3 V; PVCC = 1.8 V; VRI = VTTS = 0.9 V; EN = VCC; COUT = 3 x 10 mF (Ceramic); unless otherwise noted. Parameter Conditions Symbol Min Typ Max Units V/V PGOOD − Powergood Comparator PGOOD Lower Threshold (with respect to VRO) −23.5% −20% −17.5 % PGOOD Upper Threshold (with respect to VRO) 17.5% 20% 23.5% PGOOD Hysteresis 5% PGOOD Start−up Delay Start−up rising edge, VTTS within 15% of VRO PGOOD Leakage Current VTTS = VRI (PGOOD = True) PGOOD = VCC + 0.2 V PGOOD = False Delay VTTS is beyond ±20% PGOOD trip thresholds PGOOD Output Low Voltage IGOOD = 4 mA 2 ms 1 10 ms 0.4 www.onsemi.com 4 mA V NCP51200, NCV51200 ELECTRICAL CHARACTERISTICS −40°C ≤ TA ≤ 125°C; VCC = 3.3 V; PVCC = 1.8 V; VRI = VTTS = 0.9 V; EN = VCC; COUT = 3 x 10 mF (Ceramic); unless otherwise noted. Parameter Conditions Symbol Min EN Logic high VIH 1.7 EN Logic low VIL Typ Max Units EN − Enable Logic Logic Input Threshold Hysteresis Voltage EN pin Logic Leakage Current EN pin, TA = +25°C 0.3 VENHYS IILEAK V 0.5 −1 V +1 mA Thermal Shutdown Thermal Shutdown Temperature TSD 150 °C Thermal Shutdown Hysteresis TSH 25 °C Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. Figure 1. Typical DDR−3 Application Schematic www.onsemi.com 5 NCP51200, NCV51200 Figure 2. Block Diagram www.onsemi.com 6 NCP51200, NCV51200 General limits of the PowerGood window. During initial VTT startup, PGOOD asserts high 2 ms after the VTT enters power good window. Because PGOOD is an open−drain output, a 100 kW, pull−up resistor between PGOOD and a stable active supply voltage rail is required. The LDO has a constant over−current limit (OCL). Note that the OCL level reduces by one−half when the output voltage is not within the power good window. This reduction is non−latch protection. For VCC under−voltage lockout (UVLO) protection, the NCP51200 monitors VCC voltage. When the VCC voltage is lower than the UVLO threshold voltage, both the VTT and VRO regulators are powered off. This shutdown is also non−latch protection. The NCP51200 is a sink/source tracking termination regulator specifically designed for low input voltage and low external component count systems where space is a key application parameter. The NCP51200 integrates a high−performance, low−dropout (LDO) linear regulator that is capable of both sourcing and sinking current. The LDO regulator employs a fast feedback loop so that small ceramic capacitors can be used to support the fast load transient response. To achieve tight regulation with minimum effect of trace resistance, a remote sensing terminal, VTTS, should be connected to the positive terminal of the output capacitors as a separate trace from the high current path from VTT. Thermal Shutdown with Hysteresis VRI − Generation of Internal Voltage Reference If the NCP51200 is to operate in elevated temperatures for long durations, care should be taken to ensure that the maximum operating junction temperature is not exceeded. To guarantee safe operation, the NCP51200 provides on−chip thermal shutdown protection. When the chip junction temperature exceeds 150°C, the part will shutdown. When the junction temperature falls back to 125°C, the device resumes normal operation. If the junction temperature exceeds the thermal shutdown threshold then the VTT and VRO regulators are both shut off, discharged by the internal discharge MOSFETs. The shutdown is a non−latch protection. The output voltage, VTT, is regulated to VRO. When VRI is configured for standard DDR termination applications, VRI can be set by an external equivalent ratio voltage divider connected to the memory supply bus (VDDQ). The NCP51200 supports VRI voltage from 0.5 V to 1.8 V, making it versatile and ideal for many types of low−power LDO applications. VRO − Reference Output When it is configured for DDR termination applications, VRO generates the DDR VTT reference voltage for the memory application. It is capable of supporting both a sourcing and sinking load of 10 mA. VRO becomes active when VRI voltage rises to 435 mV and VCC is above the UVLO threshold. When VRO is less than 360 mV, it is disabled and subsequently discharges to GND through an internal 10 kW MOSFET. VRO is independent of the EN pin state. Tracking Startup and Shutdown The NCP51200 also supports tracking startup and shutdown when EN is tied directly to the system bus and not used to turn on or turn off the device. During tracking startup, VTT follows VRO once VRI voltage is greater than 435 mV. VRI follows the rise of VDDQ memory supply rail via a voltage divider. The typical soft−start time for the VDDQ memory supply rail is approximately 3 ms, however it may vary depending on the system configuration. The SS time of the VTT output no longer depends on the OCL setting, but it is a function of the SS time of the VDDQ memory supply rail. PGOOD is asserted 2 ms after VTT is within ±20% of VRO. During tracking shutdown, VTT falls following VRO until VRO reaches 360 mV. Once VRO falls below 360 mV, the internal discharge MOSFETs are turned on and quickly discharge both VRO and VTT to GND. PGOOD is de−asserted once VTT is beyond the ±20% range of VRO. Soft Start The soft−start function of the VTT pin is achieved via a current clamp. The current clamp allows the output capacitors to be charged with low and constant current, providing a linear ramp−up of the output voltage. When VTT is outside of the power good window, the current clamp level is one−half of the full over−current limit (OCL) level. When VTT rises or falls within the PGOOD window, the current clamp level switches to the full OCL level. The soft−start function is completely symmetrical; it works not only from GND to the VRO voltage but also from PVCC to the VRO voltage. VTT Output Capacitor EN − Enable Control The NCP51200 requires the output capacitor connected as close as possible to the VTT and PGND pins. The regulator has been designed to remain stable with output capacitor’s effective capacitance in range from 20 μF to 1000 μF. The ceramic X7R or X5R type is recommended due to its low capacitance variations over the specified temperature range and low ESR and ESL. When selecting the capacitor value the changes with temperature and DC bias voltage needs to be taken into account. Especially for small package size When EN is driven high, the NCP51200 VTT regulator begins normal operation. When EN is driven low, VTT is discharges to GND through an internal 18−W MOSFET. VREF remains on when EN is driven low. PGOOD − PowerGood The NCP51200 provides an open−drain PGOOD output that goes high when the VTT output is within ±20% of VRO. PGOOD de−asserts within 10 ms after the output exceeds the www.onsemi.com 7 NCP51200, NCV51200 limited). This capacitor provides needed energy during load transients for output capacitor re−charging and from this point of view, the higher value is better. The good starting value is the half of the output capacitor value. The rules mentioned at VTT capacitor paragraph are applicable for PVCC capacitor as well. capacitors, the effective capacitance drops rapidly with the applied DC bias voltage (refer the capacitor’s datasheet for details). Larger capacitance and lower ESR improves the load transient response and PSRR. In the PCB layout, design the traces short and wide and place the capacitor at the same PCB layer as the device (do not use layers changing for the traces). VCC Input Capacitor Add a ceramic capacitor, connected as close as possible to VCC and GND pins. The X7R or X5R capacitor should be used with a value in range from 1 μF to 10 μF is recommended. PVCC Input Capacitor Power input capacitor, connected as close as possible to PVCC and PGND pins, is also necessary to ensure device stability and good transient response. The value of the input capacitor should be 10 μF or greater (max. value is not DEVICE ORDERING INFORMATION Device Marking Code Package Feature Shipping† Non−Wettable Flank 3000 / Tape & Reel Wettable Flank SFS Process 3000 / Tape & Reel NCP51200MNTXG 51200 NCV51200MNTXG* 51200 MN NCV51200MWTXG* 51200 MW NCV51200MLTXG* 51200 ML DFNW10 (Pb−Free) Wettable Flank SLP Process 3000 / Tape & Reel NCP51200AMNTXG 51200 A DFN10 (Pb−Free) Non−Wettable Flank 3000 / Tape & Reel DFN10 (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. www.onsemi.com 8 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DFN10, 3x3, 0.5P CASE 485C ISSUE F SCALE 2:1 DATE 16 DEC 2021 GENERIC MARKING DIAGRAM* XXXXX XXXXX ALYWG G XXXXX = Specific Device Code A = Assembly Location L = Wafer Lot *This information is generic. Please refer to Y = Year device data sheet for actual part marking. W = Work Week Pb−Free indicator, “G” or microdot “G”, may G = Pb−Free Package or may not be present. Some products may (Note: Microdot may be in either location) not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98AON03161D Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. DFN10, 3X3 MM, 0.5 MM PITCH PAGE 1 OF 1 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DFNW10 3x3, 0.5P CASE 507AM ISSUE A DATE 12 JUN 2018 GENERIC MARKING DIAGRAM* XXXXX XXXXX ALYWG G DOCUMENT NUMBER: DESCRIPTION: XXXXX = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) 98AON85414G DFNW10 3x3, 0.5P *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Some products may not follow the Generic Marking. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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