NCP5332ADW

NCP5332A Two−Phase Buck Controller with Integrated Gate Drivers and 5−Bit DAC The NCP5332A is a second−generation, two−phase step down controller which incorporates all control functions required to power high performance processors and high current power supplies. Proprietary multi−phase architecture guarantees balanced load current distribution and reduces overall solution cost in high current applications. Enhanced V2 control architecture provides the fastest possible transient response, excellent overall regulation, and ease of use. The NCP5332A is a second−generation PWM controller because it optimizes transient response by combining traditional Enhanced V 2 with an internal PWM ramp and fast−feedback directly from VCORE to the internal PWM comparator. These enhancements provide greater design flexibility, facilitate use and reduce output voltage jitter. The NCP5332A multi−phase architecture reduces output voltage and input current ripple, allowing for a significant reduction in filter size and inductor values with a corresponding increase in inductor current slew rate. This approach allows a considerable reduction in input and output capacitor requirements, as well as reducing overall solution size and cost.  Semiconductor Components Industries, LLC, 2003 August, 2003 − Rev. 4 1 28 1 SO−28L DW SUFFIX CASE 751F PIN CONNECTIONS AND MARKING DIAGRAM 1 COMP VFB VDRP CS1 CS2 CSREF PWRGD VID0 VID1 VID2 VID3 VID4 ILIM REF A WL, L YY, Y WW, W NCP5332A AWLYYWW Features • Enhanced V2 Control Method with Internal Ramp • Internal PWM Ramp • Fast−Feedback Directly from VCORE • VRM 9.X DAC with 1.0% Accuracy • Adjustable Output Voltage Positioning • 4 On−Board Gate Drivers • 200 kHz to 800 kHz Operation Set by Resistor • Current Sensed through Buck Inductors or Sense Resistors • Hiccup Mode Current Limit • Individual Current Limits for Each Phase • On−Board Current Sense Amplifiers • 3.3 V, 1.0 mA Reference Output • 5 V and 12 V, or 12 V Only Operation • On/Off Control (through Soft Start Pin) • Power Good Output with Internal Delay http://onsemi.com 28 ROSC VCCL VCCL1 GATE(L)1 GND GATE(H)1 VCCH1 LGND SS VCCL2 GATE(L)2 GND2 GATE(H)2 VCCH2 = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION Device Package Shipping NCP5332ADW SO−28L 26 Units/Rail NCP5332ADWR2 SO−28L 1000 Tape & Reel Publication Order Number: NCP5332A/D NCP5332A L1 300 nH D1 BAT54SLT1 +12 V D3 MBRA120LT3 C1 1.0 µF 10 Ω ENABLE C2 1.0 µF D2 BAT54SLT1 1.0 µF + CINPUT Electrolytics CQ1 0.1 µF R3 CAMP 2.2 nF CVFBK 470 pF CCMP1 2.2 nF VFB 330 Q5 2N3904 CVCC 1.0 µF SIGGND RCSREF 36 k CCSREF 0.01 µF SIGGND RLIM2 1.0 k RLIM1 3.6 k SIGGND CSREF PWRGD VID0 VID1 VID2 VID3 VID4 COMP VFB VDRP Cs1 CS2 CSREF PWRGD VID0 VID1 VID2 VID3 VID4 ILIM REF CREF 0.1 µF ROSC 65 k ROSC VCCL VCCL1 GL1 GND1 GH1 VCCH1 LGND SS VCCL2 GL2 GND2 GH2 VCCH2 NCP5332A SIGGND CS1 L2 770 nH CVCCLx 1.0 µF Q2 D4 18 V COUT Electrolytics 1.0 k 1.0 µF BAV199LT1 CVCCHx 1.0 µF 1.0 µF Q3 L3 770 nH BAV199LT1 Q4 SIGGND CSS 0.1 µF SIGGND RCS1 71 k 1.0 k SWNODE1 SWNODE2 CCS2 0.01 µF CCER VCORE Ceramics CQ3 0.1 µF CS2 CCS1 0.01 µF + RDRP 6.98 k Q1 BZX84C18LT1 RVFBK 2.0 k RCS2 71 k Recommended Components: L1: Coiltronics P/N CTX15−14771 or T30−26 core with 3T of #16 AWG L2: T50−52B with 5T of #16 AWG Bifilar CINPUT: 3 × Sanyo Oscon 16SP270M (270 µF, 16 V, 4.4 ARMS, 18 mΩ) COUT: 10 × Rubycon 16MBZ1500M10x20 (1500 µF, 16 V, 13 mΩ) or 8 × Sanyo Oscon 4SP820M (820 µF, 4 V, 12 mΩ) CCERAMICS: 12 × Panasonic ECJ−3YB0J106K (10 µF, 6.3 V) Q1−Q4: ON Semiconductor NTB85N03T1 Figure 1. Application Diagram, 12 V Only to 1.6 V at 45 A, 220 kHz http://onsemi.com 2 NCP5332A +12 V L1 300 nH +5.0 V D1 MBRA120LT3 + 2.2 Ω CQ1 0.1 µF ENABLE CAMP 2.2 nF RVFBK 1.0 k CVFBK 470 pF Q1 CVCC 1.0 µF CCMP1 2.2 nF VFB L2 400 nH Q2 SIGGND RCSREF 9.1 k CCSREF 0.01 µF SIGGND RLIM1 2.0 k SIGGND CSREF PWRGD VID0 VID1 VID2 VID3 VID4 COMP VFB VDRP Cs1 CS2 CSREF PWRGD VID0 VID1 VID2 VID3 VID4 ILIM REF CREF 0.1 µF NCP5332A SIGGND CS1 COUT Electrolytics ROSC 39.2 k ROSC VCCL VCCL1 GL1 GND1 GH1 VCCH1 LGND SS VCCL2 GL2 GND2 GH2 VCCH2 + RDRP 3.4 k RLIM2 1.0 k CINPUT Electrolytics CVCCLx 1.0 µF CVCCHx 1.0 µF CQ3 0.1 µF Q3 L3 400 nH Q4 SIGGND CSS 0.1 µF SIGGND RCS1 18 k SWNODE1 CS2 CCS1 0.01 µF VCORE CCER Ceramics SWNODE2 CCS2 0.01 µF RCS2 18 k Recommended Components: L1: Coiltronics P/N CTX15−14771 or T30−26 core with 3T of #16 AWG L2: Coiltronics P/N CTX15−14811 or T60−2 with 8T of #16 AWG Bifilar Figure 2. Alternate Application Diagram, 5.0 V (with 12 V Bias) to 1.6 V at 45 A, 335 kHz http://onsemi.com 3 NCP5332A MAXIMUM RATINGS* Rating Operating Junction Temperature Lead Temperature Soldering: Reflow: (SMD styles only) (Note 1) Package Thermal Resistance: Junction−to−Case, RθJC Junction−to−Ambient, RθJA Storage Temperature Range ESD Susceptibility: Human Body Model Machine Model JEDEC Moisture Sensitivity Value Unit 150 °C 230 peak °C 15 75 °C/W °C/W −65 to +150 °C 2.0 200 kV V Level 2 − 1. 60 second maximum above 183°C. *The maximum package power dissipation must be observed. MAXIMUM RATINGS Pin Name VMAX VMIN ISOURCE ISINK COMP 6.0 V −0.3 V 1.0 mA 1.0 mA VFB 6.0 V −0.3 V 1.0 mA 1.0 mA VDRP 6.0 V −0.3 V 1.0 mA 1.0 mA CS1, CS2 6.0 V −0.3 V 1.0 mA 1.0 mA CSREF 6.0 V −0.3 V 1.0 mA 1.0 mA ROSC 6.0 V −0.3 V 1.0 mA 1.0 mA PWRGD 6.0 V −0.3 V 1.0 mA 8.0 mA VID Pins 6.0 V −0.3 V 1.0 mA 1.0 mA ILIM 6.0 V −0.3 V 1.0 mA 1.0 mA REF 6.0 V −0.3 V 1.0 mA 20 mA SS 6.0 V −0.3 V 1.0 mA 1.0 mA VCCL 16 V −0.3 V N/A 50 mA VCCHx 20 V −0.3 V N/A 1.5 A for 1.0 µs, 200 mA DC VCCLx 16 V −0.3 V N/A 1.5 A for 1.0 µs, 200 mA DC GATE(H)x 20 V −2.0 V for 100 ns, −0.3 V DC 1.5 A for 1.0 µs, 200 mA DC 1.5 A for 1.0 µs, 200 mA DC GATE(L)x 16 V −2.0 V for 100 ns, −0.3 V DC 1.5 A for 1.0 µs, 200 mA DC 1.5 A for 1.0 µs, 200 mA DC GND1, GND2 0.3 V −0.3 V 2.0 A for 1.0 µs, 200 mA DC N/A LGND 0V 0V 50 mA N/A http://onsemi.com 4 NCP5332A ELECTRICAL CHARACTERISTICS (0°C < TA < 70°C; 0°C < TJ < 125°C; 9.5 V < VCCH1 = VCCH2 < 20 V; 4.5 V < VCCL = VCCL1 = VCCL2 < 14 V; CGATE = 3.3 nF, RR(OSC) = 32.4 kΩ, CCOMP = 1.0 nF, CREF = 0.1 µF, CSS = 0.1 µF, DAC Code 10000 (1.45 V), CVCC = 1.0 µF; unless otherwise specified.) Test Conditions Characteristic Min Typ Max Unit ± 1.0 % Voltage Identification DAC Accuracy (all codes) Measure VFB = COMP VID4 VID3 VID2 VID1 VID0 1 1 1 1 1 − 1 1 1 1 0 − 1.089 1.100 1.111 V 1 1 1 0 1 − 1.114 1.125 1.136 V 1 1 1 0 0 − 1.139 1.150 1.162 V 1 1 0 1 1 − 1.163 1.175 1.187 V 1 1 0 1 0 − 1.188 1.200 1.212 V 1 1 0 0 1 − 1.213 1.225 1.237 V 1 1 0 0 0 − 1.238 1.250 1.263 V 1 0 1 1 1 − 1.262 1.275 1.288 V 1 0 1 1 0 − 1.287 1.300 1.313 V 1 0 1 0 1 − 1.312 1.325 1.338 V 1 0 1 0 0 − 1.337 1.350 1.364 V 1 0 0 1 1 − 1.361 1.375 1.389 V 1 0 0 1 0 − 1.386 1.400 1.414 V 1 0 0 0 1 − 1.411 1.425 1.439 V 1 0 0 0 0 − 1.436 1.450 1.465 V 0 1 1 1 1 − 1.460 1.475 1.490 V 0 1 1 1 0 − 1.485 1.500 1.515 V 0 1 1 0 1 − 1.510 1.525 1.540 V 0 1 1 0 0 − 1.535 1.550 1.566 V 0 1 0 1 1 − 1.559 1.575 1.591 V 0 1 0 1 0 − 1.584 1.600 1.616 V 0 1 0 0 1 − 1.609 1.625 1.641 V 0 1 0 0 0 − 1.634 1.650 1.667 V 0 0 1 1 1 − 1.658 1.675 1.692 V 0 0 1 1 0 − 1.683 1.700 1.717 V 0 0 1 0 1 − 1.708 1.725 1.742 V 0 0 1 0 0 − 1.733 1.750 1.768 V 0 0 0 1 1 − 1.757 1.775 1.793 V 0 0 0 1 0 − 1.782 1.800 1.818 V 0 0 0 0 1 − 1.807 1.825 1.843 V 0 0 0 0 0 − 1.832 1.850 1.869 V Fault Mode − Output Off V Input Threshold VID4, VID3, VID2, VID1, VID0 1.00 1.25 1.50 V Input Pull−up Resistance VID4, VID3, VID2, VID1, VID0 25 50 100 kΩ 3.15 3.30 3.45 V Pull−up Voltage − http://onsemi.com 5 NCP5332A ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < 70°C; 0°C < TJ < 125°C; 9.5 V < VCCH1 = VCCH2 < 20 V; 4.5 V < VCCL = VCCL1 = VCCL2 < 14 V; CGATE = 3.3 nF, RR(OSC) = 32.4 kΩ, CCOMP = 1.0 nF, CREF = 0.1 µF, CSS = 0.1 µF, DAC Code 10000 (1.45 V), CVCC = 1.0 µF; unless otherwise specified.) Characteristic Test Conditions Min Typ Max Unit Power Good Output Power Good Fault Delay CSREF = DAC to 2.5 V 60 120 240 µs PWRGD Low Voltage CSREF = 1.0 V, IPWRGD = 4.0 mA − 0.25 0.40 V Output Leakage Current CSREF = 1.45 V, PWRGD = 5.5 V − 0.1 10 µA Lower Threshold % of Nominal VID −18 −14 −11 % 1.90 2.03 2.15 V Upper Threshold − Voltage Feedback Error Amplifier VFB Bias Current 1.0 V < VFB < 1.9 V. Note 2. 27 31 34.5 µA COMP Source Current COMP = 0.5 V to 2.0 V; VFB = 1.8 V; DAC = 00000 15 30 60 µA COMP Sink Current COMP = 0.5 V to 2.0 V; VFB = 1.9 V; DAC = 00000 15 30 60 µA COMP Clamp Voltage SS = 0.25 V to 2.5 V; VFB = LGND; Measure COMP, Note 3. − − SS Voltage V COMP Max Voltage COMP Open; VFB = 1.8 V; DAC = 00000 2.4 2.7 − V COMP Min Voltage COMP Open; VFB = 1.9 V; DAC = 00000 − 0.1 0.2 V Transconductance −10 µA < ICOMP < +10 µA, Note 3. − 32 − mmho Output Impedance Note 3. − 2.5 − MΩ Open Loop DC Gain Note 3. 60 90 − dB Unity Gain Bandwidth 0.01 µF COMP Capacitor, Note 3. − 400 − kHz PSRR @ 1.0 kHz Note 3. − 70 − dB Soft Start Charge Current 0.2 V ≤ SS ≤ 3.0 V 15 30 50 µA Soft Start Discharge Current 0.2 V ≤ SS ≤ 3.0 V 4.0 7.5 13 µA Soft Start Hiccup Mode Charge/Discharge Ratio − 3.0 4.0 − − Soft Start Clamp Voltage − 3.3 4.0 4.2 V Soft Start Discharge Threshold Voltage − 0.20 0.27 0.34 V − 350 475 ns 0.3 0.4 0.5 V PWM Comparators Minimum Pulse Width CS1 = CS2 = CSREF Channel Start Up Offset V(CS1) = V(CS2) = V(VFB) = V(CSREF) = 0 V; Measure V(COMP) when GATE(H)1, GATE(H)2, switch high GATE(H) and GATE(L) High Voltage (AC) Measure VCCLX − GATE(L)X or VCCHX − GATE(H)X. Note 3. − 0 1.0 V Low Voltage (AC) Measure GATE(L)X or GATE(H)X. Note 3. − 0 0.5 V Rise Time GATE(H)X 1.0 V < GATE < 8.0 V; VCCHX = 10 V − 35 80 ns 2. The VFB Bias Current changes with the value of ROSC per Figure 5. 3. Guaranteed by design. Not tested in production. http://onsemi.com 6 NCP5332A ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < 70°C; 0°C < TJ < 125°C; 9.5 V < VCCH1 = VCCH2 < 20 V; 4.5 V < VCCL = VCCL1 = VCCL2 < 14 V; CGATE = 3.3 nF, RR(OSC) = 32.4 kΩ, CCOMP = 1.0 nF, CREF = 0.1 µF, CSS = 0.1 µF, DAC Code 10000 (1.45 V), CVCC = 1.0 µF; unless otherwise specified.) Characteristic Test Conditions Min Typ Max Unit GATE(H) and GATE(L) Rise Time GATE(L)X 1.0 V < GATE < 8.0 V; VCCLX = 10 V − 35 80 ns Fall Time GATE(H)X 8.0 V > GATE > 1.0 V; VCCHX = 10 V − 35 80 ns Fall Time GATE(L)X 8.0 V > GATE > 1.0 V; VCCLX = 10 V − 35 80 ns GATE(H)x to GATE(L)x Delay GATE(H)X < 2.0 V, GATE(L)X > 2.0 V 30 65 110 ns GATE(L)x to GATE(H)x Delay GATE(L)X < 2.0 V, GATE(H)X > 2.0 V 30 65 110 ns GATE Pull−Down Force 100 µA into GATE with VCCHX and VCCLX = 2.0 V. − 1.2 1.6 V Oscillator Switching Frequency Measure any phase (ROSC = 32.4 k) 340 400 460 kHz Switching Frequency Measure any phase (ROSC = 63.4 k). Note 4. 150 200 250 kHz Switching Frequency Measure any phase (ROSC = 16.2 k). Note 4. 600 800 1000 kHz ROSC Voltage − − 1.0 − V Phase Delay − 165 180 195 deg −15 − 15 mV − − 2.3 V 260 330 400 mV 2.6 3.3 4.0 V/V Adaptive Voltage Positioning VDRP Output Voltage to DACOUT Offset CS1 = CS2 = CSREF, VFB = COMP Measure VDRP − COMP VDRP Operating Voltage Range Measure VDRP − GND, Note 4. Maximum VDRP Voltage (CS1 = CS2) − CSREF = 50 mV, VFB = COMP, Measure VDRP − COMP Current Sense Amp to VDRP Gain − Current Sensing and Sharing CS1−CS2 Input Bias Current V(CSx) = V(CSREF) = 0 V − 0.1 2.0 µA CSREF Input Bias Current V(CSx) = V(CSREF) = 0 V − 0.3 4.0 µA 3.15 3.5 3.9 V/V Current Sense Amplifier Gain − Current Sense Amp Mismatch (The Sum of Gain and Offset Errors.) 0 ≤ (CSx − CSREF) ≤ 50 mV. Note 4. −5.0 − 5.0 mV Current Sense Input to ILIM Gain 0.5 V < ILIM < 1.00 V 5.5 6.75 8.5 V/V 4.0 10 26 mV/µs Current Limit Filter Slew Rate − ILIM Operating Voltage Range Note 4. − − 1.3 V ILIM Bias Current 0 < ILIM < 1.0 V − 0.1 1.0 µA Single Phase Pulse−by−Pulse Current Limit Measure V(CSx) − V(CSREF) that Trips Pulse−by−Pulse Limit 90 105 135 mV Current Share Amplifier Bandwidth Note 4. 1.0 − − MHz General Electrical Specifications VCCL Operating Current VFB = COMP (no switching) − 22 26 mA VCCL1 or VCCL2 Operating Current VFB = COMP (no switching) − 4.5 6.0 mA 4. Guaranteed by design. Not tested in production. http://onsemi.com 7 NCP5332A ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < 70°C; 0°C < TJ < 125°C; 9.5 V < VCCH1 = VCCH2 < 20 V; 4.5 V < VCCL = VCCL1 = VCCL2 < 14 V; CGATE = 3.3 nF, RR(OSC) = 32.4 kΩ, CCOMP = 1.0 nF, CREF = 0.1 µF, CSS = 0.1 µF, DAC Code 10000 (1.45 V), CVCC = 1.0 µF; unless otherwise specified.) Characteristic Test Conditions Min Typ Max Unit − 3.2 4.5 mA General Electrical Specifications VCCH1 or VCCH2 Operating Current VFB = COMP (no switching) VCCL Start Threshold GATEs switching, Soft Start charging 4.05 4.3 4.5 V VCCL Stop Threshold GATEs stop switching, Soft Start discharging 3.75 4.1 4.35 V VCCL Hysteresis GATEs not switching, Soft Start not charging 100 200 300 mV VCCH1 Start Threshold GATEs switching, Soft Start charging 8.7 9.2 9.7 V VCCH1 Stop Threshold GATEs stop switching, Soft Start discharging 6.9 7.4 7.9 V VCCH1 Hysteresis GATEs not switching, Soft Start not charging 1.5 1.8 2.1 V 0 mA < I(VREF) < 1.0 mA 3.2 3.3 3.4 V − 125 − mV Reference Output VREF Output Voltage Internal Ramp Ramp Height @ 50% PWM Duty−Cycle CS1 = CS2 = CSREF. PACKAGE PIN DESCRIPTION PACKAGE PIN # SO−28L PIN SYMBOL 1 COMP 2 VFB 3 VDRP Current sense output for AVP. The offset of this pin above the DAC voltage is proportional to the output current. Connect a resistor from this pin to VFB to set amount AVP or leave this pin open for no AVP. This pin’s maximum working voltage is 2.3 Vdc. 4−5 CS1−CS2 Current sense inputs. Connect current sense network for the corresponding phase to each input. The input voltages to these pins must be kept within 105 mV of CSREF or pulse− by−pulse current limit will be tripped. 6 CSREF Reference for Current Sense Amplifiers, input to the Power Good comparators, and fast feedback connection to the PWM comparator. To balance input offset voltages between the inverting and noninverting inputs of the Current Sense Amplifiers, connect a resistor between CSREF and the output voltage. The value should be 1/3 of the value of the resistors connected to the CSx pins. The input voltage to this pin must not exceed the maximum DAC (VID) setting by more than 100 mV or the internal PWM comparator may saturate. 7 PWRGD Power Good Output. Open collector output goes low when CSREF (VCORE) is out of regulation. 8−12 VID4−VID0 Voltage ID DAC inputs. These pins are internally pulled up to 3.3 V if left open. FUNCTION Output of the error amplifier and input for the PWM comparators. Voltage Feedback Pin. To use Adaptive Voltage Positioning (AVP) select an offset voltage at light load and connect a resistor between VFB and VCORE. The output current of the VFB pin and the resistor value determine output voltage offset for zero output current. Short VFB to VCORE for no AVP. http://onsemi.com 8 NCP5332A PACKAGE PIN DESCRIPTION (continued) PACKAGE PIN # SO−28L PIN SYMBOL FUNCTION 13 ILIM Sets threshold for current limit. Connect to reference through a resistive divider. This pin’s maximum working voltage is 1.3 Vdc. 14 REF Reference output. Decouple with 0.1 µF to LGND. 15 VCCH2 16 GATE(H)2 17 GND2 18 GATE(L)2 19 VCCL2 20 SS Soft Start capacitor pin. The Soft Start capacitor controls both Soft Start time and hiccup mode frequency. The COMP pin is clamped below Soft Start during Start−Up and hiccup mode. 21 LGND Return for internal control circuits and IC substrate connection. 22 VCCH1 Power for GATE(H)1. UVLO Sense for High Side Driver supply connects to this pin. 23 GATE(H)1 24 GND1 Return #1 drivers. 25 GATE(L)1 Low side driver #1. 26 VCCL1 Power for GATE(L)1. 27 VCCL Power for internal control circuits. UVLO Sense for Logic connects to this pin. 28 ROSC A resistor from this pin to ground sets operating frequency and VFB bias current. Power for GATE(H)2. High side driver #2. Return for #2 drivers. Low side driver #2. Power for GATE(L)2. High side driver #1. http://onsemi.com 9 Figure 3. Block Diagram http://onsemi.com 10 ILIM CS2 CS1 CSREF LGND ROSC VID2 VID3 VID4 VID0 VID1 VCCL GCSA2 3.50 − + + − GCSA1 3.50 + − OSC VFB_BIAS Start 4.3 V Stop 4.1 V − + GILIM 1.93 GVDRP 0.94 Σ Summer 0.4 V −+ SU Offset − + Error Amp VCCH1 + − + SS Discharge Threshold 0.27 V Shutdown Current Limit VCCH1 Fault + − CO2 RAMP2 SU Offset CO1 + SU Offset RAMP1 COMP Start 9.2 V Stop 7.4 V − + Slew Rate Limit PH2 PH1 Shutdown VCCL Fault Summer CO2 Σ CO1 11111 OUT Current Gen 5−Bit DAC 3.3 V REF VFB + − RESET + − DAC OUT CSREF MAXC2 + − − + PWMC2 0.367 V +− MAXC1 + − PWMC1 − + R S Fault D F/F R S R S Q Q Q COMP Clamp D F/F Q RESET Dominant D F/F Q ON SS Charge Current 30 µA ON SS Discharge Current 7.5 µA − + − + Q SET Dominant +− −14% −+ 2.0 V PH2 PH1 RESET Dominant Non−Overlap Gate Driver Gate Driver VCCL 120 µs Delay Non−Overlap 3.3 V + − VCCL SS Clamp 4.0 V Soft Start VDRP PWRGD GND2 GATE(L)2 VCCL2 GATE(H)2 VCCH2 GND1 GATE(L)1 VCCL1 GATE(H)1 VCCH1 NCP5332A NCP5332A TYPICAL PERFORMANCE CHARACTERISTICS 900 75 800 60 VFB Bias Current, µA Frequency (kHz) 700 600 500 400 300 45 30 15 200 100 10 20 30 40 50 ROSC Value (kΩ) 60 0 10 70 120 120 100 100 80 80 60 40 20 20 0 2 4 6 8 10 Load Capacitance, nF 12 14 0 16 120 120 100 100 80 80 60 40 20 20 2 4 6 8 10 Load Capacitance, nF 12 14 70 80 0 2 4 6 8 10 Load Capacitance, nF 12 14 16 60 40 0 60 Figure 7. GATE(H) Fall Time vs. Load Capacitance Measured from 4.0 V to 1.0 V with VCC at 5.0 V Time, ns Time, ns Figure 6. GATE(H) Rise Time vs. Load Capacitance Measured from 1.0 V to 4.0 V with VCC at 5.0 V 0 40 50 ROSC Value, kΩ 60 40 0 30 Figure 5. VFB Bias Current vs. ROSC Value Time, ns Time, ns Figure 4. Oscillator Frequency vs. ROSC Value 20 0 16 0 2 4 6 8 10 Load Capacitance, nF 12 14 Figure 9. GATE(L) Fall Time vs. Load Capacitance Measured from 4.0 V to 1.0 V with VCC at 5.0 V Figure 8. GATE(L) Rise Time vs. Load Capacitance Measured from 1.0 V to 4.0 V with VCC at 5.0 V http://onsemi.com 11 16 NCP5332A APPLICATIONS INFORMATION Overview currents in individual phases. Each phase is delayed 180° from the previous phase. Normally, GATE(H) transitions to a high voltage at the beginning of each oscillator cycle. Inductor current ramps up until the combination of the current sense signal, the internal ramp and the output voltage ripple trip the PWM comparator and bring GATE(H) low. Once GATE(H) goes low, it will remain low until the beginning of the next oscillator cycle. While GATE(H) is high, the Enhanced V2 loop will respond to line and load variations. On the other hand, once GATE(H) is low, the loop can not respond until the beginning of the next PWM cycle. Therefore, constant frequency Enhanced V2 will typically respond to disturbances within the off−time of the converter. The Enhanced V2 architecture measures and adjusts the output current in each phase. An additional input (CSn) for inductor current information has been added to the V2 loop for each phase as shown in Figure 10. The triangular inductor current is measured differentially across RS, amplified by CSA and summed with the Channel Startup Offset, the Internal Ramp, and the Output Voltage at the non−inverting input of the PWM comparator. The purpose of the Internal Ramp is to compensate for propagation delays in the NCP5332A. This provides greater design flexibility by allowing smaller external ramps, lower minimum pulse widths, higher frequency operation, and PWM duty cycles above 50% without external slope compensation. As the sum of the inductor current and the internal ramp increase, the voltage on the positive pin of the PWM comparator rises and terminates the PWM cycle. If the inductor starts a cycle with higher current, the PWM cycle will terminate earlier providing negative feedback. The NCP5332A provides a CSn input for each phase, but the CSREF and COMP inputs are common to all phases. Current sharing is accomplished by referencing all phases to the same CSREF and COMP pins, so that a phase with a larger current signal will turn off earlier than a phase with a smaller current signal. The NCP5332A DC/DC controller from ON Semiconductor was developed using the Enhanced V2 topology to meet requirements of low voltage, high current loads with fast transient requirements. Enhanced V2 combines the original V2 topology with peak current−mode control for fast transient response and current sensing capability. The addition of an internal PWM ramp and implementation of fast−feedback directly from VCORE has improved transient response and simplified design. The NCP5332A includes Power Good (PWRGD) and MOSFET gate drivers to provide a “fully integrated solution” to simplify design, minimize circuit board area, and reduce overall system cost. Two advantages of a multi−phase converter over a single−phase converter are current sharing and increased apparent output frequency. Current sharing allows the designer to use less inductance in each phase than would be required in a single−phase converter. The smaller inductor will produce larger ripple currents but the total per phase power dissipation is reduced because the RMS current is lower. Transient response is improved because the control loop will measure and adjust the current faster in a smaller output inductor. Increased apparent output frequency is desirable because the off time and the ripple voltage of the two−phase converter will be less than that of a single−phase converter. Fixed Frequency Multi−Phase Control In a multi−phase converter, multiple converters are connected in parallel and are switched on at different times. This reduces output current from the individual converters and increases the apparent ripple frequency. Because several converters are connected in parallel, output current can ramp up or down faster than a single converter (with the same value output inductor) and heat is spread among multiple components. The NCP5332A controller uses two−phase, fixed frequency, Enhanced V2 architecture to measure and control n = 1 or 2 SWNODE Ln RLn CSn + CSA COn RSn Internal Ramp CSREF VOUT (VCORE) −+ “Fast−Feedback” Connection + VFB E.A. + DAC Out Channel Start−Up Offset To F/F Reset + PWM COMP COMP + Figure 10. Enhanced V2 Control Employing Resistive Current Sensing and Additional Internal Ramp http://onsemi.com 12 NCP5332A Enhanced V2 responds to disturbances in VCORE by employing both “slow” and “fast” voltage regulation. The internal error amplifier performs the slow regulation. Depending on the gain and frequency compensation set by the amplifier’s external components, the error amplifier will typically begin to ramp its output to react to changes in the output voltage in 1−2 PWM cycles. Fast voltage feedback is implemented by a direct connection from VCORE to the non−inverting pin of the PWM comparator via the summation with the inductor current, internal ramp, and Offset. A rapid increase in load current will produce a negative offset at VCORE and at the output of the summer. This will cause the PWM duty cycle to increase almost instantly. Fast feedback will typically adjust the PWM duty cycle in 1 PWM cycle. As shown in Figure 10, an internal ramp (nominally 125 mV at a 50% duty cycle) is added to the inductor current ramp at the positive terminal of the PWM comparator. This additional ramp compensates for propagation time delays from the current sense amplifier (CSA), the PWM comparator, and the MOSFET gate drivers. As a result, the minimum ON time of the controller is reduced and lower duty cycles may be achieved at higher frequencies. Also, the additional ramp reduces the reliance on the inductor current ramp and allows greater flexibility when choosing the output inductor and the RCSnCCSn (n = 1 or 2) time constant of the feedback components from VCORE to the CSn pin. Including both current and voltage information in the feedback signal allows the open loop output impedance of the power stage to be controlled. When the average output current is zero, the COMP pin will be: Or, in a closed loop configuration when the output current changes, the COMP pin must move to keep the same output voltage. The required change in the output voltage or COMP pin depends on the scaling of the current feedback signal and is calculated as:
V  RS  GCSA 
IOUT. The single−phase power stage output impedance is: Single Stage Impedance 
VOUT
IOUT  RS  GCSA The multi−phase power stage output impedance is the single−phase output impedance divided by the number of phases. The output impedance of the power stage determines how the converter will respond during the first few microseconds of a transient before the feedback loop has repositioned the COMP pin. The peak output current can be calculated from: IOUT,PEAK  (VCOMP  VOUT  Offset)(RS  GCSA) Figure 11 shows the step response of the COMP pin at a fixed level. Before T1 the converter is in normal steady state operation. The inductor current provides a portion of the PWM ramp through the Current Sense Amplifier. The PWM cycle ends when the sum of the current ramp, the “partial” internal ramp voltage signal and Offset exceed the level of the COMP pin. At T1 the output current increases and the output voltage sags. The next PWM cycle begins and the cycle continues longer than previously while the current signal increases enough to make up for the lower voltage at the VFB pin and the cycle ends at T2. After T2 the output voltage remains lower than at light load and the average current signal level (CSn output) is raised so that the sum of the current and voltage signal is the same as with the original load. In a closed loop system the COMP pin would move higher to restore the output voltage to the original level. VCOMP  VOUT @ 0 A  Channel_Startup_Offset  Int_Ramp  GCSA  Ext_Ramp2 Int_Ramp is the “partial” internal ramp value at the corresponding duty cycle, Ext_Ramp is the peak−to−peak external steady−state ramp at 0 A, GCSA is the Current Sense Amplifier Gain (nominally 3.5 V/V), and the Channel Startup Offset is typically 0.40 V. The magnitude of the Ext_Ramp can be calculated from: SWNODE VFB (VOUT) Ext_Ramp  D  (VIN  VOUT)(RCSn  CCSn  fSW) For example, if VOUT at 0 A is set to 1.630 V with AVP and the input voltage is 12.0 V, the duty cycle (D) will be 1.630/12.0 or 13.6%. Int_Ramp will be 125 mV ⋅ 13.6/50 = 34 mV. Realistic values for RCSn, CCSn and fSW are 60 kΩ, 0.01 µF, and 220 kHz − using these and the previously mentioned formula, Ext_Ramp will be 10.6 mV. Internal Ramp CSA Out w/ Exaggerated Delays COMP−Offset VCOMP  1.630 V  0.40 V  34 mV  3.5 VV  10.6 mV2 CSA Out + Ramp + CSREF  2.083 Vdc. T1 T2 Figure 11. Open Loop Operation If the COMP pin is held steady and the inductor current changes, there must also be a change in the output voltage. http://onsemi.com 13 NCP5332A RCSn SWNODE n = 1 or 2 CSn + CSA Ln COn CCSn Internal Ramp RLn CSREF VOUT (VCORE) −+ “Fast−Feedback” Connection + VFB E.A. + DAC Out Channel Start−Up Offset To F/F Reset + PWM COMP COMP + Figure 12. Enhanced V2 Control Employing Lossless Inductive Current Sensing and Internal Ramp Inductive Current Sensing Current Sense Amplifier (CSA) input mismatch and the value of the current sense component will determine the accuracy of the current sharing between phases. The worst case Current Sense Amplifier input mismatch is ±5.0 mV and will typically be within 3.0 mV. The difference in peak currents between phases will be the CSA input mismatch divided by the current sense resistance. If all current sense components are of equal resistance a 3.0 mV mismatch with a 2.0 mΩ sense resistance will produce a 1.5 A difference in current between phases. For lossless sensing, current can be sensed across the inductor as shown in Figure 12. In the diagram, L is the output inductance and RL is the inherent inductor resistance. To compensate the current sense signal, the values of RCSn and CCSn are chosen so that L/RL = RCSn ⋅ CCSn. If this criteria is met, the current sense signal will be the same shape as the inductor current and the voltage signal at CSn will represent the instantaneous value of inductor current. Also, the circuit can be analyzed as if a sense resistor of value RL was used as a sense resistor (RS). When choosing or designing inductors for use with inductive sensing, tolerances and temperature effects should be considered. Cores with a low permeability material or a large gap will usually have minimal inductance change with temperature and load. Copper magnet wire has a temperature coefficient of 0.39% per °C. The increase in winding resistance at higher temperatures should be considered when setting the ILIM threshold. If a more accurate current sense is required than inductive sensing can provide, current can be sensed through a resistor as shown in Figure 10. External Ramp Size and Current Sensing The internal ramp allows flexibility of current sense time constant. Typically, the current sense RCSn ⋅ CCSn time constant (n = 1 or 2) should be equal to or slower than the inductor’s time constant. If RC is chosen to be smaller (faster) than L/RL, the AC or transient portion of the current sensing signal will be scaled larger than the DC portion. This will provide a larger steady state ramp, but circuit performance will be affected and must be evaluated carefully. The current signal will overshoot during transients and settle at the rate determined by RCSn ⋅ CCSn. It will eventually settle to the correct DC level, but the error will decay with the time constant of RCSn ⋅ CCSn. If this error is excessive it will effect transient response, adaptive positioning and current limit. During a positive current transient, the COMP pin will be required to undershoot in response to the current signal in order to maintain the output voltage. Similarly, the VDRP signal will overshoot which will produce too much transient droop in the output voltage. Single phase overcurrent will trip earlier than it would if compensated correctly and hiccup mode current limit will have a lower threshold for fast rise step loads than for slowly rising output currents. The waveforms in Figure 13 show a simulation of the current sense signal and the actual inductor current during a Current Sharing Accuracy Printed circuit board (PCB) traces that carry inductor current can be used as part of the current sense resistance depending on where the current sense signal is picked off. For accurate current sharing, the current sense inputs should sense the current at relatively the same point for each phase and the connection to the CSREF pin should be made so that no phase is favored. In some cases, especially with inductive sensing, resistance of the PCB can be useful for increasing the current sense resistance. The total current sense resistance used for calculations must include any PCB trace resistance between the CSn input and the CSREF input that carries inductor current. http://onsemi.com 14 NCP5332A Transient Response and Adaptive Positioning positive step in load current with values of L = 500 nH, RL = 1.6 mΩ, RCSn = 20 k and CCSn = 0.01 µF. For ideal current signal compensation the value of RCSn should be 31 kΩ. Due to the faster than ideal RC time constant there is an overshoot of 50% and the overshoot decays with a 200 µs time constant. With this compensation the ILIM pin threshold must be set more than 50% above the full load current to avoid triggering hiccup mode during a large output load step. For applications with fast transient currents the output filter is frequently sized larger than ripple currents require in order to reduce voltage excursions during load transients. Adaptive voltage positioning can reduce peak−to−peak output voltage deviations during load transients and allow for a smaller output filter. The output voltage can be set higher than nominal at light loads to reduce output voltage sag when the load current is applied. Similarly, the output voltage can be set lower than nominal during heavy loads to reduce overshoot when the load current is removed. For low current applications a droop resistor can provide fast accurate adaptive positioning. However, at high currents the loss in a droop resistor becomes excessive. For example; in a 50 A converter a 1 mΩ resistor to provide a 50 mV change in output voltage between no load and full load would dissipate 2.5 Watts. Lossless adaptive positioning is an alternative to using a droop resistor, but must respond to changes in load current. Figure 14 shows how adaptive positioning works. The waveform labeled normal shows a converter without adaptive positioning. On the left, the output voltage sags when the output current is stepped up and later overshoots when current is stepped back down. With fast (ideal) adaptive positioning the peak to peak excursions are cut in half. In the slow adaptive positioning waveform the output voltage is not repositioned quickly enough after current is stepped up and the upper limit is exceeded. Figure 13. Inductive Sensing Waveform During a Load Step with Fast RC Time Constant (50 µs/div) Current Limit Two levels of overcurrent protection are provided. First, if the voltage on the Current Sense pins (either CS1 or CS2) exceeds CSREF by more than a fixed threshold (Single Pulse Current Limit), the PWM comparator is turned off. This provides fast peak current protection for individual phases. Second, the individual phase currents are summed and low−pass filtered to compare an averaged current signal to a user adjustable voltage on the ILIM pin. If the ILIM voltage is exceeded, the fault latch trips and the Soft Start capacitor is discharged until the Soft−Start pin reaches 0.27 V. Then Soft Start begins. The converter will continue to operate in a low current hiccup mode until the fault condition is corrected. Normal Fast Adaptive Positioning Slow Adaptive Positioning Limits Figure 14. Adaptive Positioning The controller can be configured to adjust the output voltage based on the output current of the converter. (Refer to the application diagram in Figure 1). To set the no−load positioning, a resistor is placed between the output voltage and VFB pin. The VFB bias current will develop a voltage across the resistor to adjust the no−load output voltage. The VFB bias current is dependent on the value of ROSC as shown in the datasheet. During no load conditions the VDRP pin is at the same voltage as the VFB pin, so none of the VFB bias current flows through the VDRP resistor. When output current increases the VDRP pin increases proportionally and the VDRP pin current offsets the VFB bias current and causes the output voltage to decrease. The response during the first few microseconds of a load transient are controlled primarily by power stage output impedance and the ESR and ESL of the output filter. The Overvoltage Protection Overvoltage protection (OVP) is provided as a result of the normal operation of the Enhanced V2 control topology with synchronous rectifiers. The control loop responds to an overvoltage condition within 400 ns, causing the top MOSFET to shut OFF and the synchronous (lower) MOSFET to turn ON. This results in a “crowbar” action to clamp the output voltage and prevent damage to the load. The regulator will remain in this state until the overvoltage condition ceases or the input voltage is pulled low. http://onsemi.com 15 NCP5332A discharged below the Soft Start Discharge Threshold and then charged back up above the Channel Start Up Offset. The Soft Start pin will disable the converter when pulled below the maximum Soft Start Discharge Threshold (nominally 0.27 V). transition between fast and slow positioning is controlled by the total ramp size and the error amp compensation. If the current signal size is too large or the error amp too slow there will be a long transition to the final voltage after a transient. This will be most apparent with lower capacitance output filters. Power Good (PWRGD) The open−collector Power Good (PWRGD) pin is driven by a “window−comparator” monitoring VCORE. If VCORE is greater than −14% of the nominal VID setting and less than 2.0 V, this comparator will transition LOW causing PWRGD to go HIGH. If VCORE falls below 14% or rises above 2.0 V, the comparator will transition high and after a 120 µs delay, PWRGD will be pulled low. Error Amp Compensation & Tuning The transconductance error amplifier requires a capacitor (CCMP1 in the Applications Diagram) between the COMP pin and GND. This capacitor stabilizes the transconductance error amplifier. Values less than 1 nF may cause oscillations of the COMP voltage. These oscillations will increase the output voltage jitter. The capacitor (CAMP) between the COMP pin and the inverting error amplifier input (the VFB pin) and the parallel combination of the resistors RFBK1 and RDRP1 determine the bandwidth of the error amplifier. The gain of the error amplifier crosses 0 dB at a high enough frequency to give a quick transient response, but well below the switching frequency to minimize ripple and noise on the COMP pin. A capacitor in parallel with the VFB resistor (CFBK2) adds a zero to boost phase near the crossover frequency to improve loop stability. Setting−up and tuning the error amplifier is a three step process. First, the no−load and full−load adaptive voltage positioning (AVP) are set using RFBK1 and RDRP1, respectively. Second, the current sense time constant and error amplifier gain are adjusted with RCSn and CAMP while monitoring VOUT during transient loading. Lastly, the peak−to−peak voltage ripple on the COMP pin is examined when the converter is fully loaded to insure low output voltage jitter. The details of this process are covered in the Design Procedure section. Layout Guidelines With the fast rise, high output currents of microprocessor applications, parasitic inductance and resistance should be considered when laying out the power, filter and feedback signal sections of the board. Typically, a multi−layer board with at least one ground plane is recommended. If the layout is such that high currents can exist in the ground plane underneath the controller or control circuitry, the ground plane can be slotted to route the currents away from the controller. The slots should typically not be placed between the controller and the output voltage or in the return path of the gate drive. Additional power and ground planes or islands can be added as required for a particular layout. Gate drives experience high di/dt during switching and the inductance of gate drive traces should be minimized. Gate drive traces should be kept as short and wide as practical and should have a return path directly below the gate trace. Output filter components should be placed on wide planes connected directly to the load to minimize resistive drops during heavy loads and inductive drops and ringing during transients. If required, the planes for the output voltage and return can be interleaved to minimize inductance between the filter and load. The current sense signals are typically tens of milli−volts. Noise pick−up should be avoided wherever possible. Current feedback traces should be routed away from noisy areas such as the switch node and gate drive signals. If the current signals are taken from a location other than directly at the inductor any additional resistance between the pick−off point and the inductor appears as part of the inherent inductor resistances and should be considered in design calculations. The capacitors for the current feedback networks should be placed as close to the current sense pins as practical. After placing the NCP5332A control IC, follow these guidelines to optimize the layout and routing: 1. Place the 1 µF power supply bypass (ceramic) capacitors close to their associated pins: VCCL, VCCH1 (and/or VCCH2), VCCL1 (and/or VCCL2). 2. Place the MOSFETs to minimize the length of the Gate traces. Orient the MOSFETs such that the Drain connections are away from the controller and the Gate connections are closest to the controller. Undervoltage Lockout (UVLO) The controller has undervoltage lockout functions connected to two pins. One, intended for the logic and low−side drivers, with approximately a 4.2 V turn−on threshold is connected to the VCCL pin. A second, for the high side drivers, with approximately a 9.0 V threshold, is connected to the VCCH1 pin. The UVLO threshold for the high side drivers varies with the part type. In many applications this function will be disabled or will only check that the applicable supply is on − not that is at a high enough voltage to run the converter. See individual datasheets for more information on UVLO. Soft Start Enable, and Hiccup Mode A capacitor between the Soft Start pin and GND controls Soft Start and Hiccup mode slopes. A 0.1 µF capacitor with the 30 µA charge current will allow the output to ramp up at 0.3 V/ms or 1.6 V in 5.3 ms at start−up. When a fault is detected due to an overcurrent condition the converter will enter a low duty cycle hiccup mode. During hiccup mode the converter will not switch from the time a fault is detected until the Soft Start capacitor has http://onsemi.com 16 NCP5332A 3. Place the components associated with the internal error amplifier (RFBK1, CFBK2, CAMP, RCMP1, CCMP1, RDRP1) to minimize the trace lengths to the pins VFB, VDRP and COMP. 4. Place the current sense components (RCS1, RCS2, CCS1, CCS2, RCSREF, CCSREF) near the CS1, CS2, and CSREF pins. 5. Place the frequency setting resistor (ROSC) close to the ROSC pin. The ROSC pin is very sensitive to noise. Route noisy traces, such as the SWNODEs and GATE traces, away from the ROSC pin and resistor. 6. Place the Soft Start capacitor (CSS) near the Soft Start pin. 7. Place the MOSFETs and output inductors to reduce the size of the noisy SWNODEs. There is a trade−off between reducing the size of the SWNODEs for noise reduction and providing adequate heat−sinking for the synchronous MOSFETs. 8. Place the input inductor and input capacitor(s) near the Drain of the control (upper) MOSFETs. There is a trade−off between reducing the size of this node to save board area and providing adequate heat−sinking for the control MOSFETs. 9. Place the output capacitors (electrolytic and ceramic) close to the processor socket or output connector. 10. The trace from the SWNODEs to the current sense components (RCS1, RCS2) will be very noisy. Route this away from more sensitive, low−level traces. The Ground layer can be used to help isolate this trace. 11. The Gate traces are very noisy. Route these away from more sensitive, low−level traces. Keep each Gate signal on one layer and insure that there is an uninterrupted return path directly below the Gate trace. The Ground layer can be used to help isolate these traces. 12. Don’t “daisy chain” connections to Ground from one via. Allow each connection to Ground to have its own via as close to the component as possible. 13. Use a slot in the ground plane from the bulk output capacitors back to the input power connector to prevent high currents from flowing beneath the control IC. This slot should extend length−wise under the control IC and separate the connections to “signal ground” and “power ground.” Examples of signal ground include the capacitors at COMP, CSREF, Soft−Start (SS) and REF, the resistors at ROSC and ILIM, and the LGND pin to the controller. Examples of power ground include the capacitors to VCCH1 (and/or VCCH2) and VCCL1 (and/or VCCL2), the Source of the synchronous MOSFET, and the GND1 and GND2 pins of the controller. 14. The CSREF sense point should be equidistant between the output inductors to equalize the PCB resistance added to the current sense paths. This will insure acceptable current sharing. Also, route the CSREF connection away from noisy traces such as the SWNODEs and GATE traces. If noise from the SWNODEs or GATE signals capacitively couples to the CSREF trace the external ramps will be very noisy and voltage jitter will result. 15. Ideally, the SWNODEs are exactly the same shape and the current sense points (connections to RCS1 and RCS2) are made at identical locations to equalize the PCB resistance added to the current sense paths. This will help to insure acceptable current sharing. 16. Place the 0.1 µF ceramic capacitors, CQ1 and CQ2, close to the drains of the MOSFETs Q1 and Q2, respectively. Design Procedure 1. Output Capacitor Selection The output capacitors filter the current from the output inductor and provide a low impedance for transient load current changes. Typically, microprocessor applications will require both bulk (electrolytic, tantalum) and low impedance, high frequency (ceramic) types of capacitors. The bulk capacitors provide “hold up” during transient loading. The low impedance capacitors reduce steady−state ripple and bypass the bulk capacitance when the output current changes very quickly. The microprocessor manufacturers usually specify a minimum number of ceramic capacitors. The designer must determine the number of bulk capacitors. Choose the number of bulk output capacitors to meet the peak transient requirements. The formula below can be used to provide a starting point for the minimum number of bulk capacitors (NOUT,MIN): NOUT,MIN  ESR per capacitor 
IO,MAX
VO,MAX (1) In reality, both the ESR and ESL of the bulk capacitors determine the voltage change during a load transient according to:
VO,MAX  (
IO,MAX
t)  ESL 
IO,MAX  ESR (2) Unfortunately, capacitor manufacturers do not specify the ESL of their components and the inductance added by the PCB traces is highly dependent on the layout and routing. Therefore, it is necessary to start a design with slightly more than the minimum number of bulk capacitors and perform transient testing or careful modeling/simulation to determine the final number of bulk capacitors. 2. Output Inductor Selection The output inductor may be the most critical component in the converter because it will directly effect the choice of other components and dictate both the steady−state and http://onsemi.com 17 NCP5332A difficult for the converter to stay within the regulation limits when the load is removed than when it is applied − excessive overshoot may result. The output voltage ripple can be calculated using the output inductor value derived in this Section (LoMIN), the number of output capacitors (NOUT,MIN) and the per capacitor ESR determined in the previous Section: transient performance of the converter. When selecting an inductor the designer must consider factors such as DC current, peak current, output voltage ripple, core material, magnetic saturation, temperature, physical size, and cost (usually the primary concern). In general, the output inductance value should be as low and physically small as possible to provide the best transient response and minimum cost. If a large inductance value is used, the converter will not respond quickly to rapid changes in the load current. On the other hand, too low an inductance value will result in very large ripple currents in the power components (MOSFETs, capacitors, etc) resulting in increased dissipation and lower converter efficiency. Also, increased ripple currents will force the designer to use higher rated MOSFETs, oversize the thermal solution, and use more, higher rated input and output capacitors − the converter cost will be adversely effected. One method of calculating an output inductor value is to size the inductor to produce a specified maximum ripple current in the inductor. Lower ripple currents will result in less core and MOSFET losses and higher converter efficiency. Equation 3 may be used to calculate the minimum inductor value to produce a given maximum ripple current (α) per phase. The inductor value calculated by this equation is a minimum because values less than this will produce more ripple current than desired. Conversely, higher inductor values will result in less than the maximum ripple current. (VIN  VOUT)  VOUT LoMIN  (  IO,MAX  VIN  fSW) VOUT,P−P  (ESR per cap  NOUT,MIN)  (VIN  #Phases  VOUT)  D  (LoMIN  fSW) This formula assumes steady−state conditions with no more than one phase on at any time. The second term in Equation 4 is the total ripple current seen by the output capacitors. The total output ripple current is the “time summation” of the two individual phase currents that are 180 degrees out−of−phase. As the inductor current in one phase ramps upward, current in the other phase ramps downward and provides a canceling of currents during part of the switching cycle. Therefore, the total output ripple current and voltage are reduced in a multi−phase converter. 3. Input Capacitor Selection The choice and number of input capacitors is primarily determined by their voltage and ripple current ratings. The designer must choose capacitors that will support the worst case input voltage with adequate margin. To calculate the number of input capacitors one must first determine the total RMS input ripple current. To this end, begin by calculating the average input current to the converter: (3) IIN,AVG  IO,MAX  D α is the ripple current as a percentage of the maximum output current per phase (α = 0.15 for ±15%, α = 0.25 for ±25%, etc). If the minimum inductor value is used, the inductor current will swing ± α% about its value at the center (1/2 the DC output current for a two−phase converter). Therefore, for a two−phase converter, the inductor must be designed or selected such that it will not saturate with a peak current of (1 + α) ⋅ IO,MAX/2. The maximum inductor value is limited by the transient response of the converter. If the converter is to have a fast transient response then the inductor should be made as small as possible. If the inductor is too large its current will change too slowly, the output voltage will droop excessively, more bulk capacitors will be required, and the converter cost will be increased. For a given inductor value, its interesting to determine the times required to increase or decrease the current. For increasing current:
tINC  Lo 
IO(VIN  VOUT) (5) where: D is the duty cycle of the converter, D = VOUT/VIN. η is the specified minimum efficiency. IO,MAX is the maximum converter output current. The input capacitors will discharge when the control FET is ON and charge when the control FET is OFF as shown in Figure 15. IC,MAX ∆IC,IN = IC,MAX − IC,MIN IC,MIN 0A tON T/2 FET Off, Caps Charging −IIN,AVG FET On, Caps Discharging (3.1) For decreasing current:
tDEC  Lo 
IO(VOUT) (4) Figure 15. Input Capacitor Current for a Two−Phase Converter (3.2) For typical processor applications with output voltages less than half the input voltage, the current will be increased much more quickly than it can be decreased. It may be more The following equations will determine the maximum and minimum currents delivered by the input capacitors: http://onsemi.com 18 NCP5332A IC,MAX  ILo,MAX  IIN,AVG (6) IC,MIN  ILo,MIN  IIN,AVG (7) derating. The designer should be cognizant of the ESR of the input capacitors. The input capacitor power loss can be calculated from: ILo,MAX is the maximum output inductor current: PCIN  ICIN,RMS2  ESR_per_capacitorNIN (13) ILo,MAX  IO,MAX2 
ILo2 (8) Low ESR capacitors are recommended to minimize losses and reduce capacitor heating. The life of an electrolytic capacitor is reduced 50% for every 10°C rise in the capacitor’s temperature. ILo,MIN is the minimum output inductor current: ILo,MIN  IO,MAX2 
ILo2 (9) ∆ILo is the peak−to−peak ripple current in the output inductor of value Lo:
ILo  (VIN  VOUT)  D(Lo  fSW) 4. Input Inductor Selection The use of an inductor between the input capacitors and the power source will accomplish two objectives. First, it will isolate the voltage source and the system from the noise generated in the switching supply. Second, it will limit the inrush current into the input capacitors at power up. Large inrush currents will reduce the expected life of the input capacitors. The inductor’s limiting effect on the input current slew rate becomes increasingly beneficial during load transients. The worst case input current slew rate will occur during the first few PWM cycles immediately after a step−load change is applied as shown in Figure 16. When the load is applied, the output voltage is pulled down very quickly. Current through the output inductors will not change instantaneously so the initial transient load current must be conducted by the output capacitors. The output voltage will step downward depending on the magnitude of the output current (IO,MAX), the per capacitor ESR of the output capacitors (ESROUT), and the number of the output capacitors (NOUT) as shown in Figure 16. Assuming the load current is shared equally between the two phases, the output voltage at full, transient load will be: (10) For the two−phase converter, the input capacitor(s) RMS current is then: (11) ICIN,RMS  [2D  (IC,MIN2  IC,MIN 
IC,IN 
IC,IN23)  IIN,AVG2  (1  2D)]12 Select the number of input capacitors (NIN) to provide the RMS input current (ICIN,RMS) based on the RMS ripple current rating per capacitor (IRMS,RATED): NIN  ICIN,RMSIRMS,RATED (12) For a two−phase converter with perfect efficiency (η = 1), the worst case input ripple−current will occur when the converter is operating at a 25% duty cycle. At this operating point, the parallel combination of input capacitors must support an RMS ripple current equal to 25% of the converter’s DC output current. At other duty cycles, the ripple−current will be less. For example, at a duty cycle of either 10% or 40%, the two−phase input ripple−current will be approximately 20% of the converter’s DC output current. In general, capacitor manufacturers require derating to the specified ripple−current based on the ambient temperature. More capacitors will be required because of the current VOUT,FULL−LOAD  VOUT,NO−LOAD  (IO,MAX2)  ESROUTNOUT VOUT MAX dI/dt occurs in first few PWM cycles. ILi Vi(t = 0) = 12 V Q1 (14) SWNODE ILo Vo(t = 0) = 1.630 V Lo 700 nH Li TBD Ci 3 × 16SP270 + VCi + Co 7 × 16MBZ1500M10X20 Q2 + Vi − 12 V ESRCi 18 m/3 = 6.0 m 22.5 u(t) ESRCo 13 m/7 = 1.9 m Figure 16. Calculating the Input Inductance http://onsemi.com 19 NCP5332A Once the dissipation is known, the heat sink thermal impedance can be calculated to prevent the specified maximum case or junction temperatures from being exceeded at the highest ambient temperature. Power dissipation has two primary contributors: conduction losses and switching losses. The control or upper MOSFET will display both switching and conduction losses. The synchronous or lower MOSFET will exhibit only conduction losses because it switches into nearly zero voltage. However, the body diode in the synchronous MOSFET will suffer diode losses during the non−overlap time of the gate drivers. For the upper or control MOSFET, the power dissipation can be approximated from: When the control MOSFET (Q1 in Figure 16) turns ON, the input voltage will be applied to the opposite terminal of the output inductor (the SWNODE). At that instant, the voltage across the output inductor can be calculated as:
VLo  VIN  VOUT,FULL−LOAD (15)  VIN  VOUT,NO−LOAD  (IO,MAX2)  ESROUTNOUT The differential voltage across the output inductor will cause its current to increase linearly with time. The slew rate of this current can be calculated from: dILodt 
VLoLo (16) PD,CONTROL  (IRMS,CNTL2  RDS(on)) Current changes slowly in the input inductor so the input capacitors must initially deliver the vast majority of the input current. The amount of voltage drop across the input capacitors (∆VCi) is determined by the number of input capacitors (NIN), their per capacitor ESR (ESRIN), and the current in the output inductor according to: (19)  (ILo,MAX  QswitchIg  VIN  fSW)  (Qoss2  VIN  fSW)  (VIN  QRR  fSW) Before the load is applied, the voltage across the input inductor (VLi) is very small − the input capacitors charge to the input voltage, VIN. After the load is applied the voltage drop across the input capacitors, ∆VCi, appears across the input inductor as well. Knowing this, the minimum value of the input inductor can be calculated from: The first term represents the conduction or IR losses when the MOSFET is ON while the second term represents the switching losses. The third term is the losses associated with the control and synchronous MOSFET output charge when the control MOSFET turns ON. The output losses are caused by both the control and synchronous MOSFET but are dissipated only in the control FET. The fourth term is the loss due to the reverse recovery time of the body diode in the synchronous MOSFET. The first two terms are usually adequate to predict the majority of the losses. Where IRMS,CNTL is the RMS value of the trapezoidal current in the control MOSFET: LiMIN  VLi  dIINdtMAX IRMS,CNTL  [D  (ILo,MAX2  ILo,MAX  ILo,MIN (20)
VCi  ESRINNIN  dILodt  tON (17)  ESRINNIN  dILodt  DfSW (18) 
VCi  dIINdtMAX  ILo,MIN2)3]12 dIIN/dt MAX is the maximum allowable input current slew rate. The input inductance value calculated from Equation 18 is relatively conservative. It assumes the supply voltage is very “stiff” and does not account for any parasitic elements that will limit dI/dt such as stray inductance. Also, the ESR values of the capacitors specified by the manufacturer’s data sheets are worst case high limits. In reality input voltage “sag,” lower capacitor ESRs, and stray inductance will help reduce the slew rate of the input current. As with the output inductor, the input inductor must support the maximum current without saturating the magnetic. Also, for an inexpensive iron powder core, such as the −26 or −52 from Micrometals, the inductance “swing” with DC bias must be taken into account − inductance will decrease as the DC input current increases. At the maximum input current, the inductance must not decrease below the minimum value or the dI/dt will be higher than expected. ILo,MAX is the maximum output inductor current: ILo,MAX  IO,MAX2 
ILo2 (21) ILo,MIN is the minimum output inductor current: ILo,MIN  IO,MAX2 
ILo2 (22) IO,MAX is the maximum converter output current. D is the duty cycle of the converter: D  VOUTVIN (23) ∆ILo is the peak−to−peak ripple current in the output inductor of value Lo:
ILo  (VIN  VOUT)  D(Lo  fSW) (24) RDS(on) is the ON resistance of the MOSFET at the applied gate drive voltage. Qswitch is the post gate threshold portion of the gate−to−source charge plus the gate−to−drain charge. This may be specified in the data sheet or approximated from the gate−charge curve as shown in the Figure 17. 5. MOSFET & Heatsink Selection Power dissipation, package size, and thermal solution drive MOSFET selection. To adequately size the heat sink, the design must first predict the MOSFET power dissipation. Qswitch  Qgs2  Qgd http://onsemi.com 20 (25) NCP5332A θSA is the sink−to−ambient thermal impedance of the heatsink assuming direct mounting of the MOSFET (no thermal “pad” is used). TJ is the specified maximum allowed junction temperature. TA is the worst case ambient operating temperature. For TO−220 and TO−263 packages, standard FR−4 copper clad circuit boards will have approximate thermal resistances (θSA) as shown below: ID VGATE VGS_TH QGS1 QGS2 QGD VDRAIN Figure 17. MOSFET Switching Characteristics Ig is the output current from the gate driver IC. VIN is the input voltage to the converter. fsw is the switching frequency of the converter. QG is the MOSFET total gate charge to obtain RDS(on). Commonly specified in the data sheet. Vg is the gate drive voltage. QRR is the reverse recovery charge of the lower MOSFET. Qoss is the MOSFET output charge specified in the data sheet. For the lower or synchronous MOSFET, the power dissipation can be approximated from: PD,SYNCH  (IRMS,SYNCH2  RDS(on))  (Vfdiode  IO,MAX2  t_nonoverlap  fSW) Single−Sided 1 oz. Copper 0.5/323 60−65°C/W 0.75/484 55−60°C/W 1.0/645 50−55°C/W 1.5/968 45−50°C/W 2.0/1290 38−42°C/W 2.5/1612 33−37°C/W As with any power design, proper laboratory testing should be performed to insure the design will dissipate the required power under worst case operating conditions. Variables considered during testing should include maximum ambient temperature, minimum airflow, maximum input voltage, maximum loading, and component variations (i.e. worst case MOSFET RDS(on)). Also, the inductors and capacitors share the MOSFET’s heatsinks and will add heat and raise the temperature of the circuit board and MOSFET. For any new design, its advisable to have as much heatsink area as possible – all too often new designs are found to be too hot and require re−design to add heatsinking. (26) The first term represents the conduction or IR losses when the MOSFET is ON and the second term represents the diode losses that occur during the gate non−overlap time. All terms were defined in the previous discussion for the control MOSFET with the exception of: 6. Adaptive Voltage Positioning There are two resistors that determine the Adaptive Voltage Positioning: RVFBK and RDRP. RVFBK establishes the no−load “high” voltage position and RDRP determines the full−load “droop” voltage. Resistor RVFBK is connected between VCORE and the VFB pin of the controller. At no load, this resistor will conduct the internal bias current of the VFB pin and develop a voltage drop from VCORE to the VFB pin. Because the error amplifier regulates VFB to the DAC setting, the output voltage, VCORE, will be lower by the amount IBIASVFB ⋅ RVFBK. This condition is shown in Figure 18. To calculate RVFBK the designer must specify the no−load voltage decrease below the VID setting (∆VNO−LOAD) and determine the VFB bias current. Usually, the no−load voltage decrease is specified in the design guide for the processor that is available from the manufacturer. It is a voltage that, under load transient condition, will be the maximum acceptable for the VID code setting. The VFB bias current is determined by the value of the resistor from ROSC to ground (see Figure 5 in the data sheet for a graph of IBIASVFB versus ROSC). The value of RVFBK can then be calculated: (27) IRMS,SYNCH  [(1  D)  (ILo,MAX2  ILo,MAX  ILo,MIN  ILo,MIN2)3]12 where: Vfdiode is the forward voltage of the MOSFET’s intrinsic diode at the converter output current. t_nonoverlap is the non−overlap time between the upper and lower gate drivers to prevent cross conduction. This time is usually specified in the data sheet for the control IC. When the MOSFET power dissipations are known, the designer can calculate the required thermal impedance to maintain a specified junction temperature at the worst case ambient operating temperature T  (TJ  TA)PD Pad Size (in2/mm2) (28) where; θT is the total thermal impedance (θJC + θSA). θJC is the junction−to−case thermal impedance of the MOSFET. http://onsemi.com 21 NCP5332A L1 0A CS1 CCS1 RCS2 L2 0A CS2 CCS2 +− + − GVDRP COMP Σ − + RCS1 Error Amp VID Setting IBIASVFB RDRP + − GVDRP VDRP = VID RVFBK VFB = VID IDRP = 0 CSREF VCORE IFBK = IBIASVFB VCORE = VID − IBIASVFB
RVFBk Figure 18. AVP Circuitry at No−Load (29) (RL), the PCB trace resistance between the current sense points (RPCB), and the controller IC’s gain from the current sense to the VDRP pin (GVDRP): Resistor RDRP is connected between the VDRP and the VFB pins. At no−load, the VDRP and the VFB pins will both be at the DAC voltage so this resistor will conduct zero current. However, at full−load, the voltage at the VDRP pin will increase proportional to the output inductor’s current while VFB will still be regulated to the DAC voltage. Current will be conducted from VDRP to VFB by RDRP. This current will be large enough to supply the VFB bias current and cause a voltage drop from VFB to Vcore across RVFBK – the converter’s output voltage will be reduced. This condition is shown in Figure 19. To determine the value of RDRP the designer must specify the full−load voltage reduction from the VID (DAC) setting (∆VOUT,FULL−LOAD) and predict the voltage increase at the VDRP pin at full−load. Usually, the full−load voltage reduction is specified in the design guide for the processor that is available from the manufacturer. To predict the voltage increase at the VDRP pin at full−load (∆VDRP), the designer must consider the output inductor’s resistance RCS1 L1 IMAX/2 RDRP  CS2
VDRP (
VOUT,FULL−LOADRVFBK  IBIASVFB) 7. Current Sensing For inductive current sensing, choose the current sense network (RCSn, CCSn, n = 1 or 2) to satisfy RCSn  CCSn  Lo(RL  RPCB) COMP Σ Error Amp VID Setting IBIASVFB RDRP + − GVDRP (31) ∆VOUT,FULL−LOAD is the full−load voltage reduction from the VID (DAC) setting. ∆VOUT,FULL−LOAD is not the voltage change from the no−load AVP setting. +− + − GVDRP (30) The value of RDRP can then be calculated: CCS1 RCS2 L2 IMAX/2 CS1
VDRP  IO,MAX  (RL  RPCB)  GVDRP − + RVFBK 
VNO−LOADIBIASVFB RVFBK VDRP = VID + VFB = VID IMAX • RL • GVDRP VCORE CCS2 IDRP IFBK IDRP = IMAX • RL • GVDRP/RDRP IFBK = IDRP + IBIASVFB CSREF VCORE = VID − (IDRP + IBIASVFB)
RVFBK = VID − IMAX
RL
GVDRP
RVFBK/RDRP − IBIASVFB
RVFBK Figure 19. AVP Circuitry at Full−Load http://onsemi.com 22 (32) NCP5332A For resistive current sensing, choose the current sense network (RCSn, CCSn, n = 1 or 2) to satisfy RCSn  CCSn  Lo(Rsense) (33) This will provide an adequate starting point for RCSn and CCSn. After the converter is constructed, the value of RCSn (and/or CCSn) should be fine−tuned in the lab by observing the VDRP signal during a step change in load current. The RCSn ⋅ CCSn network should be tuned to provide a “square−wave” at the VDRP output pin with maximum rise time and minimal overshoot as shown in Figure 22. Equation 32 will be most accurate for better iron powder core material (such as the −8 from Micrometals). This material is very consistent with DC current and frequency. Less expensive core materials (such as the −52 from Micrometals) change their characteristics with DC current, AC flux density, and frequency. This material will yield acceptable converter performance if the current sense time constant is set lower (longer) than anticipated. As a rule of thumb, use approximately twice the resistance (RCSn) or twice the capacitance (CCSn) when using the less expensive core material. Figure 20. VDRP Tuning Waveforms. The RC Time Constant of the Current Sense Network Is Too Long (Slow): VDRP and VOUT Respond Too Slowly. 8. Error Amplifier Tuning After the steady−state (static) AVP has been set and the current sense network has been optimized the Error Amplifier must be tuned. Basically, the gain of the Error Amplifier should be adjusted to provide an acceptable transient response by increasing or decreasing the Error Amplifier’s feedback capacitor (CAMP in the Applications Diagram). The bandwidth of the control loop will vary directly with the gain of the error amplifier. Figure 21. VDRP Tuning Waveforms. The RC Time Constant of the Current Sense Network Is Too Short (Fast): VDRP and VOUT Both Overshoot. Figure 23. The Value of CAMP Is Too High and the Loop Gain/Bandwidth Too Low. COMP Slews Too Slowly Which Results in Overshoot in VOUT. Figure 22. VDRP Tuning Waveforms. The RC Time Constant of the Current Sense Network Is Optimal: VDRP and VOUT Respond to the Load Current Quickly Without Overshooting. If CAMP is too large the loop gain/bandwidth will be low, the COMP pin will slew too slowly, and the output voltage will overshoot as shown in Figure 23. On the other hand, if CAMP is too small the loop gain/bandwidth will be high, the COMP pin will slew very quickly and overshoot. Integrator http://onsemi.com 23 NCP5332A “wind up” is the cause of the overshoot. In this case the output voltage will transition more slowly because COMP spikes upward as shown in Figure 24. Too much loop gain/bandwidth increase the risk of instability. In general, one should use the lowest loop gain/bandwidth as possible to achieve acceptable transient response − this will insure good stability. If CAMP is optimal the COMP pin will slew quickly but not overshoot and the output voltage will monotonically settle as shown in Figure 25. After the control loop is tuned to provide an acceptable transient response the steady−state voltage ripple on the COMP pin should be examined. When the converter is operating at full, steady−state load, the peak−to−peak voltage ripple on the COMP pin should be less than 20 mVPP as shown in Figure 26. Less than 10 mVPP is ideal. Excessive ripple on the COMP pin will contribute to output voltage jitter. Figure 26. At Full−Load (28 A) the Peak−to−Peak Voltage Ripple on the COMP Pin Should Be Less than 20 mV for a Well−Tuned/Stable Controller. Higher COMP Voltage Ripple Will Contribute to Output Voltage Jitter. 9. Current Limit Setting When the output of the current sense amplifier (CO1 or CO2 in the block diagram) exceeds the voltage on the ILIM pin the part will enter hiccup mode. For inductive sensing, the ILIM pin voltage should be set based on the inductor’s maximum resistance (RLMAX). The design must consider the inductor’s resistance increase due to current heating and ambient temperature rise. Also, depending on the current sense points, the circuit board may add additional resistance. In general, the temperature coefficient of copper is +0.393% per °C. If using a current sense resistor (RSENSE), the ILIM pin voltage should be set based on the maximum value of the sense resistor. To set the level of the ILIM pin: Figure 24. The Value of CAMP Is Too Low and the Loop Gain/Bandwidth Too High. COMP Moves Too Quickly, Which Is Evident from the Small Spike in Its Voltage When the Load Is Applied or Removed. The Output Voltage Transitions More Slowly Because of the COMP Spike. VILIM  (IOUT,LIM 
ILo2)  R  GILIM (34) where: IOUT,LIM is the current limit threshold of the converter; ∆ILo/2 is half the inductor ripple current; R is either (RLMAX + RPCB) or RSENSE; GILIM is the current sense to ILIM gain. For the overcurrent protection to work properly, the current sense time constant (RC) should be slightly larger than the RL time constant. If the RC time constant is too fast, during step load changes the sensed current waveform will appear larger than the actual inductor current and will probably trip the current limit at a lower level than expected. 10. PWM Comparator Input Voltage The voltage at the positive input terminal of the PWM comparator (see Figure 10 or 12) is limited by the internal voltage supply of the controller (3.3 V), the size of the internal ramp, and the magnitude of the channel startup offset voltage. To prevent the PWM comparator from saturating, the differential input voltage from CSREF to CSn (n = 1 or 2) must satisfy the following equation: Figure 25. The Value of CAMP Is Optimal. COMP Slews Quickly Without Spiking or Ringing. VOUT Does Not Overshoot and Monotonically Settles to Its Final Value. http://onsemi.com 24 NCP5332A VCSREF,MAX  VCOn,MAX  310 mV  D  2.45 V NOUT,MIN  ESR per capacitor  (35)
IO,MAX
VO,MAX (1)  13 m  45 A(1.630 V  1.540 V) where:  6.5 or 7 capacitors minimum (10, 500 F) VCSREF,MAX  Max VID Setting w AVP @ Full Load VCOn,MAX  [VCSn  VCSREF]  GCSA,MAX  (IO,MAX2 
ILo2)  RMAX  GCSA,MAX 2. Output Inductor Selection Calculate the minimum output inductance at IO,MAX according to Equation 4 with ±20% inductor ripple current (α = 0.20): RMAX  RSENSE or (RL,MAX  RPCB,MAX) LoMIN  11. Soft Start Time  If the Soft Start time is defined from the instant the Soft Start pin is released (i.e. the converter is enabled) to when the output reaches the VID setting with AVP then the Soft Start time (tSS) can be calculated from: TSS  VCOMP  CSSISS (VIN  VOUT)  VOUT (  IO,MAX  VIN  fSW) (3) (12 V  1.565 V)  1.565 V (0.2  45 A  12 V  220 kHz)  687 nH To save cost, we choose the inexpensive T50−52B core from Micrometals: 43.5 nH/N2, 3.19 cm/turn. According to the Micrometals catalog, at 22.5 A (per phase) the permeability of this core will be approximately 70% of the permeability at 0 A. Therefore, at 0 A we must achieve at least 687 nH/0.7 or 981 nH. Using five turns of #16AWG bifilar (2 mΩ/ft) will produce 1.1 µH. Use Equation 4 to insure the output voltage ripple will satisfy the design goal with the minimum number of capacitors and the nominal output inductance: (36) where: VCOMP  VOUT @ 0 A  Channel_Startup_Offset  Int_Ramp  GCSA  Ext_Ramp2 CSS is the capacitor from the Soft−Start pin to LGND; Ext_Ramp = D ⋅ (VIN − VOUT) / (RCSn ⋅ CCSn ⋅ fSW); ISS is the Soft−Start charge current from the data sheet. VOUT,P−P  (ESR per cap  NOUT,MIN)  (VIN  #Phases  VOUT)  D  (LoMIN  fSW) Design Example (4)  (13 m7)  (12 V  2  1.6 V)  (1.6 V12 V)(1.1 H  220 kHz) Typical Design Requirements: VIN = 12.0 Vdc VOUT = 1.60Vdc (nominal) VOUT,RIPPLE < 10 mVPP max VID Range: 1.100 Vdc − 1.850 Vdc IO,MAX = 45 A at full−load IOUT,LIM = 52 A min at 55°C (shutdown threshold) dIIN/dt = 0.50 A/µs max fSW = 220 kHz η = 81% min at full−load TA,MAX = 60°C TJ,MAX = 125°C tSS < 10.0 ms (Soft Start time) ∆VOUT at no−load (static) = −30 mV from VID setting = 1.630 Vdc ∆VOUT at full−load (static) = –65 mV from VID setting = 1.565 Vdc ∆VOUT at full−load (transient) = −95 mV from VID setting = 1.540 Vdc  (1.86 m)  {2.38 A}  9.0 mV The output voltage ripple will be decreased when output capacitors are added to satisfy transient loading requirements. We will need the nominal and worst case inductor resistances for subsequent calculations: RL  5 turns  3.19 cmturn  0.03218 ftcm  2 mft  1.03 m The inductor resistance will be maximized when the inductor is “hot” due to the load current and the ambient temperature is high. Assuming a 40°C temperature rise of the inductor at full−load and a 35°C ambient temperature rise we can calculate: RL,MAX  1.03 m  [1  0.39%°C  (40°C  35°C)] 1. Output Capacitor Selection  1.33 m First, choose a low−cost, low−ESR output capacitor such as the Rubycon 16MBZ1500M10X20: 16 V, 1500 µF, 2.55 ARMS, 13 mΩ, 10 × 20mm. Calculate the minimum number of output capacitors: The output inductance at full−load will be: Lo  0.70
1.1 H  770 nH http://onsemi.com 25 NCP5332A 3. Input Capacitor Selection Use Equation 5 to determine the average input current to the converter at full−load; IIN,AVG  IO,MAX  D (5)  45 A  (1.565 V12 V)0.81  7.25 A Next, use Equations 6 to 10 with the full−load inductance value of 770 nH:
ILo  (VIN  VOUT)  D(Lo  fSW)  (12 V  1.565 V)  (1.565 V12 V) (770 nH  220 kHz) (10)  8.03 App ILo,MAX  IO,MAX2 
ILo2 Figure 27. Actual DC/DC Converter Circuitry With the Calculated Input Inductor and Minimum Filtering Components. The Measured Slew−Rate (dIIN/dt) of the Input Current (0.064 A/
s) Is Much Lower Than Expected (0.1 A/
s) Because of Input Voltage Drop, Parasitic Inductance, and Lower Real ESRs Than Specified in the Capacitors’ Data Sheets. (8)  45 A2  8.03 App2  26.5 A ILo,MIN  IO,MAX2 
ILo2  45 A2  8.03 App2  18.5 A IC,MAX  ILo,MAX  IIN,AVG (9) (6) First, use Equation 15 to calculate the voltage across the output inductor due to the 45 A load current being shared equally between the two phases:  26.5 A0.81  7.25 A  25.5 A IC,MIN  ILo,MIN  IIN,AVG (7)
VLo  VIN  VOUT,NO−LOAD  18.5 A0.81  7.25 A  15.6 A (15)  (IO,MAX2)  ESROUTNOUT  12 V  1.85 V  45 A2  13 m7 For the two−phase converter, the input capacitor(s) RMS current at full−load is then (Note: D = 1.565 V/12 V = 0.13):  10.19 V (11) ICIN,RMS  [2D  (IC,MIN2  IC,MIN 
IC,IN Second, use Equation 16 to determine the rate of current increase in the output inductor when the load is first applied (i.e. Lo has not changed much due to the DC current): 
IC,IN23)  IIN,AVG2  (1  2D)]12 dILodt 
VLoLo  [0.26  (15.62  15.6  8.00  8.0023) (16)  10.19 V1.1 H  9.26 Vs  7.252  (1  0.26)]12 Finally, use Equations 17 and 18 to calculate the minimum input inductance value:  11.8 ARMS At this point, the designer must decide between saving board space by using higher−rated/more costly capacitors or saving cost by using more lower−rated/less costly capacitors. To save board space, we choose the SP (Oscon) series capacitors by Sanyo. Part number 16SP270: 270 µF, 16 V, 4.4 ARMS, 18 mΩ, 10 × 10.5 mm. This design will require 11.8 A/4.4 A = 2.7 or NIN = 3 capacitors on the input for a conservative design.
VCi  ESRINNIN  dILodt  DfSW (17)  18 m3  9.26 Vs  0.157220 kHz  39.7 mV LiMIN 
VCi  dIINdtMAX (18)  39.7 mV0.50 As  80 nH Next, choose the small, cost effective T30−26 core from Micrometals (33.5 nH/N2) with #16 AWG. The design requires only 1.54 turns to achieve the minimum inductance value. Allow for inductance “swing” at full−load by using three turns. The input inductor’s value will be: 4. Input Inductor Selection The input inductor must limit the input current slew rate to less than 0.5 A/µs during a load transient from 0 to 45 A. A conservative value will be calculated assuming the minimum number of output capacitors (NOUT = 7), three input capacitors (NIN = 3), worst case ESR values for both the input and output capacitors, and a maximum duty cycle (D = (1.850 V + 30 mVAVP)/12.0 VIN = 0.157). Li  32  33.5 nHN2  301 nH This inductor is available as part number CTX15−14771 from Coiltronics. http://onsemi.com 26 NCP5332A 5. MOSFET & Heatsink Selection PD,SYNCH  (IRMS,SYNCH2  RDS(on)) The NTB85N03T1 from ON Semiconductor is chosen for both the control and synchronous MOSFET due to its low RDS(on) and low gate−charge requirements. The following parameters are derived from the NTB85N03T1 data sheet: RdsON = 3.9 mΩ @ 10 V QSWITCH = 25 nC QRR = 45 nC QOSS = 35 nC Vfdiode = 0.86 V @ 25 A θJC = 1.0°C/W NCP5332A Parameters: iG = 1.5 A VG = 10 V t_nonoverlap = 65 ns  (Vfdiode  IO,MAX2  t_nonoverlap  fSW)  (21.12 ARMS  3.9 m)  (0.86 V  45 A2  65 ns  220 kHz)  1.74 W  0.28 W  2.02 W Equation 28 is used to calculate the heat sink thermal impedances necessary to maintain less than the specified maximum junction temperatures at 60°C ambient: CNTL  (125  60°C)1.6 W  1.0°CW  40°CW SYNCH  (125  60°C)2.02 W  1.0°CW  31°CW If board area permits, a cost effective heatsink could be formed by using a TO−263 mounting pad of at least 1.5 in2 for the upper MOSFET and 2.5 in2 for the lower MOSFET on a single−sided, 1 oz. copper PCB. The total required pad area would be slightly less if the area were divided evenly between top and bottom layers with multiple thermal vias joining the two areas. To conserve board space, AAVID offers clip−on heatsinks for TO−220 thru−hole packages. Examples of these heatsinks include #577002 (1″ × 0.75″ × 0.25″, 33°C/W at 2 W) and #591302 (0.75″ ×0.5″ × 0.5″, 29°C/W at 2 W). The RMS value of the current in the control MOSFET is calculated from Equation 20 and the previously derived values for D, ILMAX, and ILMIN at the converter’s maximum output current: (20) IRMS,CNTL  [D(ILo,MAX2  ILo,MAX  ILo,MIN  ILo,MIN2)3]12  0.36  [(26.52  26.5  18.5  18.52)3]12  8.15 ARMS 6. Adaptive Voltage Positioning Equation 19 is used to calculate the power dissipation of the control MOSFET: PD,CONTROL  (IRMS,CNTL2  RDS(on)) (26) First, to achieve the 220 kHz switching frequency, use Figure 4 to determine that a 65 kΩ resistor is needed for ROSC. Then, use Figure 5 to find the VFB bias current at the corresponding value of ROSC. In this example, the 65 kΩ ROSC resistor results in a VFB bias current of approximately 15 µA. Knowing the VFB bias current, one can calculate the required values for RFBK1 and RDRP using Equations 29 through 31. The no−load position is easily set using Equation 29: (19)  (ILo,MAX  QswitchIg  VIN  fSW)  (Qoss2  VIN  fSW)  (VIN  QRR  fSW)  (8.152 ARMS  3.9 m)  (26.5 A  25 nC1.5 A  12 V  220 kHz)  (35 nC2  12 V  220 kHz) RVFBK 
VNO−LOADIBIASVFB  (12 V  45 nC  220 kHz) (29)  +30 mV15 A  0.26 W  1.17 W  0.05 W  0.12 W  2.0 k  1.60 W For inductive current sensing, the designer must calculate the inductor’s resistance (RL) and approximate any resistance added by the circuit board (RPCB). We found the inductor’s nominal resistance in Section 2 (0.82 mΩ). In this example, we approximate 0.50 mΩ for the circuit board resistance (RPCB). With this information, Equation 30 can be used to calculate the increase at the VDRP pin at full load: The RMS value of the current in the synchronous MOSFET is calculated from Equation 27 and the previously derived values for D, ILo,MAX, and ILo,MIN at the converter’s maximum output current: (27) IRMS,SYNCH  [(1  D)  (ILo,MAX2  ILo,MAX  ILo,MIN  ILo,MIN2)3]12
VDRP  IO,MAX  (RL  RPCB)  GVDRP  [(1  0.13)  (26.52  26.5  18.5  18.52)3]12  45 A  (1.03 m  0.50 m)  3.3 VV  21.1 ARMS  227 mV Equation 26 is used to calculate the power dissipation of the synchronous MOSFET: RDRP can then be calculated from Equation 31: http://onsemi.com 27 (30) NCP5332A RDRP  (31)
VDRP (
VOUT,FULL−LOADRVFBK  IBIASVFB) 9. Current Limit Setting The maximum inductor resistance, the maximum PCB resistance, and the maximum current−sense gain as shown in Equation 34 determine the current limit. The maximum current, IOUT,LIM, was specified in the design requirements. The maximum inductor resistance occurs at full−load and the highest ambient temperature. This value was found in the “Output Inductor Selection” (1.33 mΩ). This analysis assumes the PCB resistance only increases due to the change in ambient temperature. Component heating will also increase the PCB temperature but quantifying this effect is difficult. Lab testing should be used to “fine tune” the overcurrent threshold.  227 mV(95 mV2.0 k  15 A)  6.98 k 7. Current Sensing Choose the current sense network (RCSn, CCSn, n = 1 or 2) to satisfy: RCSn  CCSn  Lo(RL  RPCB) (32) Equation 32 will be most accurate for better iron powder core material (such as the −8 from Micrometals). This material is very consistent with DC current and frequency. Less expensive core materials (such as the −52 from Micrometals) change their characteristics with DC current, AC flux density, and frequency. This material will yield acceptable converter performance if the current sense time constant is set lower (longer) than anticipated. As a rule of thumb, use approximately twice the resistance (RCSn) or twice the capacitance (CCSn) when using the less expensive core material. The component values determined thus far are Lo = 1.1 µH, RL = 1.03 mΩ, and RPCB = 0.50mΩ. We choose a convenient value for CCS1 (0.01 µF) and solve for RCS1; RPCB,MAX  0.50 m  (1  0.39%°C  (60  25)°C)  0.57 m VILIM  (IOUT,LIM 
ILo2)  (RLMAX  RPCB,MAX)  GILIM  GCSA  (52 A  8.03 A2)  (1.33 m  0.57 m)  1.93 VV  3.50 VV  0.718 Vdc Set the voltage at the ILIM pin using a resistor divider from the 3.3 V reference output as shown in Figure 28. If the resistor from ILIM to GND is chosen as 1 k (RLIM2), the resistor from ILIM to 3.3 V can be calculated from: RCSn  1.1 H(1.03 m  0.50 m)0.01 F  71 k Equation 32 will be most accurate for higher quality iron powder core materials such as the −2 or −8 from Micrometals. The permeability of these more expensive cores is relatively constant versus DC current, AC flux density and frequency. Less expensive core materials (such as the −52 from Micrometals) change their characteristics versus DC current, AC flux density, and frequency. The less expensive materials may yield acceptable converter performance if the current sense time constant is set approximately 1×−2× longer than anticipated. For example, use up to twice the resistance (RCSn) or twice the capacitance (CCSn) when using the less expensive core material. If we use −52 material for this design, the value of RCSn may need to be increased to 2 × 71 kΩ or 142 kΩ. After the circuit is constructed, the values of RCSn and/or CCSn should be tuned to provide a “square−wave” at VDRP with minimal overshoot and fast rise time due to a step change in load current as shown in Figures 20−22. RLIM1  (VREF  VILIM)(VILIMRLIM2)  (3.3 V  0.718 V)(0.718 V1 k)  3596  or 3.57 k 3.3 VREF RLIM1 VLIM To ILIM Pin RLIM2 1k Figure 28. Setting the Current Limit 10. PWM Comparator Input Voltage Use Equation 35 to check the voltage level to the positive pin of the internal PWM comparators. The design should not saturate the PWM comparator at maximum DAC output voltage (+1% error), AVP at full−load, 100% duty cycle (D = 1), and worst−case maximum internal ramp (310 mV at 100% duty cycle): 8. Error Amplifier Tuning The error amplifier is tuned by adjusting CAMP to provide an acceptable full−load transient response as shown in Figures 23−25. After a value for CAMP is chosen, the peak−to−peak voltage ripple on the COMP pin is examined under full−load to insure less than 20 mVPP as shown in Figure 26. VCSREF,MAX  Max VID Setting w AVP @ Full−Load  1.01  1.850 V  30 mV  1.834 V http://onsemi.com 28 NCP5332A Then calculate the steady−state COMP voltage: VCOn,MAX  (IO,MAX2 
ILo2)  RMAX  GCSA,MAX VCOMP  VOUT @ 0 A  Channel_Startup_Offset  (52 A2  8.03 A2)  (1.33 m  0.57 m)  Int_Ramp  GCSA  Ext_Ramp2  3.90 VV  1.630 V  0.40 V  0.135  250 mV  0.222 V  3.5 VV  11 mV2 VCSREF,MAX  VCOn,MAX  310 mV  D  2.083 V (35)  1.834 V  0.222 V  310 mV Then choose a convenient value for the Soft−Start time (7.5 ms) and solve Equation 37 for the Soft−Start capacitor, CSS:  2.366 V This value is acceptable because it below the specified maximum of 2.45 V. CSS  tSS  ISSVCOMP  7.5 ms  30 A2.083 V 11. Soft Start Time  0.108 F or 0.1 F To set the Soft Start time, first calculate the external ramp size at a duty−cycle of D = 1.630 V/12 V = 0.135: ISS is the Soft−Start charge current from the data sheet. (VIN  VOUT) Ext_Ramp  D  (RCSn  CCSn  fSW)  0.135  (37) (12 V  1.630 V) 60 k  0.01 F  220 kHz)  11 mV V2 is a trademark of Switch Power, Inc. http://onsemi.com 29 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−28 WB CASE 751F ISSUE J DATE 23 SEP 2015 SCALE 1:1 −X− D 28 15 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBER PR5OTRUSION SHALL NOT BE 0.13 TOTATL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. H E 0.25 Y M M −Y− 1 14 PIN 1 IDENT A L 0.10 G B 0.025 M T X S A1 Y −T− SEATING PLANE DIM A A1 B C D E G H L M C M S SOLDERING FOOTPRINT GENERIC MARKING DIAGRAM* 8X 11.00 28X 28 1.30 1 MILLIMETERS MIN MAX 2.35 2.65 0.13 0.29 0.35 0.49 0.23 0.32 17.80 18.05 7.40 7.60 1.27 BSC 10.05 10.55 0.41 0.90 0_ 8_ XXXXXXXXXXXXXX XXXXXXXXXXXXXX XXXXXXXXXXXXXX AWLYYWWG 28 1 XXXXX A WL Y WW G 28X 0.52 1.27 PITCH 14 = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. 15 DIMENSIONS: MILLIMETERS DOCUMENT NUMBER: DESCRIPTION: 98ASB42345B SOIC−28 WIDE BODY Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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