NCP81174MNTXG

NCP81174 4/3/2-Phase Synchronous Buck Controller with Power Saving Mode and PWM VID Interface www.onsemi.com The NCP81174 is a general−purpose up to four−phase synchronous buck controller. It combines differential voltage sensing, differential phase current sensing, and PWM VID interface to provide accurate regulated power for the computer or graphic controllers. It can receive power saving command (PSI) from processors and operates in single−phase diode emulation mode to obtain high efficiency in light load. Dual−edge multiphase PWM modulation ensures a fast transient response with minimum possible capacitors. Features • • • • • • • • • • • • • • QFN32 MW SUFFIX CASE 488AM 1 NCP81174 AWLYYWWG G A WL YY WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION Typical Applications • GPU and CPU Power • Graphics Card Applications • Desktop and Notebook Applications March, 2015 − Rev. 5 32 MARKING DIAGRAM Output Voltage up to 2.0 V with PWM VID Interface Support 1.8 V and 3.3 V VID interface Remote Differential Output Voltage Sense Differential Current Sense For Each Phase 200 kHz − 1000 kHz Switching Frequency Power Saving Interface (PSI) Power Good Output Thermally Compensated Current Monitoring Over Current Protection Fast Transient Response 5 V VCC Shunt Regulator Latched OVP and UVP Protections QFN−32, 5 x 5 mm, 0.5 mm Pitch Package This is a Pb−Free Device © Semiconductor Components Industries, LLC, 2015 1 Device Package Shipping† NCP81174MNTXG QFN32 (Pb−Free) 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 1 Publication Order Number: NCP81174/D G3 G2 G1 30 DRVON 31 G4 VREF 32 VCC REFIN NCP81174 29 28 27 26 25 VIDBUF 1 24 CS4 VID 2 23 CS4N VR_RDY 3 22 CS3 EN 4 21 CS3N PSI 5 20 CS2 12VMON 6 19 CS2N ROSC 7 18 CS1 ILIM 8 17 CS1N NCP81174 Top View (not to scale) 13 14 15 16 VFB VDFB CSSUM 12 VDRP 11 COMP 10 DIFFOUT VSP 9 VSN FLAG/GND (Pin 32) Figure 1. Pinout www.onsemi.com 2 NCP81174 12V_FILTER 12V_FILTER 12V_FILTER D1 3.3V C4 C3 4 PSI 5 VR_RDY 3 VID EN 30 OD IN RFB CFB1 RFB1 RF 12 13 CF CH 14 15 RDRP 16 RNOR L1 SW DRL Q2 PSI VR_RDY R2 RS1 C2 CS1 25 G1 18 CS1 17 CS1N 26 G2 20 CS2 19 CS2N VSN 27 G3 VSP NCP81174 22 CS3 DIFFOUT 21 CS3N 28 G4 24 CS4 COMP 23 CS4N VFB 29 VDRP DRVON 12V_FILTER 12V_FILTER BST VCC OD IN DRH SW DRL PGND VDFB 12V_FILTER 12V_FILTER CSSUM + 10 9 11 Q1 DRH PGND 2 VID 31 VREF 32 REFIN 1 VIDBUF VREF BST VCC VCC VR_EN 12VMON 6 C1 U2 8 ILIM 33 GND RISO1RT2 RISO2 7 ROSC R6 CDFB CPU GND BST VCC VREF ROSC OD IN DRH SW DRL PGND 12V_FILTER 12V_FILTER BST VCC OD IN DRH SW DRL PGND VSP VSN Figure 2. Typical Four Phase Application Circuit with PWM−VID Interface www.onsemi.com 3 NCP81174 VID UVP&OVP VIDBUF REFIN G1 G2 PWM Control VSN VSP G3 G4 PSI DIFFOUT ILIM EN VFB Fault Logic UVLO PGOOD COMP VR_RDY 12VMON DRVON VDFB VDRP CSSUM VREF CS1 CS1N VREF VCC CS2 CS2N CS3 Ramp Generator CS Amps RSOC CS3N CS4 GND CS4N Figure 3. Functional Block Diagram www.onsemi.com 4 NCP81174 PIN DESCRIPTION Pin Name 1 VIDBUF Description 2 VID 3 VR_RDY 4 EN Chip enable. 5 PSI Power saving control. Three levels. 6 12VMON 7 ROSC VID PWM pulse output from an internal buffer. Voltage ID from processor. Power good indicator. 12 V input power rail monitor. It is a divided down voltage from the input power rail, should be kept to less than 4 V at all time. A resistance from this pin to ground programs the oscillator frequency. 8 ILIM Over current shutdown threshold setting. 9 VSP Non−inverting input to the internal differential remote sense amplifier. 10 VSN Inverting input to the internal differential remote sense amplifier. 11 DIFFOUT 12 COMP 13 VFB 14 VDRP Voltage signal proportional to the total current. 15 VDFB Current summing amplifier inverting input 16 CSSUM 17 CS1N 18 CS1 19 CS2N Output of the differential remote voltage sense amplifier. Output of the compensation amplifier. Inverting input of the compensation error amplifier Current summing output signal Inverting input to current sense amplifier, phase 1. Non−inverting input to current sense amplifier, phase 1. Inverting input to current sense amplifier, phase 2. 20 CS2 21 CS3N Non−inverting input to current sense amplifier, phase 2. 22 CS3 23 CS4N 24 CS4 25 G1 Phase 1 PWM output, 3 levels. 26 G2 Phase 2 PWM output, 3 levels. 27 G3 Phase 3 PWM output, 3 levels. 28 G4 Phase 4 PWM output, 3 levels. 29 DRVON 30 VCC Power supply for the chip. NCP81174 has a built−in 5 V shunt regulator, allowing it to connect to the external 12 V supply through a resistor. Do not connect a 5 V supply to VCC directly. 31 VREF 2.0 V output reference voltage. A 10 nF ceramic capacitor is recommended to connect this pin to ground. 32 REFIN Reference voltage input for output voltage regulation. 33 FLAG Thermal pad and analog ground, connected to system ground. Inverting input to current sense amplifier, phase 3. Non−inverting input to current sense amplifier, phase 3. Inverting input to current sense amplifier, phase 4. Non−inverting input to current sense amplifier, phase 4. Gate driver enable. www.onsemi.com 5 NCP81174 MAXIMUM RATINGS ELECTRICAL INFORMATION Pin Symbol VMAX VMIN ISOURCE ISINK COMP 5.5 V −0.3 V 10 mA 10 mA VDRP 5.5 V −0.3 V 5 mA 5 mA VSP 5.5 V GND – 300 mV 1 mA 1 mA VSN GND + 300 mV GND – 300 mV 1 mA 1 mA DIFFOUT 5.5 V −0.3 V 20 mA 20 mA VR_RDY 5.5 V −0.3 V N/A 20 mA VCC 7.0 V −0.3 V N/A 10 mA ROSC 5.5 V −0.3 V 1 mA N/A PWMVID 5.5 V −0.3 V (−2 V, 2.5 V) PSI Level Power Mode Phase Configuration High (PSI ≥ 2.4 V) PS0 Full Phase, FCCM Intermediate (0.8V < PSI < 2.4 V) PS1 1−Phase, FCCM Low (PSI ≤ 0.8 V) PS2 1−Phase, Auto CCM/DCM Table 2. POWER SAVING INTERFACE (PSI) CONFIGURATIONS (1.8 V I/O, 2.5 V > EN > 1.1 V) PSI Level Power Mode Phase Configuration High (PSI ≥ 1.4 V) PS0 Full Phase, FCCM Intermediate (0.8 V < PSI < 1.4 V) PS1 1−Phase, FCCM Low (PSI ≤ 0.8 V) PS2 1−Phase, Auto CCM/DCM Remote Voltage Sense REFIN A true differential amplifier allows the NCP81174 to measure Vcore voltage feedback with respect to the Vcore ground reference point by connecting the Vcore reference point to VSP, and the Vcore ground reference point to VSN. This configuration keeps ground potential differences between the local controller ground and the Vcore ground reference point from affecting regulation of Vcore between Vcore and Vcore ground reference points. The remote sensing amplifier also subtracts the REFIN (DAC) voltage, thereby producing an unamplified output error voltage at the DIFFOUT pin. This output also has a 1.3 V bias voltage as the floating ground to allow both positive and negative error voltages. VSN VSP DIFFOUT Figure 4. Voltage Remote Sense www.onsemi.com 11 NCP81174 Switching Frequency PWM VID The Rosc pin provides a 2.0 V reference voltage. The resistor connected to this pin will sink current from the pin to ground. This current is internally mirrored into a capacitor to create an oscillator. The period is proportional to the resistance and the frequency is inversely proportional to the total resistance. The total resistance may be estimated by equation 1. This equation is valid for the individual phase frequency in multi−phase mode PS0 and single phase mode PS1. In PS2, the frequency will be close to set frequency in CCM and scaled down with load current in DCM operation. The NCP81174 receives the PWMVID signal from the upstream controller for the Vcore regulation. The signal is decoded internally and passed to the VID buffer output (VIDBUF), where the duty cycle is converted to a corresponding signal between 0 V and 2 V. The VIDBUF high level is derived from a precise 2.0 V reference voltage. The VIDBUF signal is then filtered through the external low pass filter constructed by R_REFADJ and C_REFIN. The filtered output is connected to the REFIN pin. The REFIN is the voltage reference of the Vcore regulator. The output voltage maximum, minimum, and also boot voltage can be calculated with below equations. Rosc ^ 20947 @ F SW −1.1262 (eq. 1) V max + Vref @ ROSC vs. FREQ 60 Calculation V min + Vref @ Real 50 Rosc−kohm 40 (eq. 2) R_VREF2 R VREF2 ) ǒR_VREF1 ø R_REFADJǓ R_VREF2 ø R_REFADJ (eq. 3) R VREF1 ) ǒR_VREF2 ø R_REFADJǓ V boot + V max ) V min (eq. 4) 2 30 20 10 0 100 1000 Freq−kHz Figure 5. ROSC vs. Frequency VREF R _VREF 1 VIDBUF REFIN R _REFADJ PWMVID R _VREF 2 C_ REFIN Figure 6. PWM VID Interface Soft Start The NCP81174 can decode both 1.8 V and 3.3 V PWMVID output levels. If the EN voltage input is more than 2.5 V, a 3.3 V PWMVID I/O is identified. If EN voltage is above 1.1 V (Overall chip enable threshold) but less than 2.5 V, a 1.8 V PWMVID I/O is assumed. The NCP81174 has an internal controlled soft start function. The output starts to ramp up following a system reset period after the device is enabled. The device is able to www.onsemi.com 12 NCP81174 start up smoothly under an output pre−biased condition without discharging the output before ramping up. Before the output soft start begins, an internal switch will be turned on to discharge the external filter cap C_REFIN connected to the REFIN pin to reset the DAC setting, the typical on resistance of the switch is around 6 Ws. After the discharging, internal switch will be turned off to allow external C_REFIN cap to recharge. After 100 ms, the output voltage ramps up with a fixed slew rate of 1.3 mV/mS. The circuit can be set to start from either all the phases when the input power rails are all available or from phase 1 when only one input power rail is available by presetting the power mode from PSI pin (See Power Operation Modes). sense amplifier must be connected across the current sensing element of the phase controlled by the corresponding gate output (G1, G2, G3, or G4). If a phase is unused, the differential inputs to that phase’s current sense amplifier must be shorted together and connected to the output. A voltage is generated across the current sense element (such as an inductor or sense resistor) by the current flowing in that phase. The outputs of four current amplifiers are fed into a summing amplifier to have a summed−up output (CSSUM). Signal of CSSUM combines information of total current of all phases in operation. The gain from the total sense current input to CSSUM (ACSSUM) is ~3.93. The output of the current sense amplifiers are used to control three functions. First, the output controls the adaptive voltage positioning, where the output voltage is actively controlled according to the output current. Second, the output signal is fed to the current limit circuit. This again is the summed current of all phases in operation. Finally, the individual phase current is connected to the PWM comparator. In this way current balance is accomplished. 5V Shunt Regulator The NCP81174 has an internal shunt regulator to generate 5 V from the external power supply (e.g. 12 V). It is recommended to connect three 0603 resistors (450 W each) in parallel from a 12 V power supply to the VCC pin. Thermal Compensation Amplifier with VDRP and VDFB pins Undervoltage Lockout (VCC UVLO) and 12VMON Thermal compensation amplifier is an internal amplifier in the path of droop current feedback for additional adjustment of the gain of summing current and temperature compensation. The way thermal compensation is implemented separately ensures minimum interference to the voltage loop compensation network. VCC is constantly monitored for undervoltage lockout (UVLO). Line input (normally 12V) is monitored for undervoltage lockout through 12VMON pin by connecting an appropriate resistor divider from line input to the 12VMON input. The setting of the resistor divider should make the 12VMON voltage less than 4 V at all time. During power-up, both VCC and 12VMON will be monitored. Only after they exceed their individual UVLO thresholds, the full circuit will be activated and ready for soft start if the enable pin is also valid. Both UVLO comparators have hysteresis to avoid chattering. The second function of 12VMON pin is to provide feed-forward input voltage information in PS2 mode, see Power Operation Mode section. PWM Comparators with Hysteresis and 3rd state of PWM Outputs Four PWM comparators receive an error signal at their non−inverting input and one of the triangle waves at its inverting input. The output of each comparator generates the PWM outputs G1, G2, G3 and G4. During the steady state operation, the duty cycle will center on the valley of the triangle waveform, with steady state duty cycle calculated by Vout/Vin. During a transient event, both high and low comparator output transitions shift phase to the points where the error signal intersects the down and up ramp of the triangle wave. PWM signals vary between high and low in all phase operation or forced PWM mode. In power saving mode (PS2), PWM signals vary between high and mid level to allow diode emulation. Over Current Protection and Under Voltage Protection A programmable overcurrent function is incorporated within the IC. The inverting input of the comparator is connected to the ILIM pin. The voltage at this pin (0~2 V) sets the maximum output current the converter can produce. The VREF pin provides a convenient and accurate reference voltage from which a resistor divider can create the overcurrent setpoint voltage. Although not actually disabled, tying the ILIM pin directly to the VREF pin sets the limit above useful levels − effectively disabling overcurrent shutdown. The comparator non−inverting input is the summed current information from the current sense amplifier. The overcurrent event will set PWM low for the rest of the cycle when the current information exceeds the voltage at the ILIM pin. If the overcurrent continuously happens and the output will eventually hit the Under Voltage Protection (UVP) limit and it will be a latched event. The UVP limit is set to 50% below the REFIN voltage. The PWM outputs will stay at mid state until the VCC voltage is removed and re−applied, or the ENABLE input is brought low and then high. 2/3/4 Phase Operation Besides 4−phase, the part can be configured to run in 2 or 3−phase mode. In 2−phase mode, phase 1 and 3 should be used to drive the external gate drivers, gate outputs G2 and G4 should be grounded. In 3−phase mode, gate output G4 should be grounded. The current sense inputs of the unused channels should be connected to the Vcore output. Differential Current Sense Amplifiers and Summing Amplifier Four differential amplifiers are provided to sense the output current of each phase. The inputs of each current www.onsemi.com 13 NCP81174 Over Voltage Protection if 50% over REFIN creates a voltage above the 2 V. The outputs will remain disabled until the VCC voltage is removed and reapplied, or the ENABLE input is brought low and then high. An output voltage monitor is incorporated. During normal operation, if the output voltage is 50% over the REFIN, the VR_RDY goes low, the DRVON signal remains high, and PWM outputs are set low. The limit will be clamped to 2 V DESIGN METHODOLOGY Programming the Current Limit Acssum Adrp RNOR The VREF pin provides a 2.0 V reference voltage which is divided down with a resistor divider (RLIM1/RLIM2) and fed into the current limit pin ILIM. The current limit function is based on the total sensed current of all phases multiplied by a controlled gain (Acssum*Adrp). DCR sensed inductor current is a function of the winding temperature. If not using thermal compensation, the best approach is to set the maximum current limit based on expected average maximum temperature of the inductor windings, I1 RISO1 RT2 RISO2 I2 − + I3 RSUM + I4 + OCP − event Ilim Figure 7. ACSSUM and ADRP (eq. 5) DCR Tmax + DCR 25 @ (1 ) 0.00393 @ (T max * 25)) As introduced before, VLIMIT comes from a resistor divider connected to VREF, thus For multiphase controller, the ripple current can be calculated as, I PP + ǒV in * N @ V outǓ @ V out V LIMIT + 2 V @ (eq. 6) L @ F SW @ V in A DRP + − V LIMI ^ A CSSUM @ A DRP @ DCR TMAX (eq. 7) V LIMIT ^ A CSSUm @ A DRP @ DCR TMAX @ ǒ I MIN_OCP @ ) 0.5 @ @ COEpsi (eq. 8) R NOR @ ǒR ISO1 ) R ISO2 ) R T2Ǔ (eq. 9) ǒR NOR ) R ISO1 ) R ISO2 ) R T2Ǔ @ R SUM RISO1 and RISO2 are in series with RT2 , the NTC temperature sense resistor placed near inductor. RSUM is the resistor connecting between pin VDFB and pin CSSUM. In PS0 mode, the current limit follows the Equation 10; In PS1 or PS2, the current limit calculation follows Equation 11, COEpsi is a coefficient for the current limiting related in power saving mode PS1, PS2. COEpsi value is one over the original phase count N. Refer to the PSI and phase shedding section for more details. Ǔ ǒV in * N @ V outǓ @ V out L @ F SW @ V in R LIM2 ) R LIM2 A CSSUM X+ −3.93 Therefore calculate the current limit voltage as below, @ ǒI MIN_OCP @ ) 0.5 @ I PPǓ R LIM2 In Equation 7, ACSSUM and ADRP are the gain of current summing amplifier and droop amplifier. 2 V@R LIM2 R LIM1)R LIM2 I LIMIT(normal) ^ 3.93 @ R NOR@ǒR ISO1)R ISO2)R T2Ǔ ǒR NOR@R ISO1)R ISO2)R T2Ǔ@R SUM * 0.5 @ @ DCR 25° @ (1 ) 0.00393 @ (T inductor * 25)) (V in * V out) @ V out L @ F SW @ V in 2 V@R LIM2 R LIM1)R LIM2 I LIMIT(normal) ^ 3.93 @ R NOR@ǒR ISO1)R ISO2)R T2Ǔ ǒR NOR@R ISO1)R ISO2)R T2Ǔ@R SUM * 0.5 @ (eq. 10) ǒV * V outǓ @ V in @ COEpsi @ DCR 25° @ ǒ1 ) 0.00393 @ ǒT inductor * 25ǓǓ out L @ F SW @ V in N is the number of phases involved in the circuit. www.onsemi.com 14 (eq. 11) NCP81174 Inductor Current Sensing Compensation R sense(T) + The NCP81174 uses the inductor current sensing method. An RC filter is selected to cancel out the impedance from inductor and recover the current information through the inductor’s DCR. This is done by matching the RC time constant of the sensing filter to the L/DCR time constant. The first cut approach is to use a 0.1 uF capacitor for C and then solve for R. (eq. 12) L 0.1 @ mF @ DCR 25C @ (1 ) 0.00393 @ (T * 25)) Because the inductor value is a function of load and inductor temperature final selection of R is best done experimentally on the bench by monitoring the VDRP pin and performing a step load test on the actual solution. Compensation and Output Filter Design E1 + R14 − V3 Voff E C6 0 0 0 12 1 L 2 DCR 1 LBRD 2 RBRD 0 VRamp_min CBulk CCer RSUM ESRBulk ESRCer 2 2 RDFB ESLBulk Vout ESLCer R8 Voff 1E4 1 1 Vdrp C5 0 C_REFIN R_VIDBUF R12 COMP PWMVID 0 R_VREF2 CFB1 CH RFB1 CF VREF 2.0V REFIN 0 RF R_VREF1 0 RFB 0 V4 R6 Voff 1E4 Voffset C4 0 0 Figure 8. System Average Model (eq. 13) 1 1 + 2p @ CF @ RF 2p @ (RBRD ) ESRBulk) @ CBulk A simple state average model shown in Figure 8 can be used to assist the system design and determine a stable solution. The goal is to compensate the system such that the resulting gain generates constant output impedance from DC up to the frequency where the ceramic takes over holding the impedance below the target output impedance. By matching the following equations a good set of starting compensation values can be found for a typical mixed bulk and ceramic capacitor type output filter. (eq. 14) 1 1 + 2p @ CCer @ (RBRD ) ESRBulk) 2p @ CFB1 @ (RFB1 ) RFB) Droop Injection and Thermal Compensation The VDRP signal is generated by summing the sensed output currents for each phase. A droop amplifier is added to adjust the total gain to approximately eight. VDRP is www.onsemi.com 15 NCP81174 externally summed into the feedback network by the resistor RDRP. This introduces an offset which is proportional to the output current thereby forcing a controlled, resistive output impedance. RDRP determines the target output impedance by the basic equation: V out I out + Z out + R FB @ DCR @ A CCSUM @ A DRP CH CFB1 RFB1 RF R DRP + CF − + + 1.3 V RDRP Droop Amp RT RISO2 − Error Amp 1.3 V RISO1 RSUM Gain = 4 − + CSSUM Amp 1.3 V RSx + + RL + − CSx Gain = 1 Figure 9. Droop Injection and Thermal Compensation Z out(T) + (eq. 17) Actual DCR increases by temperature. The system can be thermally compensated to cancel this effect to a great degree by adding an NTC in parallel with RNOR to reduce the droop gain as the temperature increases. The NTC device is nonlinear. Putting a resistor in series with the NTC helps make the device appear more linear with temperature. The series resistor is split and inserted on both sides of the NTC to reduce noise injection into the feedback loop. The recommended total value for RISO1 plus RISO2 is approximately 1.0 kW. The output impedance varies with inductor temperature by the equation: − RNOR (eq. 16) Z out DCR(T) + DCR 25C @ (1 ) 0.00393 @ (T * 25)) PWM Comparator + R FB @ DCR @ A CSSUM @ A DRP The value of the inductor’s DCR is a function of temperature according to Equation 17: RFB I Bias (eq. 15) R DRP R FB @ DCR 25C @ (1 ) 0.00393 @ (T * 25)) @ A CSSUM @ A DRP (eq. 18) R DRP By including the NTC RT2 and the series isolation resistors the new equation becomes: R FB @ DCR 25C @ (1 ) 0.00393 @ (T * 25)) @ A CSSUM @ Z out(T) + R NOR )R ISO1 )R ISO2 Ǔ T2 ǒRNOR)RISO1)RISO2)RT2Ǔ@RSUM (eq. 19) R DRP Zout vs Temperature The typical equation of an NTC is based on a curve fit Equation 20: RT2(T) + RT2 25C @ e b ǒ @ R ƪǒ Ǔ ǒ Ǔƫ 1 1 * 298 273 ) T 0.0013 Zout 0.0012 Zout(uncomp) (eq. 20) 0.0011 Ohm Figure 10 shows an example of the comparison of the compensated output impedance and uncompensated output impedance varying with temperature. 0.001 0.0009 0.0008 0.0007 0.0006 25 45 65 85 105 Celsius Figure 10. Zout vs. Temperature (10 kW NTC with a b value of 3740) www.onsemi.com 16 NCP81174 SYSTEM TIMING DIAGRAM 12V, VSYS 5V, VCC EN 3.3V or 1.8V 1.1ms PWMVID, 1V DRVON ~700 us VBOOT VSP−VSN ~100 us VRRDY REFIN VBOOT Figure 11. System Timing Diagram www.onsemi.com 17 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS QFN32 5x5, 0.5P CASE 488AM ISSUE A 1 32 SCALE 2:1 A D PIN ONE LOCATION ÉÉ ÉÉ NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30MM FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L L B DATE 23 OCT 2013 L1 DETAIL A ALTERNATE TERMINAL CONSTRUCTIONS E DIM A A1 A3 b D D2 E E2 e K L L1 0.15 C 0.15 C EXPOSED Cu A DETAIL B 0.10 C (A3) A1 0.08 C DETAIL A 9 32X L ALTERNATE CONSTRUCTION GENERIC MARKING DIAGRAM* K D2 1 XXXXXXXX XXXXXXXX AWLYYWWG G 17 8 MOLD CMPD DETAIL B SEATING PLANE C SIDE VIEW NOTE 4 ÉÉ ÉÉ ÇÇ TOP VIEW MILLIMETERS MIN MAX 0.80 1.00 −−− 0.05 0.20 REF 0.18 0.30 5.00 BSC 2.95 3.25 5.00 BSC 2.95 3.25 0.50 BSC 0.20 −−− 0.30 0.50 −−− 0.15 E2 1 32 25 e e/2 32X b 0.10 M C A B 0.05 M C BOTTOM VIEW XXXXX = Specific Device Code A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. NOTE 3 RECOMMENDED SOLDERING FOOTPRINT* 5.30 32X 0.63 3.35 3.35 5.30 0.50 PITCH 32X 0.30 DIMENSION: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON20032D QFN32 5x5 0.5P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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