NCT7491MNTXG

NCT7491 Remote Thermal Monitor and Fan Controller with PECI 3.0 Interface and SMBus Compatible Master The NCT7491 is a two−wire serially programmable hardware monitor. It can monitor 2 remote temperature zones and its own ambient temperature. A PECI 3.0 single wire interface allows the NCT7491 to monitor CPU temperatures. The NCT7491 also implements an SMBus compatible master, allowing it to read automatically from thermal sensors on the SMBus. The NCT7491 can automatically control the speed of 3 fans using PWM control, and monitor the speed of 4 fans. There are 4 analog inputs, used for measuring 12 V, 5 V, 2.5 V and Vccp channels. The NCT7491 supply voltage and PECI VTT voltage are also monitored. Each of the measured temperature, voltage and fan speed values are compared with programmable limits and if any channel is outside the programmed limit an interrupt is generated via the ALERT output pin. A THERM output is also available for fail−safe thermal control. Up to 3 GPIO pins are available for digital control or signalling. Communication with the NCT7491 is accomplished via the SMBus/I2C interface which is compatible with industry standard protocols. The SMBus address is set by 2 address selection pins. The NCT7491 is available in a 24−lead QFN or QSOP package and operates over a supply range of 3.0 V to 3.6 V. Features • • • • • • • • • • • • • • • • PECI 3.0 Master for CPU Monitoring SMBus Compatible Master On−chip Temperature Sensor 2 Remote Sensor Channels Series Resistance Cancellation on Remote Sensors 3 PWM Fan Control Outputs 4 Tach Monitoring Input PWM Automatic Fan Speed Control 4 Analog Inputs for Voltage Monitoring Vdd Supply Voltage Monitoring PECI VTT Voltage Monitoring Overtemperature Outputs Limit Comparison of Monitored Channels SMBus Address Selection Allows up to 3 Devices Meets SMBus 2.0 Electrical Specifications (fully SMBus 1.1 compliant) These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant © Semiconductor Components Industries, LLC, 2016 June, 2016 − Rev. 3 1 www.onsemi.com QFN24 MN SUFFIX CASE 485L QSOP24 RQ SUFFIX CASE 492B MARKING DIAGRAMS NCT 7491 ALYWG G (Top View) A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) NCT7491 YYWWG (Top View) A (Bottom View) NCT7491 = Specific Device Code A = Assembly Location YY = Year WW = Work Week G = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 79 of this data sheet. Publication Order Number: NCT7491/D NCT7491 Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 NCT7491 QSOP Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 NCT7491 QFN Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 QSOP & QFN Package Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Comparison of NCT7491 and ADT7490 QSOP pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Functional Comparison between the NCT7491 and the ADT7490 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Typical System Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SMBus Slave Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Analog Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Push Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PECI 3.0 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 SMBus Compatible Master Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Automatic Fan Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Fan Override Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Fan Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 THERM Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 THERM Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 SMBALERT Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Voltage Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 GPIO Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 VCCP Low Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 XNOR Tree Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Register Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 QSOP Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 QFN Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 www.onsemi.com 2 NCT7491 NCT7491 QSOP Pinout SDA_S 1 24 PWM1/XTO SCL_S 2 23 Vccp GND 3 22 +2.5Vin/THERM VDD 4 SDA_M/GPIO1 5 SCL_M/GPIO2 6 PECI 7 18 D1+ VTT 8 17 D1− TACH3 9 16 D2+ PWM2/SMBALERT 10 15 D2− NCT7491 21 +12Vin TOP VIEW 20 +5Vin (Not to scale) 19 GPIO3/THERM/SMBALERT TACH4/THERM/SMBALERT/ ADDR SELECT TACH1 11 14 TACH2 12 13 PWM3/ADDREN NCT7491 QFN Pinout www.onsemi.com 3 NCT7491 Table 1. ABSOLUTE MAXIMUM RATINGS Parameter Rating Positive Supply Voltage (VCC) 3.6 V Maximum Voltage on +12VIN Pin 14 V Maximum Voltage on +5VIN Pin 6.25 V Maximum Voltage on All Open−Drain Outputs (excluding PWM pins) 3.6 V Maximum Voltage on PWM Pins +5.5 V Maximum Voltage on TACH Pins +5.5 V Voltage on Remaining Input or Output Pins −0.3 V to +4.2 V Input Current at Any Pin ±5 mA Package Input Current ±20 mA Maximum Junction Temperature (TJ max) 150°C Storage Temperature Range −65°C to +150°C Lead Temperature, Soldering IR Reflow Peak Temperature 220°C Pb−Free Peak Temperature 260°C Lead Temperature (Soldering, 10 sec) 300°C ESD Rating HBM 2 kV FICDM 0.5 kV Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Specifications TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted. All voltages are measured with respect to GND, unless otherwise specified. Typical voltages are at TA = 25°C and represent a parametric norm. Logic inputs accept input high voltages up to VMAX, even when the device is operating down to VMIN. Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge, and VIH = 2.0 V for a rising edge. SMBus timing specifications are guaranteed by design and are not production tested. Table 2. SPECIFICATIONS Parameter Min Typ Max Unit Test Conditions/Comments 3.0 3.3 3.6 V 1.5 5 mA Interface inactive, ADC active Local Sensor Accuracy ±0.5 ±3.5 °C 0°C ≤ TA ≤ 85°C Local Sensor Resolution 0.25 Remote Diode Sensor Accuracy ±0.5 Remote Sensor Resolution 0.25 °C 30 mA Low Level 1 240 mA High Level 1 37.5 mA Low Level 2 300 mA High Level 2 POWER SUPPLY Supply Voltage Supply Current, ICC TEMP−TO−DIGITAL CONVERTER Remote Sensor Source Current Series Resistance Cancellation °C ±3.5 270 www.onsemi.com 4 °C W 0°C ≤ TA ≤ 85°C −40°C ≤ TD ≤ 125°C NCT7491 Table 2. SPECIFICATIONS Parameter Min Typ Max Unit Test Conditions/Comments ±2 % For 12 V channel ±1.5 % For all other channels ±1 LSB 8 bits ANALOG−TO−DIGITAL CONVERTER (INCLUDING MUX AND ATTENTUATORS) Total Unadjusted Error (TUE) Differential Nonlinearity (DNL) ±0.1 %/V Conversion Time (Voltage Input) 11 ms Averaging enabled, 16 samples per averaged reading. Conversion Time (Local Temperature) 38 ms Averaging enabled, 16 samples per averaged reading. Conversion Time (Remote Temperature) 38 ms Averaging enabled, 16 samples per averaged reading. Input Resistance 224 kW For +12 V channel 110 kW For all other channels Power Supply Sensitivity FAN RPM−TO−DIGITAL CONVERTER ±10 % 0°C ≤ TA ≤ 85°C ±14 % −40°C ≤ TA ≤ 125°C 109 RPM Fan count = 0xBFFF 329 RPM Fan count = 0x3FFF 5,000 RPM Fan count = 0x0438 10,000 RPM Fan count = 0x021C Accuracy Full−Scale Count 65,535 Nominal Input RPM OPEN−DRAIN DIGITAL OUTPUTS, PWM1 TO PWM3, XTO Current Sink, IOL 8.0 mA Output Low Voltage, VOL 0.4 V IOUT = −8.0 mA 20 mA VOUT = VCC 0.4 V IOUT = −4.0 mA 1.0 mA VOUT = VCC High Level Output Current, IOH 0.1 OPEN−DRAIN SERIAL DATA BUS OUTPUTS (SDA, SDA_M, SCL_M) Output Low Voltage, VOL High Level Output Current, IOH 0.1 SMBus DIGITAL INPUTS (SCL, SDA, SDA_M) Input High Voltage, VIH 2.0 V Input Low Voltage, VIL 0.4 Hysteresis 500 V mV DIGITAL I/O (PECI PIN) VTT Supply Voltage Input High Voltage, VIH 0.85 1.26 0.55*Vtt V Input Low Voltage, VIL Hysteresis High level output source current, ISOURCE V 0.5*Vtt V 0.1Vtt V Hysteresis between input switching levels −6 mA Output High Voltage, VOH = 0.75*Vtt mA Output Low Voltage, VOL = 0.25*Vtt mVp−p Noise glitches from 10 − 100MHz Width up to 50ns Low level output sink current, ISINK 0.5 Signal noise immunity, Vnoise 300 1.0 www.onsemi.com 5 NCT7491 Table 2. SPECIFICATIONS Parameter Min Typ Max Unit Test Conditions/Comments DIGITAL INPUT LOGIC LEVELS (TACH INPUTS) Input High Voltage, VIH 2.0 V Input Low Voltage, VIL 5.5 V 0.8 V −0.3 V Hysteresis 0.5 Maximum input voltage Minimum input voltage Vp−p DIGITAL INPUT LOGIC LEVELS (THERM) Input High Voltage, VIH 0.75 x VTT V Input Low Voltage, VIL 0.4 V DIGITAL INPUT CURRENT Input High Current, IIH ±1 mA VIN = VCC Input Low Current, IIL ±1 mA VIN = 0 Input Capacitance, CIN 5 pF SLAVE SERIAL BUS TIMING (See Figure 1) 10 Clock Frequency, fSCLK Glitch Immunity, tSW 100 kHz 50 ns Bus Free Time, tBUF 4.7 ms SCL Low Time, tLOW 4.7 ms SCL High Time, tHIGH 4.0 50 ms SCL, SDA Rise Time, tr 1,000 ns SCL, SDA Fall Time, tf 300 ns Data Setup Time, tSU;DAT 250 Detect Clock Low Timeout, tTIMEOUT 15 ns 35 ms Can be optionally disabled MASTER SERIAL BUS TIMING 100 Clock Frequency, fSCLK tLOW tR kHz tF tHD; STA SCL tHD; STA SDA tHD; DAT tHIGH tSU; STA tSU; DAT tBUF P S tSU; STO S Figure 1. SMBus Timing Diagram for Slave Port and Master Port www.onsemi.com 6 P NCT7491 Table 3. QSOP & QFN PACKAGE PIN ASSIGNMENTS QSOP Pin No. QFN Pin No. Pin Name Description 1 22 SDA_S SMBus/I2C 2 23 SCL_S Serial Clock Slave Input. Open−drain pin; Requires a pull−up resistor. 3 24 GND Ground 4 1 VDD Positive Supply Voltage 5 2 SDA_M / GPIO1 Open−drain pin; Requires a pull−up resistor. GPIO1 = General purpose I/O pin SDA_M = SMBus/I2C Master Serial Bi−directional Data Input/Output. 6 3 SCL_M / GPIO2 Open−drain pin; Requires a pull−up resistor. GPIO2 = General purpose I/O pin SCL_M = Serial Clock Master Output. 7 4 PECI PECI input to report CPU Thermal Information. PECI voltage level is referenced to the VTT input. 8 5 VTT Voltage reference for PECI. This is the supply voltage for the PECI interface and must be present to communicate over the PECI interface. 9 6 TACH3 10 7 PWM2 / #SMBALERT 11 8 TACH1 Fan tachometer input to measure Fan1 Fan tachometer input to measure Fan2 Slave Serial Bi−directional Data Input/Output. Open−drain pin; Requires a pull−up resistor. Fan tachometer input to measure Fan3 PWM output to control Fan2. Can be configured as an SMBALERT output. Open−drain pin; Requires a pull−up resistor. 12 9 TACH2 13 10 PWM3 / #ADDREN 14 11 TACH4/ #THERM/ #SMBALERT/ #ADDRESS SELECT 15 12 D2− Negative Connection for Remote Temperature Sensor 2. 16 13 D2+ Positive Connection for Remote Temperature Sensor 2. 17 14 D1− Negative Connection for Remote Temperature Sensor 1. 18 15 D1+ Positive Connection for Remote Temperature Sensor 1. 19 16 GPIO3/ #THERM/ #SMBALERT 20 17 +5Vin Analog Input. 0 V to 5 V. 21 18 +12Vin Analog Input. 0 V to 12 V. 22 19 +2.5V / #THERM Analog Input. 0 V to 2.5 V. May be reconfigured as a bidirectional THERM pin. Can be connected to the PROCHOT output of a processor, to time and monitor PROCHOT assertions. Can be used as an output to signal an overtemperature condition. In THERM mode it is an open−drain bidirectional pin and requires a pull up resistor. 23 20 Vccp Analog input. Monitors CPU core voltage (to maximum 0f 3.0 V). This pin must be connected to the NCT7491 supply voltage if it is unused. 24 21 PWM1 / XTO PWM output to control Fan 1. Open−drain pin; Requires a pull−up resistor. Also functions as the output for the XNOR tree test enable mode. PWM output to control Fan3. If pulled low on power−up the NCT7491 enters Address Select mode and the ADDRESS SELECT pin determines the slave address. Open−drain pin; Requires a pull−up resistor. Fan Tachometer Input to Measure Speed of Fan 4. May be reconfigured as a bidirectional THERM. Can be connected to thePROCHOT output of a processor, to time and monitor PROCHOT assertions. Can be used as an output to signal an overtemperature condition. The SMBALERT pin is used to signal out−of−limit comparisons of temperature, voltage, and fan speed. This is compatible with SMBus alert. Can also be used at device powerup to assign the SMBus address. If THERM or SMBALERT is enabled then a pull−up resistor is required. General−Purpose Open−Drain Digital Input/Output. Requires a pull−up resistor. Can be configured as a bidirectional THERM pin or as an SMBALERT pin. www.onsemi.com 7 NCT7491 Table 4. COMPARISON OF NCT7491 AND ADT7490 QSOP PINOUTS QSOP Pin No. NCT7491 ADT7490 1 SDA_S SDA 2 SCL_S SCL 3 GND GND 4 VDD VDD 5 SDA_M / GPIO1 GPIO1 6 SCL_M / GPIO2 GPIO2 7 PECI PECI 8 VTT VTT 9 TACH3 TACH3 10 PWM2 / #SMBALERT PWM2 / #SMBALERT 11 TACH1 TACH1 12 TACH2 TACH2 13 PWM3 /#ADDREN PWM3 /#ADDREN 14 TACH4/#THERM/#SMBALERT/ #ADDRESS SELECT TACH4/#THERM/#SMBALERT/ #ADDRESS SELECT 15 D2− D2− 16 D2+ D2+ 17 D1− D1− 18 D1+ D1+ 19 GPIO3/#THERM/#SMBALERT IMON 20 +5Vin +5Vin 21 +12Vin +12Vin 22 +2.5V / #THERM +2.5V / #THERM 23 Vccp Vccp 24 PWM1 / XTO PWM1 / XTO Functional Comparison between the NCT7491 and the ADT7490 • NCT7491 supports PECI 3.0 commands. • NCT7491 uses an SMBus Master port to read digital • The NCT7491 register map is organized into two pages. • temperatures. • IMON voltage monitoring pin (pin 19) on the ADT7490 • • • • • is replaced with digital pin (SMBALERT/THERM/GPIO) on the NCT7491 NCT7491 does not support Dynamic Tmin fan control. NCT7491 allows any combination of temperature sources to control any fan. NCT7491 allows individual PWM responses to THERM events. NCT7491 THERM behaviour is more flexible, allowing stepped response to THERM events. REPLACE mode for PECI is not supported by the NCT7491 • • • 0x00−0xFF (page 1) and 0x100−0x1FF (page 2) The NCT7491 supports PWM look−up table automatic fan control along with the Tmin/Trange control method used in the ADT7490 The NCT7491 allows temperatures to be written to the device from an external master. These values can be assigned for fan control and Limit/THERM assertion functions PECI fan control can be implemented in relative or absolute modes. Absolute mode uses the Tjmax value read from the CPU plus the PECI temperature to determine the actual core temperature. The reference for voltage measurement has changed from 2.25 V on the ADT7490 to 2 V on the NCT7491. www.onsemi.com 8 NCT7491 Functional Block Diagram Figure 2. Functional Block Diagram of NCT7491 www.onsemi.com 9 NCT7491 Typical System Connections Figure 3. System Connection Diagram www.onsemi.com 10 NCT7491 SMBus Slave Interface Control of the NCT7491 is carried out using the serial system management bus (SMBus). The NCT7491 is connected to this bus as a slave device, under the control of a master controller. The NCT7491 has a 7−bit serial bus address. When the device is powered up with the ADDREN pin high, the NCT7491 has a default SMBus address of 0101110 or 0x2E. The read/write bit must be added to get the 8−bit address. If more than one NCT7491 is to be used in a system, each additional NCT7491 is placed in address select mode by strapping ADDREN low on power−up. The logic state of the ADDRESS SELECT pin then determines the device’s SMBus address. The device address is latched on the first valid SMBus transaction, more precisely on the low−to−high transition at the beginning of the eighth SCL pulse, when the serial bus address byte matches the selected slave address. Any attempted changes in the address have no effect after this. the data line high after the 10th clock rising edge to assert a stop condition. In read mode, the master device overrides the acknowledge bit by floating the data line high during the low period before the ninth clock pulse; this is known as No acknowledge. The master takes the data line low during the low period before the 10th clock rising edge, and then high afetr the 10th clock rising edge to assert a stop condition. In the NCT7491, write operations contain either one or two bytes, and read operations contain one byte. To write data to one of the device data registers or read data from it, the address pointer register must be set so that the correct data register is addressed. Then data can be written into that register or read from it. The first byte of a write operation always contains an address that is stored in the address pointer register. If data is to be written to the device, the write operation must contain a second data byte that is written to the register selected by the address pointer register. This write operation is shown in Figure 4. The device address is sent over the bus, and then R/W is set to 0. This is followed by two data bytes. The first data byte is the address of the internal data register to be written to, which is stored in the address pointer register. The second data byte is the data to be written to the internal data register. When reading data from a register, there are two possibilities: • If the NCT7491 address pointer register value is unknown or not the desired value, it must first be set to the correct value before data can be read from the desired data register. This is done by performing a write to the NCT7491 as before, but only the data byte containing the register address is sent because no data is written to the register. This is shown in Figure 5. A read operation is then performed consisting of the serial bus address, R/W bit set to 1, followed by the data byte read from the data register. This is shown in Figure 6. • If the address pointer register is known to be already at the desired address, data can be read from the corresponding data register without first writing to the address pointer register, as shown in Figure 6. SMBus Addressing Options Table 5. SETTING THE SMBUS ADDRESS ADDREN pin state ADDRESS SELECT pin state Address 0 Low (10 kW to GND) 0101100 (0x2C) 0 High (10 kW pull−up) 0101101 (0x2D) 1 Don’t care 0101110 (0x2E) Data is sent over the serial bus in sequences of nine clock pulses: eight bits of data followed by an acknowledge bit from the slave device. Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, because a low−to−high transition when the clock is high may be interpreted as a stop signal. The number of data bytes that can be transmitted over the serial bus in a single read or write operation is limited only by what the master and slave devices can handle. When all data bytes have been read or written, stop conditions are established. In write mode, the master floats 1 9 9 1 SCL SDA 0 1 0 1 1 1 0 D7 R/W START B Y MASTER D6 ACK. B Y ADT7490 FRAME 1 SERIAL BUS ADDRESS BYTE D5 D4 D3 D2 D1 D0 ACK. B Y ADT7490 FRAME 2 ADDRESS POINTER REGISTER BYTE 1 9 SCL (CONTINUED) SDA (CONTINUED) D7 D6 D5 D4 D3 D2 FRAME 3 DATA BYTE D1 D0 ACK. B Y ADT7490 STOP BY MASTER Figure 4. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register www.onsemi.com 11 NCT7491 1 9 9 1 SCL SDA 0 1 0 1 1 1 0 D7 R/W D6 D4 D5 D2 D3 D1 D0 ACK. B Y ADT7490 START B Y MASTER FRAME 1 SERIAL BUS ADDRESS BYTE ACK. B Y ADT7490 FRAME 2 ADDRESS POINTER REGISTER BYTE STOP BY MASTER Figure 5. Writing to the Address Pointer Register Only 1 9 9 1 SCL SDA 0 START B Y MASTER 1 0 1 1 1 FRAME 1 SERIAL BUS ADDRESS BYTE 0 D7 R/W D6 D4 D5 ACK. B Y ADT7490 D2 D3 D1 D0 NO ACK. B Y STOP BY MASTER MASTER FRAME 2 DATA BYTE FROM ADT7490 Figure 6. Reading Data from a Previously Selected Register 6. The master asserts a stop condition on SDA and the transaction ends. For the NCT7491, the send byte protocol is used to write a register address to RAM for a subsequent single−byte read from the same address. This operation is illustrated in Figure 7. It is possible to read a data byte from a data register without first writing to the address pointer register if the address pointer register is already at the correct value. However, it is not possible to write data to a register without writing to the address pointer register because the first data byte of a write is always written to the address pointer register. In addition to supporting the send byte and receive byte protocols, the NCT7491 also supports the read byte protocol (see System Management Bus Specifications Rev. 2 for more information; this document is available from the SMBus organization). If several read or write operations must be performed in succession, the master can send a repeat start condition instead of a stop condition to begin a new operation. 1 2 S SLAVE ADDRESS W 3 4 5 6 A REGISTER ADDRESS A P Figure 7. Setting a Register Address for Subsequent Read If the master is required to read data from the register immediately after setting up the address, it can assert a repeat start condition immediately after the final ACK and carry out a single−byte read without asserting an intermediate stop condition. Write Operations The SMBus specification defines several protocols for different types of read and write operations. The ones used in the NCT7491 are discussed here. The following abbreviations are used in the diagrams: • S – Start • P – Stop • R – Read • /W – Write • A – Acknowledge • /A – No acknowledge Write Byte In this operation, the master device sends a command byte and one data byte to the slave device, as follows: 1. The master device asserts a start condition on SDA. 2. The master sends the 7−bit slave address followed by the write bit (low). 3. The addressed slave device asserts ACK on SDA. 4. The master sends a command code. 5. The slave asserts ACK on SDA. 6. The master sends a data byte. 7. The slave asserts ACK on SDA. 8. The master asserts a stop condition on SDA, and the transaction ends. The byte write operation is illustrated in Figure 8. The NCT7491 uses the following SMBus write protocols. Send Byte In this operation, the master device sends a single command byte to a slave device, as follows: 1. The master device asserts a start condition on SDA. 2. The master sends the 7−bit slave address followed by the write bit (low). 3. The addressed slave device asserts ACK on SDA. 4. The master sends a command code. 5. The slave asserts ACK on SDA. 1 2 3 SLAVE S ADDRESS W A 4 5 6 REGISTER ADDRESS A DATA 7 A P Figure 8. Single Byte Write to a Register www.onsemi.com 12 8 NCT7491 Read Operations the bus is locked and releases the bus. This prevents the device from locking or holding the SMBus expecting data. Some SMBus controllers cannot work with the SMBus timeout feature, so it can be disabled. Register 0x11 TODIS = 0, SMBus timeout enabled (default). TODIS = 1, SMBus timeout disabled. The NCT7491 uses the following SMBus read protocols. Receive Byte This operation is useful when repeatedly reading a single register. The register address must be previously set up. In this operation, the master device receives a single byte from a slave device, as follows: 1. The master device asserts a start condition on SDA. 2. The master sends the 7−bit slave address followed by the read bit (high). 3. The addressed slave device asserts ACK on SDA. 4. The master receives a data byte. 5. The master asserts NO ACK on SDA. 6. The master asserts a stop condition on SDA, and the transaction ends. In the NCT7491, the receive byte protocol is used to read a single byte of data from a register whose address has previously been set by a send byte or write byte operation. This operation is illustrated in Figure 9. 1 2 S SLAVE ADDRESS 3 R A 4 DATA 5 6 A P Register Map Paging The NCT7491 register map is organized into two pages: • Page 1 contains register addresses 0x00 to 0xFF • Page 2 contains register addresses 0x100 to 0x1FF The default page on power up is page 1, so any SMBus read/writes to the NCT7491 will be to addresses in the range 0x00−0xFF. To access page 2 of the register map, bit 0 (RGMP) of register 0xFF must be set to 1. Any subsequent read/writes after that bit is set will be to addresses in the range 0x100 to 0x1FF, e.g. reading from address 0x22 when RGMP is set will read from register 0x122. Bit 0 of register 0xFF is, in effect, the MSb of the address pointer. To return to page 1, bit 0 (RGMPCL) of register 0x1FF must be cleared to 0. All register read/writes referenced in this document refer to registers on SMBus Page 1 unless stated otherwise. Analog Temperature Measurement A simple method of measuring temperature is to exploit the negative temperature coefficient of a diode connected transistor, measuring the base emitter voltage (VBE) of a transistor operated at constant current. However, this technique requires calibration to null the effect of the absolute value of VBE, which varies from device to device. The technique used in the NCT7491 measures the change in VBE when the device operates at four different currents. Figure 10 shows the input signal conditioning used to measure the output of an external temperature sensor. This figure shows the external sensor as a substrate transistor, but it can equally be a discrete transistor. If a discrete transistor is used, the collector is not grounded but is linked to the base. To prevent ground noise interfering with the measurement, the more negative terminal of the sensor is not referenced to ground, but is biased above ground by an internal diode at the D− input. C1 may be added as a noise filter (a recommended maximum value of 1000 pF). However, a better option in noisy environments is to add a filter, as described in the Noise Filtering section. To measure DVBE, the operating current through the sensor is switched among 4 currents, 2 x 2 related currents. As shown in Figure 10, N1 x I1 is a multiple of I1 and N2 x I2 is a multiple of I2. The currents through the temperature diode are switched between I and N1 x I, giving DVBE1; and then between I and N2 x I, giving DVBE2. The temperature is then calculated using the two DVBE measurements. This method cancels the effect of any series resistance on the temperature measurement. Figure 9. Single−Byte Read from a Register Alert Response Address Alert response address (ARA) is a feature of SMBus devices that allows an interrupting device to identify itself to the host when multiple devices exist on the same bus. The SMBALERT output can be used as either an interrupt output or an SMBALERT. One or more outputs can be connected to a common SMBALERT line connected to the master. If a device’s SMBALERT line goes low, the following events occur: 1. SMBALERT is pulled low. 2. The master initiates a read operation and sends the alert response address (ARA = 0001 100). This is a general call address that must not be used as a specific device address. 3. The device whose SMBALERT output is low responds to the alert response address, and the master reads its device address. The address of the device is now known and can be interrogated in the usual way. 4. If more than one device’s SMBALERT output is low, the one with the lowest device address has priority in accordance with normal SMBus arbitration. 5. Once the NCT7491 has responded to the alert response address, the master must read the status registers, and the SMBALERT is cleared only if the error condition is gone. SMBus Timeout The NCT7491 includes an SMBus timeout feature. If there is no SMBus activity for 25 ms, the NCT7491 assumes www.onsemi.com 13 NCT7491 Figure 10. Analog Temperature Measurement Method Series Resistance Cancellation ensures that the results read back from the two registers come from the same measurement. Theoretically, the temperature sensor and ADC can measure temperatures from −64°C to +127.5°C with a resolution of +0.25°C. However, this exceeds the operating temperature range of the device, so local temperature measurements outside the NCT7491 operating temperature range are not possible. • Remote1 result registers: 0x25 (MSB), 0x77 bits (2 LSb) • Local result registers: 0x26 (MSB), 0x77 bits (2 LSb) • Remote1 result registers: 0x27 (MSB), 0x77 bits (2 LSb) Parasitic resistance to the D+ and D− inputs to the NCT7491, seen in series with the remote diode, is caused by a variety of factors, including PCB track resistance and track length and internal resistance in the CPU. This series resistance appears as a temperature offset in the remote sensor’s temperature measurement. This error typically causes a 0.5 degree C offset per ohm of parasitic resistance in series with the remote diode. The NCT7491 automatically cancels the effect of this series resistance on the temperature reading, giving a more accurate result, without the need for user characterization of this resistance. The NCT7491 is designed to automatically cancel typically up to 270 W of resistance in series with the thermal diode. By using an advanced temperature measurement method, this process is transparent to the user. This feature permits resistances to be added to the sensor path to produce a filter, allowing the part to be used in noisy environments. Table 6. TWO’S COMPLEMENT FORMAT Temperature Digital Output (10−Bit) −64°C 1100 0000 00 −55°C 1100 1001 00 −40°C 1101 1000 00 −10°C 1111 0110 00 −1°C 1111 1111 00 Temperature Measurement Results The results of the Local, Remote 1 and Remote 2 temperature measurements are stored in the local (0x26), remote 1 (0x25) and remote 2 (0x27) temperature value registers in two’s complement format or Offset 64 format, depending on bit 0 if register 0x7C (1= 2’s complement, 0 = Offset 64). These results are then compared with limits programmed into the local, remote 1 and remote 2 high and low limit registers. The high, low and THERM limits for the local, remote 1 and remote 2 channels must be in the same format as the temperature reading i.e. 2’s complement or Offset 64. All the temperature measurement data for each channel is stored in two registers, one for the MSB and one for the LSB. This gives the temperature measurement resolution of 0.25°C. When reading the full external temperature value, read the LSB first. This causes the MSB to be locked (that is, the ADC does not write to it) until it is read. This feature −0.25°C 1111 1111 11 0°C 0000 0000 00 10.25°C 0000 1010 01 25°C 0001 1001 00 125°C 0111 1101 00 127.5°C 0111 1111 10 Diode Fault – 127.75 0111 1111 11 NOTE: Bold numbers denote the LSB bits from extended resolution register 0x77. www.onsemi.com 14 NCT7491 • • • • Offset 64 Format In Offset 64 mode the range of values monitored is −64°C to 191.5°C (as opposed to −64°C to +127.5°C in 2’s complement mode). To read the temperature in this format the user must subtract 64 from the value returned from the temperature register. Offset 64 mode is enabled by setting bit 0 if register 0x7C to zero. Offset Registers Offset errors can be introduced into the temperature measurements by clock noise or when the thermal diode is located away from the hot spot. To achieve the specified accuracy on this channel, these offsets must be removed. The offset value is stored as an 8−bit, twos complement value. The value in the offset register is added to, or subtracted from, the measured value of the relevant temperature. The offset register has a default value of 0°C and has no effect unless the user writes a different value to it. The resolution of the value in the offset register is determined by bit 1 of register 0x7C. If the bit is 0 then the resolution is 0.5°C. If the bit is 1 then the resolution is 1°C. • Remote1 Offset, register 0x70 • Local Offset, register 0x71 • Remote2 Offset, register 0x72 Table 7. OFFSET64 Register Code Temperature 0 −64°C 32 −32°C 64 0°C 100 36°C 255 191°C Local Low Limit register: 0x50 Local High Limit register: 0x51 Remote2 Low Limit register: 0x52 Remote2 High Limit register: 0x53 Round Robin Temperature Measurement The local and remote sensors are read in sequence in a continuous loop when monitoring is enabled (setting bit 0 of register 0x40). The user may decide which temperature channels are included in the monitoring loop using bits in register 0x13. • Setting of register 0x13 includes the local channel in the monitoring loop. • Setting of register 0x13 includes the remote1 channel in the monitoring loop. • Setting of register 0x13 includes the remote2 channel in the monitoring loop. Any channel not required in an application should be removed from the loop to reduce the overall monitoring time. Voltage channels may also be selected for the monitoring loop. See the Voltage Monitoring section for more information. Push Registers The NCT7491 allows the user to program 4 temperatures into the device that can then be used for fan control and THERM/SMBALERT functions in the same way as other temperature sources. These temperatures can be written by the system SMBus master and should be programmed as 2’s complement values. • Push0, register 0xC8 • Push1, register 0xC9 • Push2, register 0xCA • Push3, register 0xCB Push Limit Registers Temperature Averaging There are high, low and THERM limits associated with the Push channels. The same limits are applied to all 4 channels. • Push Low Limit register, 0xCF • Push High limit register, 0xCE • Push THERM Limit register, 0xD0 The number of samples over which the temperature readings (and voltage readings) are averaged is set by bits of register 0x40. The options are: • 4 samples per averaged reading, = • 8 samples per averaged reading, = • 16 samples per averaged reading, = • 32 samples per averaged reading, = Averaging can be disabled for temperature readings by setting bit of register 0x73. Push Tmin/Trange Registers The Push channels also have associated Tmin/Trange values for Automatic Fan Control. The hysteresis applied at the Tmin value can also be programmed. • Push Tmin, 0xCC • Push Trange, 0xCD bits • Push Hysteresis, 0xEB bits Temperature Limits Temperature limits can be set for each channel to detect an out of limit condition. These registers are programmed in the same format as the temperature reading, so if Offset64 mode is enabled then these registers must be programmed in that format, otherwise theay are programmed as 2’s complement. • Remote1 Low Limit register: 0x4E • Remote1 High Limit register: 0x4F PECI 3.0 Interface The PECI 3.0 interface reads thermal data from the up to 4 CPUs located at PECI addresses between 0x30 and 0x37 (the first 4 addresses populated are used), and from 1 or 2 domains per CPU. The hottest reading from the domains for each CPU is stored in the PECI temperature registers. It can www.onsemi.com 15 NCT7491 also be set to indicate that at least one CPU was detected. If any processors are detected then the PECI monitoring loop will automatically start. The Vccp pin must be connected to an input voltage for the PECI interface to function correctly. If it is not connected to the CPU supply voltage then it should be connected to the NCT7491 supply voltage, Vcc. If the system processor does not support PECI 3.0 then the PECI monitoring loop will not automatically start. In that case the user can write to the PECI registers to manually configure the interface. The register descriptions are given below. also write thermal data to the Package Configuration Space in the CPU. A PECI reading is a negative value, in degrees Celsius, which represents the offset from the thermal control circuit (TCC) activation temperature. PECI information is returned as a 16−bit 2’s complement value from which the 8−bit 2’s complement value is derived. See the Platform Environment Control Interface (PECI) Specification from Intel for more details on the PECI data format. The PECI temperature stored for each CPU is an averaged value; the averaging window is user programmable. The NCT7491 automatically detects the presence of a CPU at each of the supported addresses, and also detects the number of supported domains for each CPU. The presence of each CPU is indicated in the NCT7491 status registers. On power up, the PECI interface will become active when the voltage measured on VTT is above 0.5 V and the voltage on Vccp is above 0.5 V. The returned CPU temperature will determine the behavior of the fans on power−up. Thermal data that is collected by the NCT7491 (e.g. the DIMM temperatures) can be written to the CPU’s Package Configuration Space (PCS) over the PECI 3.0 interface. This data can be used by the CPU to modify memory operations based on the DIMM temperature. There are associated high and low limits for each PECI reading that can be programmed. The limit values take the same format as the PECI reading. Therefore, the programmed limits are not absolute temperatures but a relative offset in degrees Celcius from the TCC activation temperature. An out−of−limit event is recorded as follows: • High Limit > comparison performed • Low Limit ≤ comparison performed An out−of−limit event is recorded in the associated status register and can be used to assert the SMBALERT pin. A generic PECI 3.0 interface command structure is also available to allow an external master to issue any PECI 3.0 command in addition to the commands implemented by the NCT7491 monitoring loops. PECI Error Detection The PECI 3.0 protocol includes FCS (Frame Check Sequence) bytes to guarantee data integrity. If there is a mismatch between the data and the FCS then a status bit indicates the communication failure (COMM status bit, register 0x43 bit ). PECI 3.0 also supports processor specific error codes to indicate error conditions relating to the temperature sensor within the processor (DATA status bit, register 0x43 bit ). These codes are shown in Table 8: Table 8. DATA ERROR CODES DATA code bits , 0x43 DATA Error code Description 0x8000 General Sensor Error 0x8002 Temperature below operational range 0x8003 Temperature above operational range PECI Completion Code Each read or write operation to the CPU Package Configuration Space returns a completion code to indicate the success or failure of the operation. The completion codes supported are shown in Table 9: PECI VTT Input Table 9. COMPLETION CODES The PECI VTT voltage is used as the reference voltage for the PECI interface. This voltage must be connected to the NCT7491 in order for the PECI interface to be operational. The PECI VTT input is also monitored by the NCT7491 and has associated high and low limits to allow out−of–limit detection on the VTT channel. The valid operational voltage range for PECI VTT is 0.85 V to 1.26 V. Completion Code Command Passed, data is valid 0x80 Command timed out. Processor cannot generate required response in a timely fashion. Retry is appropriate. 0x81 Command timed out. Processor cannot allocate resources for the request. Retry is appropriate. 0x90 Unknown/Invalid/Illegal request 0x91 PECI Control hardware, firmware or associated logic error. The processor cannot process the request. PECI Startup Operation On power up of the NCT7491 the PECI VTT pin and the Vccp pin are monitored. If the voltage on both of these pins rises above 0.5 V then the NCT7491 will wait 5 ms and then automatically scan the PECI port to check for the presence of PECI 3.0 enabled processors. For any processors that are detected the PECI address, the domain count, the Tcontrol value and the Tjmax value will be read and stored in the NCT7491. The CPU count bits will be set (bits of register 0x88). The PDET bit (bit 0f register 0x37) will Description 0x40 The completion code status bit in the NCT7491 (register 0x81 bit ) indicates the result of each read/write operation. www.onsemi.com 16 NCT7491 PECI Registers PECI CPU Addresses: • PECI0 CPU Address, 0x00 • PECI1 CPU Address, 0x01 • PECI2 CPU Address, 0x02 • PECI3 CPU Address, 0x03 These are the addresses used to access each CPU on the PECI interface and are automatically populated by the NCT7491 on power up. The values can be overwritten by the user. PECI Temperature Values: • PECI0 Temperature, 0x33 • PECI1 Temperature, 0x1A • PECI2 Temperature, 0x1B • PECI3 Temperature, 0x1C These are the relative temperature values returned by the CPU. If a CPU is not populated then its associated temperature register can be written to by an external master. Data is tored in 2’s complement format. PECI Absolute Temperature Values: • PECI0_Abs Temperature, 0x04 • PECI1_Abs Temperature, 0x05 • PECI2_Abs Temperature, 0x06 • PECI3_Abs Temperature, 0x07 These are the absolute CPU temperature values. They are automatically calculated by the NCT7491 from the relative temperature and the CPU TJMAX value. See the PECI TJMAX Values section. Data is stored in unsigned format. Absolute PECI mode The user can enable Absolute PECI mode by setting bit 2 of register 0x73 (ABS/REL) which will use the value stored in the PECI absolute temperature registers for fan control, THERM behaviour and SMBALERT behaviour rather than the relative PECI values. PECI Averaging The number of samples over which the PECI master will calculate an averaged temperature reading for each CPU can be set in register 0x36, bits : • = No averaging • = Averaged over 2 samples • = Averaged over 4 samples • = Averaged over 8 samples • to are reserved The registers relating to the operation of the PECI 3.0 interface are as follows: Enabling the Interface: • PECI Monitor, 0x40 bit 4 Setting PECI Monitor to 1 enables the PECI temperature monitoring loop. This will be automatically enabled on power up if the VTT and VCCP voltages have exceeded preset thresholds and any PECI 3.0 enabled processors have been automatically detected. NOTE: The PDET bit (bit 0x37) must also be set for correct operation. Detected number of CPUs: • CPU Count, 0x88 bits • PDET, 0x37 CPU Count indicates the number of populated CPUs. CPUs are automatically detected on power up by the NCT7491 and the number found is set here. The number can be overwritten by the user and sets the number of CPUs to be included in the temperature monitoring loop. The number of CPUs is 1 to 4, and the format is as shown in Table 10. PDET is set if at least one PECI enabled processor is detected. If it is not automatically set then it must be set by the user. Table 10. CPU COUNT 0x88 CPU Count 1 2 3 4 Domain Count bits: • DOM0, 0x36 bit 3 • DOM1, 0x88 bit 5 • DOM2, 0x88 bit 4 • DOM3, 0x88 bit 3 These bits indicate the number of supported domains per CPU (0 = 1 domain, 1 = 2 domains). THE NCT7491 automatically detects these values on power up and sets the appropriate bits. They can be overwritten by the user. PECI Interval: • PECI Update Rate, 0x37 bits This determines the rate at which the PECI temperature registers are updated. PECI Offsets: • PECI0 Offset, 0x94 • PECI1 Offset, 0x95 • PECI2 Offset, 0x96 • PECI3 Offset, 0x97 Offset values can be assigned to each temperature channel by programming these registers. The value programmed should be in 2’s complement format. The resolution is 1°C. Table 11. UPDATE RATE 0x37 PECI Update Rate 1/sec 2/sec 5/sec 10/sec www.onsemi.com 17 NCT7491 The user can choose to use the relative or absolute PECI temperature values for fan control. If Absolute PECI mode is used then the maximum valid Tmin value is 175°C. For full details on the Fan Control implementation see the ‘Fan Control’ section of this document PECI Status Bits: • PECI0 limit error, 0x43 bit 0 • PECI1 limit error, 0x81 bit 3 • PECI2 limit error, 0x81 bit 4 • PECI3 limit error, 0x81 bit 5 • DATA error, 0x43 bit 1 • COMM error, 0x43 bit 2 • DATA type, 0x43 bits • PECI completion code, 0x81 bit 0 • PECI0 TCONTROL exceeded, 0x89 bit 0 • PECI1 TCONTROL exceeded, 0x89 bit 1 • PECI2 TCONTROL exceeded, 0x89 bit 2 • PECI3 TCONTROL exceeded, 0x89 bit 3 The Data Type field indicates the returned code if a DATA error is generated. Status bits in 0x43 and 0x81 can be masked by setting the corresponding mask bits in registers 0x82 and 0x83. PECI Limits: • PECI Low Limit, 0x34 • PECI High Limit, 0x35 These registers are used to set the allowable PECI temperature range. If the temperature is above the high limit or below the low limit then a status bit is set and pins configured as SMBALERT will assert. The high and low limit values are common to all PECI channels. The format depends on whether Absolute PECI mode is enabled. If it is then the limits are in unsigned format. If Absolute PECI mode is not enabled then the format is 2’s complement. PECI TCONTROL Values: • PECI0 TCONTROL , 0x3D • PECI1 TCONTROL , 0x08 • PECI2 TCONTROL , 0x09 • PECI3 TCONTROL , 0x0A These values set the fail−safe fan assertion temperature. The response of the fans is determined by the THERM configuration registers and is described in the ‘THERM Assertion’ section of this document. These values can be read from the CPU via the PECI interface or programmed directly by the user. The format depends on whether Absolute PECI mode is enabled. If it is then the limit is in unsigned format. If Absolute PECI mode is not enabled then the format is 2’s complement. PECI TJMAX Values: • PECI0 TJMAX , 0x0B • PECI1 TJMAX , 0x0C • PECI2 TJMAX , 0x0D • PECI3 TJMAX , 0x0E Each CPU has a maximum junction temperature TJMAX. These values for the populated CPUs are read via the PECI 3.0 interface by the NCT7491. They can also be over−written by the user. They are used to determine the absolute PECI temperature. These values are stored as unsigned data. PECI Fan Control: • PECI Tmin, 0x3B • PECI Trange, 0x3C bits • PWM1 Source1, 0x8A bits • PWM2 Source1, 0x8D bits • PWM3 Source1, 0x90 bits Tmin sets the turn−on temperature for any fan that is controlled by a PECI temperature. Trange sets the range over which the PWM output will increase from PWMmin to PWMmax. The PECI Tmin and PECI Trange values are common to all PECI channels. The PWMX Source registers are used to assign temperature control to a fan. The PECI assignment is done with bits in those registers. Generic PECI Command Block • • • • • • CPU Address, 0xD1 Data Write Length, 0xD2 Data Read Length, 0xD3 Data Write Buffer, 0xD4 to 0xE0 Data Read Buffer, 0xE1 to 0xE9 Generic PECI Configuration, 0xEA These registers define the generic PECI interface. An external master can populate these registers in order to execute any supported PECI 3.0 commands. The byte definitions for this block are as follows: CPU Address sets the target address of the PECI client that is to be accessed. Data Write Length sets the number of bytes to be transferred to the PECI client. This byte should include the AW FCS byte in its count. The AW FCS byte is automatically calculated and appended by the NCT7491. Data Read Length sets the number of bytes to be returned from the PECI client. Data Write Buffer is a 13 byte buffer that holds the data to be transferred to the client. The first byte of this buffer is the command code that defines the command to be executed. Data Read Buffer is a 9 byte buffer that will hold the data returned from the client. www.onsemi.com 18 NCT7491 functions. Enabling the SMBus master port overrides any GPIO1/GPIO2 configuration settings. The PECI Configuration 5 register (address 0xEA) enables the generic block and allows the command to be executed. The configuration bits are: • AW, bit 1 • PEX, bit 2 SMBus Compatible Master Registers The registers relating to the control of the SMBus compatible master interface are as follows: Enabling the SMBus Master port: • SMBus Master Enable, 0xB5 bit 0 Setting this bit configures pins 5 and 6 on the QSOP package, or pins 2 and 3 on the QFN package as the SMBus Master Port. It also enables the Thermal slave temperature monitoring loop which will gather data from the devices configured in the SMBus Master Addressing table. When this bit is 0 and pins 5 and 6 on the QSOP package, or pins 2 and 3 on the QFN package are not configured as GPIOs then the SMBus slave port is internally connected to the SMBus master port. This allows the master connected to the NCT7491 to communicate directly with devices that are on the NCT7491 master port. Setting AW to 1 indicates that the transfer is an Assured Write transaction. Setting PEX to 1 causes the NCT7491 to execute the command that has been set up in the generic command block. This bit will automatically clear when the transaction has completed. If a communication error occurs when a Generic PECI command is sent then the GCOMM status bit is set. This bit can be masked. • GCOMM, register 0x81 • GCOMM mask, register 0x83 SMBus Compatible Master Port Thermal data is gathered from temperature monitoring devices attached to the SMBus Master port on the NCT7491. This port is used to automatically read temperature data from DIMM sensors, the PCH chipset sensor, graphics thermal sensors, or any thermal sensor with an SMBus interface. Up to 8 thermal slave devices are supported on the SMBus master port. The SMBus slave address for each device is user programmable. The register address of the thermal data within the slave device is also user programmable. This is assumed to be a 1−byte address so devices with a register address range of 0x00 to 0xFF are suitable. Each slave device has associated programmable configuration bits to indicate the protocol required to communicate over the SMBus and the temperature data format returned by the slave device. Status bits will indicate if any checksum errors arise from communicating with the slave devices. The NCT7491 can be connected to the SMLINK1 port of the PCH to allow the PCH thermal data to be read. Data is automatically read from the PCH using the SMBus Block Read protocol. The device can be configured to read the DIMM temperature registers from the PCH. The SMBus master and slave ports on the NCT7491 can be connected together if required. Temperature readings returned from the thermal devices on the SMBus master port are available for use in the Automatic Fan Control algorithm. The SMBus thermal devices have associated high and low temperature limit registers to allow out−of−limit conditions to be detected. If the SMBus Master interface is disabled then the SMBus master is internally connected to the slave interface, if the pins have not been assigned to GPIO Temperature Addressing Table: • • • • • • • • • • • • • • • • Device0 Address, 0x98 Device0 Pointer, 0x99 Device1 Address, 0x9A Device1 Pointer, 0x9B Device2 Address, 0x9C Device2 Pointer, 0x9D Device3 Address, 0x9E Device3 Pointer, 0x9F Device4 Address, 0xA0 Device4 Pointer, 0xA1 Device5 Address, 0xA2 Device5 Pointer, 0xA3 Device6 Address, 0xA4 Device6 Pointer, 0xA5 Device7 Address, 0xA6 Device7 Pointer, 0xA7 The DeviceX Address register sets the 7−bit (R/W bit not included) SMBus address of the thermal sensor. The DeviceX Pointer register sets the register address of the temperature data in the thermal slave device. Device0 can be used for SMBus Block Read commands. In that case the block read command code should be written to the Device0 Pointer register. If the NCT7491 Master port is connected to the SMLINK1 port of the Intel PCH then the PCH temperature (and possibly the DIMM temperatures) can be read from this port. In that case Device0 should be reserved for the PCH temperature and Device1 to Device 4 reserved for DIMM0 to DIMM3. www.onsemi.com 19 NCT7491 The NCT7491 will not attempt to read from a device that has a Device Address byte that is set to 0. Temperature Values: • Device0 (PCH), 0xA8 • Device1 (DIMM0), 0xA9 • Device2 (DIMM1), 0xAA • Device3 (DIMM2), 0xAB • Device4 (DIMM3), 0xAC • Device5, 0xAD • Device6, 0xAE • Device7, 0xAF The results of the readings from each of the thermal slave devices are stored here. Table 15. Device3 FORMATS 0xB2 Format 00 2’s Complement 01 JEDEC SPD standard 10 Unsigned binary 11 reserved Table 16. Device4 FORMATS 0xB3 Thermal Slave Data Formats It is necessary for the NCT7491 to be configured so that the data format for each SMBus client device is known, e.g. if the data is 2’s Complement or unsigned data, or if a JEDEC standard SPD device is used so that the data can be correctly read from the device. Each SMBus device has a bit field to determine the data format for that device. The format selected for the device determines its behaviour for out−of−limit comparisons, THERM assertions and fan control operation. For Device0, if the format is set to PCH Block Read then the resulting data is stored as unsigned binary. The VR12 literal mode can be selected to allow temperature or power data be read from a VR12 controller via the PMBus. Format 00 2’s Complement 01 JEDEC SPD standard 10 Unsigned binary 11 reserved Table 17. Device5 FORMATS 0xB3 Format 00 2’s Complement 01 JEDEC SPD standard 10 Unsigned binary 11 VR12 Literal Table 18. Device6 FORMATS 0xB3 Format 00 2’s Complement 01 JEDEC SPD standard 10 Unsigned binary 11 VR12 Literal Table 12. Device0 FORMATS 0xB2 Format 00 2’s Complement 01 JEDEC SPD standard 0xB3 Format 10 Unsigned binary 00 2’s Complement 11 PCH block reads 01 JEDEC SPD standard 10 Unsigned binary 11 VR12 Literal Table 19. Device7 FORMATS Table 13. Device1 FORMATS 0xB2 Format 00 2’s Complement 01 JEDEC SPD standard 10 Unsigned binary 11 reserved SMBus Master Update Rate The interval between successive reads from an SMBus client device is determined by register 0xC7 bits : Table 20. SMBus UPDATE Table 14. Device2 FORMATS 0xB2 Format 00 2’s Complement 01 JEDEC SPD standard 10 Unsigned binary 11 reserved 0xC7 bits SMBus Update Rate 00 250 ms 01 500 ms 10 750 ms 11 1 sec Thermal Slave Limits: • SMB Slave High Limit, 0xC1 • SMB Slave Low Limit, 0xC2 www.onsemi.com 20 NCT7491 These registers are used to set the allowable Thermal slave temperature range. If the temperature is above the high limit or below the low limit then a status bit is set and pins configured as SMBALERT will assert. The high and low limit values are common to all SMBus Thermal slave readings. The low limit is programmed as a 2’s Complement value. The high limit is programmed as an unsigned value. The difference between the two formats is necessary to cover the alternate formats available for the SMBus slave devices. Thermal Slave THERM Value: • SMBus THERM Limit, 0xC3 This value sets the fail−safe THERM assertion temperature. The response of the fans is determined by the THERM configuration registers and is described in the ‘THERM Assertion’ section of this document. This value is programmed as an 8−bit unsigned value. Thermal Slave Fan Control: • SMB Device Tmin, 0xC6 • SMB Device Trange, 0xC7 bits • PWM1 Source2, 0x8B • PWM2 Source2, 0x8E • PWM3 Source2, 0x91 Tmin sets the turn−on temperature for any fan that is controlled by a Thermal slave device. Trange sets the temperature range over which the PWM output will increase from PWMmin to PWMmax. The Tmin and Trange values apply to all Thermal slave devices. SMB Tmin is programmed as an 8−bit unsigned value. The maximum valid SMBus Tmin value is 175°C. The PWMX Source registers are used to assign temperature control to a fan. For full details on the Fan Control implementation see the ‘Fan Control’ section of this document. If 0xB5 is 1 then registers 0xA9 and 0xAA are overwritten by the Remote1 temperature reading. If 0xB5 is 1 then registers 0xAB and 0xAC are overwritten by the Remote2 temperature reading. If bit 7 of 0xB5 (DIMM from PCH) is set then bits 5 and 6 have no effect. Writing DIMM temperatures to the CPUs The DIMM temperatures collected from SPD devices, from the PCH or from the analog thermal sensors can be automatically written to the CPU via PECI. To enable this function set the PWEN bit, register 0x37 . The temperatures written will be the maximum DIMM temperature for each CPU. DIMM CPU assignments: • DIMM0 CPU, 0x0F bits • DIMM1 CPU, 0x0F bits • DIMM2 CPU, 0x0F bits • DIMM3 CPU, 0x0F bits These bits set the CPU associated with each DIMM. This information is necessary in order for the PECI loop to program the maximum DIMM temperature for each CPU. Selecting DIMMs To Be Written Each DIMM register can be enabled to be written to the CPU individually. This is done in register 0x87 bits . If a DIMM is not populated then the corresponding bit in this register should be set to zero: Setting 0x87 bit to 1 includes DIMM0 in the PECI write Setting 0x87 bit to 1 includes DIMM1 in the PECI write Setting 0x87 bit to 1 includes DIMM2 in the PECI write Setting 0x87 bit to 1 includes DIMM3 in the PECI write SMBus Thermal Slave Error Response How the NCT7491 responds to errors on the SMBus master port can be configured in the following ways: • SMBus Retry Interval, 0x10 bits • PWM1 Response, 0x11 bit 5 • PWM2 Response, 0x11 bit 6 • PWM3 Response, 0x11 bit 7 SMBus Retry Interval: If an error is encountered when communicating with a Thermal slave device then the NCT7491 will attempt to carry out the command up to 3 times. These bits set the interval between the retry attempts. SMBus Master Communication Settings • Repeated Start Enable, 0xB0 bits • PEC Supported, 0xB1 bits The Repeated Start bits enable/disable the repeated start protocol for each device. The PEC Supported bits can be set if an SMBus client device supports CRC−8 PEC. If this bit is set for a client device then the NCT7491 will read the PEC byte after the data and set the corresponding bit in the PEC status register (0xB7) if the PEC byte is incorrect. Table 21. SMBUS ERROR RETRY TIMES DIMM Temperatures from PCH • Read DIMM from PCH, 0xB5 bit 7 If this bit is set to 1 then the SMBus master port will read the DIMM registers from the SMLINK1 port of the PCH and store the results in registers 0xA9 to 0xAC. If it is 0 then it will read DIMM temperatures from SMBus slave devices. 0x10 bits SMBus Retry Interval 00 1 ms 01 2 ms 10 4 ms 11 8 ms DIMM Temperatures from Remote Sensors • DIMM 0/1 from Remote1, 0xB5 bit 5 • DIMM 2/3 from Remote2, 0xB5 bit 6 If the device fails 3 consecutive read attempts then the PWMx Response bits determine the fan behaviour. www.onsemi.com 21 NCT7491 • If bit 5 of 0x11 is 1 then PWM1 will go to 100% duty will be calculated for each temperature and the highest calculated PWM value will be output. If no temperature sources are selected then the associated PWM channel defaults to manual mode. Registers for assigning zones to PWM1: • Local/Remote1/Remote2 Control, 0x8A bits • PECI Control, 0x8A, bits • SMBus Thermal Slave Control, 0x8B bits • Push Temperature Control, 0x8C bits or Max duty. If bit 5 is 0 then the error is ignored. • If bit 6 of 0x11 is 1 then PWM2 will go to 100% duty or Max duty. If bit 6 is 0 then the error is ignored. • If bit 7 of 0x11 is 1 then PWM3 will go to 100% duty or Max duty. If bit 7 is 0 then the error is ignored. Whether the PWM outputs go to 100% or Max duty is determined by bits of register 0x16. See the THERM ASSERTION section of this document for more details. Registers for assigning zones to PWM2: • Local/Remote1/Remote2 Control, 0x8D bits • PECI Control, 0x8D, bits • SMBus Thermal Slave Control, 0x8E bits • Push Temperature Control, 0x8F bits SMBus Master Status Registers • • • • • • • Bad Block read byte count, 0x81 bit 6 NACK bits, 0xB6 bits PEC error bits, 0xB7 bits SMBus Timeout bits, 0xB8 bits High/Low Limit exceeded bits, 0xB9 bits PCH Data Invalid, 0xBA bits THERM Limit exceeded, 0xBB bits Registers for assigning zones to PWM3: • Local/Remote1/Remote2 Control, 0x90 bits • PECI Control, 0x90, bits • SMBus Thermal Slave Control, 0x91 bits • Push Temperature Control, 0x92 bits For example if the user wants to control PWM1 from the hottest of the CPU temperature, PCH temperature and the Remote1 sensor then the Control Source registers would be programmed as: • 0x8A = 1 (PECI0) • 0x8A = 1 (Remote1) • 0x8B = 1 (SMBus Device 0, PCH) Bad Block Read Count will assert if the byte count returned by the block read command is insufficient to read the required temperatures. NACK bits will assert if a device does not acknowledge its SMBus address. PEC error bits will assert if the PEC byte is incorrect. SMBus Timeout bits will assert if the bus is locked. High/Low Limit bits will assert if the temperature returned is at or below the programmed low limit value. PCH Data Invalid bits will assert if the PCH returns reserved temperature codes THERM Limit bits will assert if the returned temperature is greater than the programmed THERM limit The status bits ((except THERM status) will hold their value until the registers are read through the SMBus slave port. Status bits (except THERM status) can be masked by setting the corresponding bits in registers 0xBB to 0xBF. THERM Limit status bits will automatically clear when the temperature is below the SMBus THERM limit, unless THERM hysteresis is enabled (setting bit 0 of register 0x11) in which case the temperature must drop below THERM limit − Hysteresis. Tmin/Trange Automatic Fan Control The PWM channels can be put into Tmin/Trange in the following way: • Setting bit of register 0x10 to 0 puts PWM1 in Tmin/Trange mode • Setting bit of register 0x10 to 0 puts PWM2 in Tmin/Trange mode • Setting bit of register 0x10 to 0 puts PWM3 in Tmin/Trange mode 100% PWMmax Fan Speed % Duty Cycle Automatic Fan Control There are two automatic fan control methods that can be selected in the NCT7491. Each PWM channel can be set to use the Tmin/Trange control method or to use an 8 point PWM Look−Up Table. In both cases one or more temperature channels can be assigned to control each PWM output. PWMmin Fan Off or PWMmin Assigning Temperature Zones for Automatic Fan Control These registers allow the temperature zone to be assigned to a PWM channel by setting the appropriate bit. Any combination of temperature zones can be assigned to control any fan. If more than one zone is selected then a PWM value Tmin Trange THERM Figure 11. PWM Control Curve in Tmin/Trange Mode www.onsemi.com 22 NCT7491 The control loop behaviour in Tmin/Trange mode is determined by the Tmin, PWMmin, Trange and PWMmax values. Tmin sets the temperature at which the fan turns on and PWMmin is the PWM value at Tmin. Trange sets the temperature range over which the PWM output increases from PWMmin to PWMmax. These settings set the slope of the curve. Each temperature source has its own associated Tmin/Trange values. The THERM limit associated with the temperature channel can override the fan control curve if a THERM event occurs. Minimum PWM values: • PWM1 Minimum Duty, 0x64 • PWM2 Minimum Duty, 0x65 • PWM3 Minimum Duty, 0x66 These set the lowest PWM at which the fan will run. One Lsb equals 0.39% duty cycle. Minimum PWM values only apply in Tmin/Trange mode. Maximum PWM values: • PWM1 Maximum Duty, 0x38 • PWM2 Maximum Duty, 0x39 • PWM3 Maximum Duty, 0x3A These set the maximum duty at which the fans will run. THERM assertions can be configured to over−ride this to allow the fans to go to 100% duty on a THERM event. See the THERM ASSERTION section for more details. PWM duty cycle registers: • PWM1 Duty, 0x30 • PWM2 Duty, 0x31 • PWM3 Duty, 0x32 The current duty cycle calculated by the control loop can be read in these registers. If the PWM channel is not associated with a temperature zone then that channel’s duty cycle register will become writeable (manual mode). Tmin/Trange values for all Temperature Sources: • PECI Tmin. 0x3B • PECI Trange, 0x3C bits • Remote1 Tmin, 0x67 • Remote1 Trange, 0x5F bits • Local Tmin, 0x68 • Local Trange, 0x60 bits • Remote2 Tmin, 0x69 • Remote2 Trange, 0x61 bits • SMBus slave Tmin, 0xC6 • SMBus slave Trange, 0xC7 bits • Push temperature Tmin, 0xCC • Push temperature Trange, 0xCD bits PECI Tmin PECI Tmin values must be programmed in the same format selected for PECI fan control (selected by bit 2 of register 0x73). If relative mode is selected then Tmin is programmed in 2’s Complement format. If absolute mode is selected then Tmin is programmed as an unsigned value. If Absolute PECI mode is used then the maximum valid Tmin value is 175°C. Analog Sensor Tmin The Tmin value for the analog sensors (Remote1/ Remote2/Local) must be written in the same format as the measurement registers, i.e. if they are in Offset 64 format then the Tmin value for these channels must also be written in Offset 64 format. If they are in 2’s Complement format then Tmin must be written in the range 0°C to 127°C. SMBus Tmin The SMBus Tmin value should be programmed as an unsigned 8−bit value in the range 0°C to 175°C. Push Tmin The Push register Tmin value should be programmed as a value in the range 0°C to 127°C. Tmin Hysteresis Hysteresis can be applied to the Tmin temperature to prevent the fan from turning on and off rapidly around Tmin. Each temperature has its own hysteresis value that can be applied. The range of possible values is 0°C to 15°C. Table 22. HYSTERESIS REGISTERS Temperature Hystersis Remote1 Register 0x6D Local Register 0x6D Remote2 Register 0x6E PECI Register 0x6E SMBus slave Register 0xB5 Push registers Register 0xEB PWM Behaviour below Tmin: • PWM1 on below Tmin, 0x62 bit 5 • PWM2 on below Tmin, 0x62 bit 6 • PWM3 on below Tmin, 0x62 bit 7 Setting these bits to 1 will cause the associated PWM output to remain at the minimum PWM value rather than shut off when the control temperature is below its Tmin value minus hysteresis. This setting applies to both Tmin/Trange mode and to Look−Up Table mode. Trange Values The Trange values determine the temperature range over which the fan control curve will increase from the PWM minimum value to the PWM maximum value associated with the PWM output. www.onsemi.com 23 NCT7491 The 4−bit Trange values that can be assigned for each channel are shown in the following table: Setting the PWM Frequency Each PWM output can be set to high frequency PWM mode or low frequency PWM mode. In high frequency mode the output will run at 22 kHz. In low frequency mode the frequency can be selected for each PWM output. Setting bit of register 0x5F to 1 enables high frequency for PWM1 Setting bit of register 0x60 to 1 enables high frequency for PWM2 Setting bit of register 0x61 to 1 enables high frequency for PWM3 If low frequency is enabled (if bit in 0x5F, 0x60 or 0x61 is 0) then the frequency is set as follows: Table 23. TRANGE OPTIONS Trange Bit Field Trange Value 0000 2°C 0001 2.5°C 0010 3.33°C 0011 4°C 0100 5°C 0101 6.67°C 0110 8°C 0111 10°C 1000 13.33°C 1001 16°C 1010 20°C 1011 26.67°C 1100 32°C 1101 40°C 1110 53.33°C 1111 80°C Table 25. LOW FREQUENCY PWM SELECTION Enabling Enhanced Acoustics on the PWM Outputs: • PWM1 Max Ramp Rate, 0x62 bits • PWM1 enable acoustics, 0x62 bit 3 • PWM2 Max Ramp Rate, 0x63 bits • PWM2 enable acoustics, 0x63 bit 7 • PWM3 Max Ramp Rate, 0x63 bits • PWM3 enable acoustics, 0x63 bit 3 These settings allow the user to limit the rate at which the PWM output changes whenever the fan control loop calculates a new value. As this prevents instant changes in PWM the acoustic response of the system is improved. These settings apply to both Tmin/Trange mode and to Look−Up Table mode. Settling time 000 31.75 sec 001 15.7 sec 010 10.5 sec 011 6.33 sec 100 4 sec 101 2.66 sec 110 1.28 sec 111 0.75 sec Frequency 000 11.0 Hz 001 14.7 Hz 010 22.1 Hz 011 29.4 Hz 100 35.3 Hz 101 44.1 Hz 110 58.8 Hz 111 88.2 Hz Look−Up Table Automatic Fan Control In this mode the selected PWM output is controlled by an 8−point look−up table, where a temperature and PWM value is programmed for each point. Each channel has its own control table. Any combination of temperature sources can be assigned to control the PWM output. When more than one channel is assigned to control a PWM output in this mode the channel that is the hottest will control the output. The exception to this is if PECI relative temperatures are assigned to contol a channel. Since PECI relative values are always negative they cannot be combined with other channels, since the other channels would always dominate due to the fact that they are positive values. To allow PECI readings to be combined with other readings the user can set bit 2 of register 0x73 (ABS/REL). This will cause the absolute PECI readings to be used for fan control, rather than the relative readings. • If relative PECI readings are assigned for fan control then the control temperature values for that PWM channel must be programmed in negative 2’s complement format (−128°C to 127°C). • If any temperature source other than relative PECI is assigned for fan control (including absolute PECI readings) then the control temperatures for that PWM channel must be programmed in unsigned format (0°C to 255°C). Table 24. ENHANCED ACOUSTICS TIMES Ramp Rate code 0x5F, 0x60 or 0x61 bits www.onsemi.com 24 NCT7491 • PWM values are programmed in the range 0x00 to • Setting bit of register 0x10 to 1 puts PWM2 in 0xFF. The resolution for this register is 1 lsb = 0.392%. The NCT7491 linearly interpolates between the programmed points. It is not necessary to program all 8 points. If fewer than 8 points are required then the user should program from the lowest to the highest required control temperature and set the unused control temperatures to the maximum value (0x00 if relative PECI is assigned, 0xFF if the PWM channel is controlled by any other temperature source). • Setting bit of register 0x10 to 1 puts PWM1 in Look−up Table mode Look−up Table mode • Setting bit of register 0x10 to 1 puts PWM3 in Look−up Table mode The registers used for setting the control temperatures and PWMs for each channel are on page 2 of the register map. To access these registers the user must first set bit 0 of register 0xFF to 1. This will set the register page to page 2. When programming the table is complete the user should clear bit 0 of register 0xFF to zero to return to page 1 of the register map. Table 26. PWM1 LOOK−UP TABLE VALUES PWM1 Control Points Temperature Address PWM Address PWM1 Control Point 1 0x00 (0x100) 0x01 (0x101) PWM1 Control Point 2 0x02 (0x102) 0x03 (0x103) PWM1 Control Point 3 0x04 (0x104) 0x05 (0x105) PWM1 Control Point 4 0x06 (0x106) 0x07 (0x107) PWM1 Control Point 5 0x08 (0x108) 0x09 (0x109) PWM1 Control Point 6 0x0A (0x10A) 0x0B (0x10B) PWM1 Control Point 7 0x0C (0x10C) 0x0D (0x10D) PWM1 Control Point 8 0x0E (0x10E) 0x0F (0x10F) PWM2 Control Points Temperature Address PWM Address PWM2 Control Point 1 0x10 (0x110) 0x11 (0x111) PWM2 Control Point 2 0x12 (0x112) 0x13 (0x113) PWM2 Control Point 3 0x14 (0x114) 0x15 (0x115) PWM2 Control Point 4 0x16 (0x116) 0x17 (0x117) PWM2 Control Point 5 0x18 (0x118) 0x19 (0x119) PWM2 Control Point 6 0x1A (0x11A) 0x1B (0x11B) PWM2 Control Point 7 0x1C (0x11C) 0x1D (0x11D) PWM2 Control Point 8 0x1E (0x11E) 0x1F (0x11F) PWM3 Control Points Temperature Address PWM Address PWM3 Control Point 1 0x20 (0x120) 0x21 (0x121) PWM3 Control Point 2 0x22 (0x122) 0x23 (0x123) PWM3 Control Point 3 0x24 (0x124) 0x25 (0x125) PWM3 Control Point 4 0x26 (0x126) 0x27 (0x127) PWM3 Control Point 5 0x28 (0x128) 0x29 (0x129) PWM3 Control Point 6 0x2A (0x12A) 0x2B (0x12B) PWM3 Control Point 7 0x2C (0x12C) 0x2D (0x12D) PWM3 Control Point 8 0x2E (0x12E) 0x2F (0x12F) Table 27. PWM2 LOOK−UP TABLE VALUES Table 28. PWM3 LOOK−UP TABLE VALUES www.onsemi.com 25 NCT7491 Fan Override Settings There are bits in the NCT7491 that allow the PWM outputs to be overdriven so that the outputs go to maximum speed (as programmed in the maximum PWM registers), to go to full speed (100% duty) or to be shut off. These bits will override all other fan control settings. • Setting bit 1 of register 0x11 to 1 runs the fans at the maximum programmed PWM duty cycle • Setting bit 3 of register 0x40 to 1 runs the fans at 100% duty cycle. This bit has precedence over all others. • Setting bit 0 of register 0x87 to 1 turns off PWM1 • Setting bit 1 of register 0x87 to 1 turns off PWM2 • Setting bit 2 of register 0x87 to 1 turns off PWM3 100% 5 4 PWM 3 2 1 1 0°C 2 3 4 5 6,7,8 THERM Override 255°C Temperature Setting bit 5 of register 0x40 will allow assertions on any pin configured as a THERM pin to drive the fans to 100% duty cycle or Max PWM, deending on bits of register 0x16. This will override all other fan settings. This allows an external device to bypass the register settings of the NCT7491 for fail safe operation. Figure 12. Figure 12 shows a typical look−up table curve. The temperatures are programmed as unsigned data. In this example 5 of the 8 control points are used and the remaining 3 are set to the maximum value of 255°C. This curve applies if relative PECI values are not assigned to control the PWM channel. Fan Drive The NCT7491 uses pulse width modulation (PWM) to control fan speed. This relies on varying the duty cycle (or on/off ratio) of a square wave applied to the fan to vary the fan speed. The external circuitry required to drive a fan using PWM control is extremely simple. For 4−wire fans, the PWM drive may need only a pullup resistor. In many cases the 4−wire fan PWM input has an internal pullup resistor. The NCT7491 PWM frequency can be set to a selection of low frequencies or a single high PWM frequency. The low frequency options are used for 3−wire fans, while the high frequency option is usually used with 4−wire fans. For 3−wire fans, a single N−channel MOSFET is the only drive device required. The specifications of the MOSFET depend on the maximum current required by the fan being driven and the input capacitance of the FET. Because a 10 k (or greater) resistor must be used as a PWM pullup, an FET with large input capacitance can cause the PWM output to become distorted and adversely affect the fan control range. This is a requirement only when using high frequency PWM mode. Typical notebook fans draw a nominal 170 mA, therefore, SOT devices can be used where board space is a concern. In desktops, fans typically draw 250 mA to 300 mA each. If several fans are driven in parallel from a single PWM output or drive larger server fans, the MOSFET must handle the higher current requirements. The only other stipulation is that the MOSFET should have a gate voltage drive, VGS < 3.3 V, for direct interfacing to the PWM output pin. 100% 5 4 PWM 3 2 1 1 −128°C 2 Temperature 3 4 5 6,7,8 0°C Figure 13. Figure 13 shows a typical look−up table curve that applies when relative PECI values are assigned to control the PWM channel. The temperatures are programmed as negative 2’s complement values. In this example 5 of the 8 control points are used and the remaining 3 are set to the maximum value of 0°C, as this is the maximum value for relative PECI values. www.onsemi.com 26 NCT7491 Figure 14. Driving a 3−Wire Fan Using an N−Channel MOSFET Figure 14 uses a 10 k pullup resistor for the TACH signal. This assumes that the TACH signal is an open−collector from the fan. In all cases, the TACH signal from the fan must be kept below 3.6 V maximum to prevent damaging the NCT7491. Figure 15 shows a fan drive circuit using an NPN transistor such as a general purpose MMBT2222. While these devices are inexpensive, they tend to have much lower current handling capabilities and higher on resistance than MOSFETs. When choosing a transistor, care should be taken to ensure that it meets the fan’s current requirements. Ensure that the base resistor is chosen so that the transistor is saturated when the fan is powered on. Figure 15. Driving a 3−Wire Fan Using an NPN Transistor Because the fan drive circuitry in 4−wire fans is not switched on or off, as with previous PWM driven/powered fans, the internal drive circuit is always on and uses the PWM input as a signal instead of a power supply. This enables the internal fan drive circuit to perform better than 3−wire fans, especially for high frequency applications. Figure 16 shows a typical drive circuit for 4−wire fans. www.onsemi.com 27 NCT7491 Figure 16. Driving a 4−Wire Fan Driving Two Fans from PWM3 The NCT7491 has four TACH inputs available for fan speed measurement, but only three PWM drive outputs. If a fourth fan is being used in the system, it should be driven from the PWM3 output in parallel with the third fan. Figure 17 shows how to drive two fans in parallel using a MOSFET. Because the MOSFET can handle up to 3.5 A, it is simply a matter of connecting another fan directly in parallel with the first. Care should be taken in designing drive circuits with transistors and FETs to ensure the PWM outputs are not required to source current, and that they sink less than the 5 mA maximum current specified in the data sheet. Figure 17. Interfacing Two Fans in Parallel to the PWM3 Output Using a Single N−Channel MOSFET Driving up to Three Fans from PWM3 Synchronization is not required in high frequency mode when used with 4−wire fans. Setting bit 4 of register 0x62 (SYNC) to 1 synchronizes TACH2, TACH3, and TACH4 to PWM3. TACH measurements for fans are synchronized to particular PWM channels; for example, TACH1 is synchronized to PWM1. TACH3 and TACH4 are both synchronized to PWM3, so PWM3 can drive two fans. Alternatively, PWM3 can be programmed to synchronize TACH2, TACH3, and TACH4 to the PWM3 output. This allows PWM3 to drive two or three fans. In this case, the drive circuitry looks the same, as shown in Figure 17. The SYNC bit in Register 0x62 enables this function. TACH Inputs Pins 9, 11, 12 and 14 on the QSOP package or pins 6, 8, 9 and 11 on the QFN package (when configured as TACH inputs) are high impedance inputs intended for fan speed measurement. Signal conditioning in the NCT7491 www.onsemi.com 28 NCT7491 accommodates the slow rise and fall times typical of fan tachometer outputs. The maximum input signal range is 0 V to 3.6 V, even though VCC is 3.3 V. In the event that these inputs are supplied from fan outputs that exceed 0 V to 3.6 V, either resistive attenuation of the fan signal or diode clamping must be included to keep inputs within an acceptable range. Figure 18 to Figure 20 show circuits for the most common fan TACH outputs. If the fan TACH output has a resistive pullup to VCC, it can be connected directly to the fan input, as shown in Figure 18. Figure 18. Fan with TACH Pullup to VCC TACH input but less than 3.6 V, allowing for the voltage tolerance of the zener. A value of between 3.0 V and 3.6 V is suitable. If the fan output has a resistive pullup to 12 V, or other voltage greater than 3.6 V, the fan output can be clamped with a zener diode, as shown in Figure 19. The zener diode voltage should be chosen so that it is greater than VIH of the Figure 19. Fan with TACH Pullup to Voltage > 3.6 V, for Example, 12 V Clamped with Zener Diode If the fan has a strong pullup (less than 1 k_) to 12 V or a totem−pole output, a series resistor can be added to limit the zener current, as shown in Figure 20. Figure 20. Fan with Strong TACH Pullup to >VCC or Totem−Pole Output, Clamped with Zener Diode and Resistor www.onsemi.com 29 NCT7491 TACH Measurement Overview the fan TACH output (see Figure 21) so the accumulated count is actually proportional to the fan tachometer period and inversely proportional to the fan speed. N, the number of pulses counted, is determined by the settings of the TACH pulses per revolution register (0x7B). This register contains two bits for each fan, allowing one, two (default), three, or four TACH pulses to be counted. The fan counter does not count the fan TACH output pulses directly because the fan speed could be less than 1000 RPM, and it takes several seconds to accumulate a reasonably large and accurate count. Instead, the period of the fan revolution is measured by gating an on−chip 78 kHz oscillator into the input of a 16−bit counter for N periods of Figure 21. Fan Speed Measurement Fan Speed Measurement Registers Fan TACH Limit Registers The fan tachometer registers are 16−bit values consisting of a 2−byte read from the NCT7491. • Register 0x28, TACH1 Low Byte • Register 0x29, TACH1 High Byte • Register 0x2A, TACH2 Low Byte • Register 0x2B, TACH2 High Byte • Register 0x2C, TACH3 Low Byte • Register 0x2D, TACH3 High Byte • Register 0x2E, TACH4 Low Byte • Register 0x2F, TACH4 High Byte The fan TACH limit registers are 16−bit values consisting of two bytes. • Register 0x54, TACH1 Minimum Low Byte = 0xFF default • Register 0x55, TACH1 Minimum High Byte = 0xFF default • Register 0x56, TACH2 Minimum Low Byte = 0xFF default • Register 0x57, TACH2 Minimum High Byte = 0xFF default • Register 0x58, TACH3 Minimum Low Byte = 0xFF default • Register 0x59, TACH3 Minimum High Byte = 0xFF default • Register 0x5A, TACH4 Minimum Low Byte = 0xFF default • Register 0x5B, TACH4 Minimum High Byte = 0xFF default Reading Fan Speed from the NCT7491 The measurement of fan speeds involves a 2−register read for each measurement. The low byte should be read first. This causes the high byte to be frozen until both high and low byte registers have been read, preventing erroneous TACH readings. The fan tachometer reading registers report back the number of 12.82 us period clocks (78 kHz oscillator) gated to the fan speed counter, from the rising edge of the first fan TACH pulse to the rising edge of the third fan TACH pulse (assuming two pulses per revolution are being counted). Because the device is essentially measuring the fan TACH period, the higher the count value, the slower the fan is actually running. A 16−bit fan tachometer reading of 0xFFFF indicates that either the fan has stalled or is running very slowly ( comparison). Low limits: An interrupt is generated when a value is equal to or below its low limit ( comparison). www.onsemi.com 54 NCT7491 Table 69. TEMPERATURE LIMIT REGISTERS (Note 22) Register Address R/W Description (Note 23) Power−On Default 0x4E R/W Remote 1 temperature low limit. 0x81 0x4F R/W Remote 1 temperature high limit. 0x7F 0x50 R/W Local temperature low limit. 0x81 0x51 R/W Local temperature high limit. 0x7F 0x52 R/W Remote 2 temperature low limit. 0x81 0x53 R/W Remote 2 temperature high limit. 0x7F 22. Exceeding any of these temperature limits by 1°C causes the appropriate status bit to be set in the interrupt status register. Setting the Configuration Register 1 lock bit has no effect on these registers. 23. High limits: An interrupt is generated when a value exceeds its high limit (> comparison). Low limits: An interrupt is generated when a value is equal to or below its low limit (≤ comparison). Table 70. FAN TACHOMETER LIMIT REGISTERS (Note 24) Register Address R/W Description Power−On Default 0x54 R/W TACH1 minimum low byte. 0xFF 0x55 R/W TACH1 minimum high byte 0xFF 0x56 R/W TACH2 minimum low byte. 0xFF 0x57 R/W TACH2 minimum high byte. 0xFF 0x58 R/W TACH3 minimum low byte. 0xFF 0x59 R/W TACH3 minimum high byte. 0xFF 0x5A R/W TACH4 minimum low byte. 0xFF 0x5B R/W TACH4 minimum high byte. 0xFF 24. Exceeding any of the TACH limit registers by 1 indicates that the fan is running too slowly or has stalled. The appropriate status bit is set in Interrupt Status Register 2 to indicate the fan failure. Table 71. PWM CONFIGURATION REGISTERS Register Address R/W 0x5C R/W PWM1 configuration. 0x02 0x5D R/W PWM2 configuration. 0x02 0x02 0x5E Description Power−On Default R/W PWM3 configuration. Bit Name R/W Description SPIN R/W These bits control the startup timeout for PWMx. The PWM output stays high until two valid TACH rising edges are seen from the fan. If there is not a valid TACH signal during the fan TACH measurement directly after the fan startup timeout period, then the TACH measurement reads 0xFFFF and Status Register 2 reflects the fan fault. If the TACH minimum high and low bytes contain 0xFFFF or 0x0000, then the Status Register 2 bit is not set, even if the fan has not started. 000 = No startup timeout 001 = 100 ms 010 = 250 ms (default) 011 = 400 ms 100 = 667 ms 101 = 1 sec 110 = 2 sec 111 = 4 sec Reserved INV Reserved R/W This bit inverts the PWM output. The default is 0, which corresponds to a logic high output for 100% duty cycle. Setting this bit to 1 inverts the PWM output, so 100% duty cycle corresponds to a logic low output. www.onsemi.com 55 NCT7491 Table 72. TEMP TRANGE/PWM FREQUENCY REGISTERS Register Address R/W 0x5F R/W Remote 1 TRANGE/PWM1 frequency. 0xC3 0x60 R/W Local temperature TRANGE/PWM2 frequency. 0xC3 0x61 R/W Remote 2 TRANGE/PWM3 frequency. 0xC3 Bit Name R/W FREQ R/W Description Power−On Default Description These bits control the PWMx frequency (only apply when PWM channel is in low frequency mode). 000 = 11.0 Hz 001 = 14.7 Hz 010 = 22.1 Hz 011 = 29.4 Hz (default) 100 = 35.3 Hz 101 = 44.1 Hz 110 = 58.8 Hz 111 = 88.2 Hz HF/LF R/W HF/LF = 1, High frequency PWM mode is enabled for PWMx. HF/LF = 0, Low frequency PWM mode is enabled for PWMx. RANGE R/W These bits determine the PWM duty cycle vs. the temperature range for automatic fan control. 0000 = 2°C 0001 = 2.5°C 0010 = 3.33°C 0011 = 4°C 0100 = 5°C 0101 = 6.67°C 0110 = 8°C 0111 = 10°C 1000 = 13.33°C 1001 = 16°C 1010 = 20°C 1011 = 26.67°C 1100 = 32°C (default) 1101 = 40°C 1110 = 53.33°C 1111 = 80°C www.onsemi.com 56 NCT7491 Table 73. REGISTER 0x62 − Enhanced Acoustics Register 1 (Power−On Default = 0x20) Bit Name R/W Description ACOU R/W These bits define the maximum rate of change of the PWM1 output. Instead of the fan speed jumping instantaneously to its newly determined speed, it ramps gracefully at the rate determined by these bits. This feature ultimately enhances the acoustics of the fan. Time Slot Increase Time for 0% to 100% 000 = 1 37.5 sec 001 = 2 18.8 sec 010 = 3 12.5 sec 011 = 4 7.5 sec 100 = 8 4.7 sec 101 = 12 3.1 sec 110 = 24 1.6 sec 111 = 48 0.8 sec EN1 R/W When this bit is 1, smoothing is enabled on PWM1 output. SYNC R/W SYNC = 1 synchronizes fan speed measurements on TACH2, TACH3, and TACH4 to PWM3. This allows up to three fans to be driven from PWM3 output and their speeds to be measured. SYNC = 0 synchronizes only TACH3 and TACH4 to PWM3 output. MIN1 R/W When the NCT7491 is in automatic fan control mode, this bit defines whether PWM1 is off (0% duty cycle) or at PWM1 minimum duty cycle when the controlling temperature is below its TMIN – hysteresis value. 0 = 0% duty cycle below TMIN – hysteresis. 1 = PWM1 minimum duty cycle below TMIN – hysteresis. MIN2 R/W When the NCT7491 is in automatic fan speed control mode, this bit defines whether PWM2 is off (0% duty cycle) or at PWM2 minimum duty cycle when the controlling temperature is below its TMIN – hysteresis value. 0 = 0% duty cycle below TMIN – hysteresis. 1 = PWM 2 minimum duty cycle below TMIN – hysteresis. MIN3 R/W When the NCT7491 is in automatic fan speed control mode, this bit defines whether PWM3 is off (0% duty cycle) or at PWM3 minimum duty cycle when the controlling temperature is below its TMIN – hysteresis value. 0 = 0% duty cycle below TMIN – hysteresis. 1 = PWM3 minimum duty cycle below TMIN – hysteresis. Table 74. REGISTER 0x63 − Enhanced Acoustics Register 2 (Power−On Default = 0x00) Bit Name R/W (Note 25) Description ACOU3 R/W These bits define the maximum rate of change of the PWM3 output. Instead of the fan speed jumping instantaneously to its newly determined speed, it ramps gracefully at the rate determined by these bits. This feature ultimately enhances the acoustics of the fan. EN3 R/W Time Slot Increase Time for 0% to 100% 000 = 1 37.5 sec 001 = 2 18.8 sec 010 = 3 12.5 sec 011 = 4 7.5 sec 100 = 8 4.7 sec 101 = 12 3.1 sec 110 = 24 1.6 sec 111 = 48 0.8 sec When this bit is 1, smoothing is enabled on the PWM3 output. 25. These registers become read−only when the NCT7491 is in automatic fan control mode. www.onsemi.com 57 NCT7491 Table 74. REGISTER 0x63 − Enhanced Acoustics Register 2 (Power−On Default = 0x00) Bit Name R/W (Note 25) Description ACOU2 R/W These bits define the maximum rate of change of the PWM2 output. Instead of the fan speed jumping instantaneously to its newly determined speed, it ramps gracefully at the rate determined by these bits. This feature ultimately enhances the acoustics of the fan. EN2 R/W Time Slot Increase Time for 0% to 100% 000 = 1 37.5 sec 001 = 2 18.8 sec 010 = 3 12.5 sec 011 = 4 7.5 sec 100 = 8 4.7 sec 101 = 12 3.1 sec 110 = 24 1.6 sec 111 = 48 0.8 sec When this bit is 1, smoothing is enabled on the PWM2 output. 25. These registers become read−only when the NCT7491 is in automatic fan control mode. Table 75. PWM MINIMUM DUTY CYCLE REGISTERS Register Address R/W (Note 26) 0x64 R/W PWM1 minimum duty cycle. 0x80 (50% duty cycle) 0x65 R/W PWM2 minimum duty cycle. 0x80 (50% duty cycle) 0x66 R/W PWM3 minimum duty cycle. 0x80 (50% duty cycle) Bit Name R/W (Note 26) PWM duty cycle R/W Description Power−On Default Description These bits define the PWMMIN duty cycle for PWMx. 0x00 = 0% duty cycle (fan off). 0x40 = 25% duty cycle. 0x80 = 50% duty cycle. 0xFF = 100% duty cycle (fan full speed). 26. These registers become read−only when the NCT7491 is in automatic fan control mode. Table 76. TMIN REGISTERS (Note 27) Register Address R/W Description Power−On Default 0x67 R/W Remote 1 Temperature TMIN. 0x5A (90°C) 0x68 R/W Local Temperature TMIN. 0x5A (90°C) 0x69 R/W Remote 2 Temperature TMIN. 0x5A (90°C) 27. These are the TMIN registers for each temperature channel. When the temperature measured exceeds TMIN, the appropriate fan runs at minimum speed and increases with temperature according to TRANGE. Table 77. THERM LIMIT REGISTERS (Note 28) Register Address R/W Description Power−On Default 0x6A R/W Remote 1 THERM limit. 0x64 (100°C) 0x6B R/W Local THERM limit. 0x64 (100°C) 0x6C R/W Remote 2 THERM limit. 0x64 (100°C) 28. If any temperature measured exceeds its THERM limit, all PWM outputs drive their fans at 100% duty cycle. This is a fail−safe mechanism incorporated to cool the system in the event of a critical over temperature. It also ensures some level of cooling in the event that software or hardware locks up. If set to 0x80, this feature is disabled. The PWM output remains at 100% until the temperature drops below THERM limit − hysteresis. If the THERM pin is programmed as an output, exceeding these limits by 0.25°C can cause the THERM pin to assert low as an output. www.onsemi.com 58 NCT7491 Table 78. TEMPERATURE/TMIN HYSTERESIS REGISTERS (Note 29) Register Address R/W Description Power−On Default 0x6D R/W HYSL Local Temperature hysteresis. 0°C to 15°C of hysteresis can be applied to the Local temperature AFC control loops. HYSR1 Remote 1 Temperature hysteresis. 0°C to 15°C of hysteresis can be applied to the Remote 1 Temperature AFC control loops. 0x6E R/W HYSP PECI Temperature hysteresis. 0°C to 15°C of hysteresis can be applied to the PECI AFC control loops. HYSR2 Remote 2 Temperature hysteresis. 0°C to 15°C of hysteresis can be applied to the Local Temperature AFC control loops. Remote 1 and Local Temperature hysteresis. PECI and Remote 2 Temperature hysteresis. 0x44 0x44 29. Each 4−bit value controls the amount of temperature hysteresis applied to a particular temperature channel. Once the temperature for that channel falls below its TMIN value, the fan remains running at PWMMIN duty cycle until the temperature = TMIN – hysteresis. Up to 15°C of hysteresis can be assigned to any temperature channel. The hysteresis value chosen also applies to that temperature channel, if its THERM limit is exceeded. The PWM output being controlled goes to 100%, if the THERM limit is exceeded and remains at 100% until the temperature drops below THERM – hysteresis. For acoustic reasons, it is recommended that the hysteresis value not be programmed less than 4°C. Setting the hysteresis value lower than 4°C causes the fan to switch on and off regularly when the temperature is close to TMIN. Table 79. REGISTER 0x6F − XNOR Tree Test Enable (Power−On Default = 0x00) Register Address R/W (Note 30) XEN Reserved Description If the XEN bit is set to 1, the device enters the XNOR tree test mode. Clearing the bit removes the device from the XNOR tree test mode. Unused. Do not write to these bits. 30. This register becomes read−only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect. Table 80. REMOTE 1 TEMPERATURE OFFSET (Note 31) Register Address R/W (Note 31) Description 0x70 R/W Remote 1 temperature offset. R/W Allows a temperature offset to be automatically applied to the remote temperature 1 channel measurement. Bit 1 of 0x7C (Configuration Register 5) determines the range and resolution of this register. Power−On Default 0x00 31. This register becomes read−only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect. Table 81. LOCAL TEMPERATURE OFFSET (Note 32) Register Address R/W (Note 32) Description 0x71 R/W Local temperature offset. R/W Allows a temperature offset to be automatically applied to the local temperature measurement. Bit 1 of 0x7C (Configuration Register 5) determines the range and resolution of this register. Power−On Default 0x00 32. This register becomes read−only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect. Table 82. REMOTE 2 TEMPERATURE OFFSET (Note 33) Description Register Address R/W (Note 33) 0x72 R/W Remote 2 temperature offset. R/W Allows a temperature offset to be automatically applied to the remote temperature 2 channel measurement. Bit 1 of 0x7C (Configuration Register 5) determines the range and resolution of this register. Power−On Default 0x00 33. This register becomes read−only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect. www.onsemi.com 59 NCT7491 Table 83. REGISTER 0x73 − Configuration Register 2 (Power−On Default = 0x00) (Note 34) Bit Name R/W (Note 34) Description 0 Reserved R 1 Reserved R 2 ABS/REL R/W 0 = PECI uses relative values for fan control 1 = PECI uses absolute value for fan control 3 VAVG R/W VAVG = 1 indicates that averaging on the voltage measurements is turned off. This allows measurements on each channel to be made much faster. 4 TAVG R/W TAVG = 1 indicates that averaging on the temperature measurements is turned off. This allows measurements on each channel to be made much faster. FQ R/W Sets the fault queue length: = 1 event = 2 events = 3 events = 4 events 7 Shutdown R/W 34. This register becomes read−only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect. Table 84. REGISTER 0x74 − Interrupt Mask Register 1 (Power−On Default = 0x00) Bit Name R/W 0 2.5 V R/W 2.5 V = 1, masks SMBALERT for out−of−limit conditions on the 2.5 V channel. 1 VCCP R/W VCCP = 1 masks SMBALERT for out−of−limit conditions on the VCCP channel. 2 VCC R/W VCC = 1 masks SMBALERT for out−of−limit conditions on the VCC channel. 3 5V R/W 5 V = 1 masks SMBALERT for out−of−limit conditions on the 5 V channel. 4 RIT R/W RIT = 1 masks SMBALERT for out−of−limit conditions on the Remote 1 Temperature channel. 5 LT R/W LT = 1 masks SMBALERT for out−of−limit conditions on the Local Temperature channel. 6 R2T R/W R2T = 1 masks SMBALERT for out−of−limit conditions on the Remote 2 Temperature channel. 7 R Description Reserved Table 85. REGISTER 0x75 − Interrupt Mask Register 2 (Power−On Default = 0x00) Bit Name R/W 0 12 V R/W 2 FAN1 R/W FAN1 = 1 masks SMBALERT for a Fan 1 fault. 3 FAN2 R/W FAN2 = 1 masks SMBALERT for a Fan 2 fault. 4 FAN3 R/W FAN3 = 1 masks SMBALERT for a Fan 3 fault. 5 FAN4 R/W FAN4 = 1 masks SMBALERT for a Fan 4 fault. 6 D1 R/W D1 = 1 masks SMBALERT for a diode open or short on a Remote 1 channel. 7 D2 R/W D2 = 1 masks SMBALERT for a diode open or short on a Remote 2 channel. 1 R Description 12 V = 1, masks SMBALERT for out−of−limit conditions on the 12 V channel. Reserved Table 86. REGISTER 0x76 − Extended Resolution Register 1 (Note 35) (Power−On Default = 0x00) Bit Name R/W Description 2.5 V R 2.5 V LSBs. Holds the 2 LSBs of the 10−bit 2.5 V measurement. VCCP R VCCP LSBs. Holds the 2 LSBs of the 10−bit VCCP measurement. VCC R VCC LSBs. Holds the 2 LSBs of the 10−bit VCC measurement. 5V R 5 V LSBs. Holds the 2 LSBs of the 10−bit 5 V measurement. 35. If this register is read, this register and the registers holding the MSB of each reading are frozen until read. www.onsemi.com 60 NCT7491 Table 87. REGISTER 0x77 − Extended Resolution Register 2 (Note 36) (Power−On Default = 0x00) Bit Name R/W Description 12 V R 12 V LSBs. Holds the 2 LSBs of the 10−bit 12 V measurement. TDM1 R Remote 1 Temperature LSBs. Holds the 2 LSBs of the 10−bit Remote 1 temperature measurement. LTMP R Local Temperature LSBs. Holds the 2 LSBs of the 10−bit local temperature measurement. TDM2 R Remote 2 Temperature LSBs. Holds the 2 LSBs of the 10−bit Remote 2 temperature measurement. 36. If this register is read, this register and the registers holding the MSB of each reading are frozen until read. Table 88. REGISTER 0x78 − Configuration Register 3 (Power−On Default = 0x00) Bit Name R/W (Note 37) ALERT R/W ALERT = 1, Pin 10 on the QSOP package, Pin 7 on the QFN package (PWM2/SMBALERT) is configured as an SMBALERT interrupt output to indicate out−of−limit error conditions. ALERT = 0, Pin 10 on the QSOP package, Pin 7 on the QFN package (PWM2/SMBALERT ) is configured as the PWM2 output. THERM / 2.5 V R/W THERM = 1 enables THERM functionality on Pin 22 on the QSOP package, Pin 19 on the QFN package Reserved R FAST R/W FAST = 1 enables fast TACH measurements on all channels. This increases the TACH measurement rate from once per second to once every 250 ms (4 x). DC1 R/W DC1 = 1 enables TACH measurements to be continuously made on TACH1. Fans must be driven by dc. Setting this bit prevents pulse stretching because it is not required for dc−driven motors. DC2 R/W DC2 = 1 enables TACH measurements to be continuously made on TACH2. Fans must be driven by dc. Setting this bit prevents pulse stretching because it is not required for dc−driven motors. DC3 R/W DC3 = 1 enables TACH measurements to be continuously made on TACH3. Setting this bit prevents pulse stretching because it is not required for dc−driven motors. DC4 R/W DC4 = 1 enables TACH measurements to be continuously made on TACH4. Setting this bit prevents pulse stretching because it is not required for dc−driven motors. Description 37. Bits of this register become read−only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to bits have no effect. Table 89. REGISTER 0x79 − THERM Timer Value Register (Power−On Default = 0x00) Bit Name R/W Description TMR R Times how long THERM input is asserted. These seven bits read zero until the THERM assertion time exceeds 45.52 ms. ASRT/ TMR0 R This bit is set high on the assertion of the THERM input and is cleared on read. If the THERM assertion time exceeds 45.52 ms, this bit is set and becomes the LSB of the 8−bit TMR reading. This allows THERM assertion times from 45.52 ms to 5.82 sec to be reported back with a resolution of 22.76 ms. Table 90. REGISTER 0x7A − THERM Timer Limit Register (Power−On Default = 0xFF) Bit Name R/W Description LIMT R/W Sets maximum THERM assertion length allowed before an interrupt is generated. This is an 8−bit limit with a resolution of 22.76 ms allowing THERM assertion limits of 45.52 ms to 5.82 s to be programmed. If the THERM assertion time exceeds this limit, Bit 5 (F4P) of Interrupt Status Register 2 (Reg. 0x42) is set. If the limit value is 0x00, an interrupt is generated immediately on the assertion of the THERM input. If THERM is configured as an output the THERM timer limit should be set to 0xFF to avoid unwanted alerts from being generated. www.onsemi.com 61 NCT7491 Table 91. REGISTER 0x7B − TACH Pulses per Revolution Register (Power−On Default = 0x55) Bit Name R/W FAN1 R/W Description Sets number of pulses to be counted when measuring Fan 1 speed. Can be used to determine fan pulses per revolution for unknown fan type. Pulses Counted 00 = 1 01 = 2 (default) 10 = 3 11 = 4 FAN2 R/W Sets number of pulses to be counted when measuring Fan 2 speed. Can be used to determine fan pulses per revolution for unknown fan type. Pulses Counted 00 = 1 01 = 2 (default) 10 = 3 11 = 4 FAN3 R/W Sets number of pulses to be counted when measuring Fan 3 speed. Can be used to determine fan pulses per revolution for unknown fan type. Pulses Counted 00 = 1 01 = 2 (default) 10 = 3 11 = 4 FAN4 R/W Sets number of pulses to be counted when measuring Fan 4 speed. Can be used to determine fan pulses per revolution for unknown fan type. Pulses Counted 00 = 1 01 = 2 (default) 10 = 3 11 = 4 Table 92. REGISTER 0x7C − Configuration Register 5 (Power−On Default = 0x05) Bit Name R/W (Note 38) 2sC R/W 2sC = 1 sets the temperature range to the twos complement temperature range. 2sC = 0 changes the temperature range to the offset 64 temperature range. When this bit is changed, the NCT7491 interprets all relevant temperature register values as defined by this bit. TempOffset R/W TempOffset = 0 sets offset range to −63C to +64C with 0.5°C resolution. TempOffset = 1 sets offset range to −63°C to +127°C with 1°C resolution. These settings apply to registers 0x70, 0x71, and 0x72 (Remote 1, Internal and Remote2 Temperature offset registers. Note: PECI offset is always 1°C resolution.) Pin19 Function R/W 00 = Pin 19 is SMBALERT 01 = Pin 19 is THERM 10 = Pin 19 is GPIO3 11 = reserved Note: Pin 19 refers to the QSOP package. The equivalent pin on the QFN package is pin 16. Description 38. This register becomes read−only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect. www.onsemi.com 62 NCT7491 Table 92. REGISTER 0x7C − Configuration Register 5 (Power−On Default = 0x05) R/W (Note 38) Bit Name Description PECI TCONTROL R/W PECI = 1 enables THERM assertions when the PECI temperature read is higher than the PECI TCONTROL limit and the THERM pin is bidirectional. If THERM is configured as an output the THERM timer limit (register 0x7A) should be set to 0xFF to avoid unwanted alerts from being generated. PECI = 0 indicates that the THERM pin is configured as a timer input only. Can also be disabled by writing −128°C to the relevant PECI TCONTROL limit register. R1 THERM R/W R1 = 1 enables THERM assertions when the Remote 1 temperature read is higher than the Remote 1 THERM limit and the THERM pin is bidirectional. If THERM is configured as an output the THERM timer limit (register 0x7A) should be set to 0xFF to avoid unwanted alerts from being generated. R1 = 0 indicatesthat the THERM pin is configured as a timer input only. can also be disabled by writing one of the below values to the Remote 1 THERM limit register (0x6A): Writing −64°C in offset 64 mode. Writing −128°C in twos complement mode. Local THERM R/W Local = 1 enables THERM assertions when the Local temperature read is higher than the Local THERM limit and the THERM pin is bidirectional. If THERM is configured as an output the THERM timer limit (register 0x7A) should be set to 0xFF to avoid unwanted alerts from being generated. can also be disabled by writing one of the below values to the Remote 1 THERM limit register (0x6B): Writing −64°C in offset 64 mode. Writing −128°C in twos complement mode. R2 THERM R/W R2 = 1 enables THERM assertions when the Remote 2 temperature read is higher than the Remote 2 THERM limit and the THERM pin is bidirectional. If THERM is configured as an output the THERM timer limit (register 0x7A) should be set to 0xFF to avoid unwanted alerts from being generated. can also be disabled by writing one of the below values to the Remote 1 THERM limit register (0x6C): Writing −64°C in offset 64 mode. Writing −128°C in twos complement mode. 38. This register becomes read−only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect. Table 93. REGISTER 0x7D − Configuration Register 4 (Power−On Default = 0x00) Bit Name R/W (Note 39) PIN14FUNC R/W These bits set the functionality of Pin 14: 00 = TACH4 (default) 01 = THERM 10 = SMBALERT 11 = RESERVED Note: Pin 14 refers to the QSOP package. The equivalent pin on the QFN package is pin 11. THERM Disable R/W THERM Disable = 0 enables THERM overtemperature output assuming THERM is correctly configured (registers 0x78, 0x7C, 0x7D). THERM Disable = 1 disables THERM overtemperature output on all channels. THERM can also be disabled on any channel by: Writing −64°C to the appropriate THERM temperature limit in offset 64 mode. Writing −128°C to the appropriate THERM temperature limit in twos complement mode. BpAtt Vtt R/W Bypass Vtt attenuator. When set, the measurement scale for this channel changes from 0 V (0x00) to 2 V (0xFF). BpAtt2.5 V R/W Bypass 2.5 V attenuator. When set, the measurement scale for this channel changes from 0 V (0x00) to 2 V (0xFF). BpAttVCCP R/W Bypass VCCP attenuator. When set, the measurement scale for this channel changes from 0 V (0x00) to 2 V (0xFF). BpAtt5 V R/W Bypass 5 V attenuator. When set, the measurement scale for this channel changes from 0 V (0x00) to 2 V (0xFF). BpAtt12 V R/W Bypass 12 V attenuator. When set, the measurement scale for this channel changes from 0 V (0x00) to 2 V (0xFF). Description 39. This register becomes read−only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect. www.onsemi.com 63 NCT7491 Table 94. REGISTER 0x7E − Interrupt Status 5 (Power−On Default = 0x00) Bit Name R/W Description PUSH0 R Logic 1 indicates ALERT assertion for Push0 temperature PUSH1 R Logic 1 indicates ALERT assertion for Push1 temperature PUSH2 R Logic 1 indicates ALERT assertion for Push2 temperature PUSH3 R Logic 1 indicates ALERT assertion for Push3 temperature OVT_P0 R Logic 1 indicates THERM assertion for Push0 temperature OVT_P1 R Logic 1 indicates THERM assertion for Push1 temperature OVT_P2 R Logic 1 indicates THERM assertion for Push2 temperature OVT_P3 R Logic 1 indicates THERM assertion for Push3 temperature Table 95. REGISTER 0x7F − Interrupt Mask 5 (Power−On Default = 0x00) Bit Name R/W Description PUSH0 R/W Logic 1 masks PUSH0 ALERT assertions PUSH1 R/W Logic 1 masks PUSH1 ALERT assertions PUSH2 R/W Logic 1 masks PUSH2 ALERT assertions PUSH3 R/W Logic 1 masks PUSH3 ALERT assertions Reserved R Reserved Reserved R Reserved Reserved R Reserved Reserved R Reserved Table 96. REGISTER 0x80 − GPIO Register (Power−On Default = 0xCE ) Bit Name R/W Description RES RESERVED GPEN GPIO2 R/W If GPIO2 is set to input, this register reflects the state of the pin. If GPIO2 is configured as an output, writing to this register asserts the output high or low depending on the polarity. GPIO1 R/W If GPIO1 is set to input, this register reflects the state of the pin. If GPIO1 is configured as an output, writing to this register asserts the output high or low depending on the polarity. GPIO2 POL R/W GPIO2 polarity bit. Set to 0 for active low. Set to1 for active high. GPIO1 POL R/W GPIO1 polarity bit. Set to 0 for active low. Set to1 for active high. GPIO2 DIR R/W GPIO2 direction bit. Set to 1 for GPIO2 to act as an input, set to 0 for GPIO2 to act as an output. GPIO1 DIR R/W GPIO1 direction bit. Set to 1 for GPIO1 to act as an input, set to 0 for GPIO1 to act as an output. 1= GPIO1 enabled on pin 5, GPIO2 enabled on pin 6 0 = GPIO1 and GPIO2 are disabled This bit only has effect if the SMBus master port is disabled (0xB5 =0) Table 97. REGISTER 0x81 − Interrupt Status Register 4 (Power−On Default = 0x00) Bit Name R/W Description PCC R PECI Completion code interrupt TTS R Logic 1 indicates that the THERM Timer limit has been exceeded. GCOMM R Logic 1 indicates a COMM error resulting from a Generic PECI instruction PECI1 R A logic 1 indicates that the PECI high or low limit has been exceeded by the PECI1 value. PECI2 R A logic 1 indicates that the PECI high or low limit has been exceeded by the PECI2 value. PECI3 R A logic 1 indicates that the PECI high or low limit has been exceeded by the PECI3 value. www.onsemi.com 64 NCT7491 Table 97. REGISTER 0x81 − Interrupt Status Register 4 (Power−On Default = 0x00) Bit Name R/W Description SMBCNT R Logic 1 indicates that the byte count returned by the SMBus Master Block Read is too low. If the PCH temperature only is required then the returned byte count should be 2 or greater. If DIMM temperatures are being read from the PCH then the returned byte count should be 9 or greater. VTT R A logic 1 indicates that the VTT high or low limit has been exceeded. This bit is cleared on a read of the status register only if the error condition has subsided. Table 98. REGISTER 0x82 − Interrupt Mask Register 3 (Power−On Default = 0x00) Bit Name R/W PECI0 R/W A logic 1 masks SMBALERT assertions for out−of−limit conditions on PECI0. DATA R/W A logic 1 masks SMBALERT assertions for PECI Data errors. This also disables the fan over−ride function for PECI errors. COMM R/W A logic 1 masks SMBALERT assertions for PECI communications errors. This also disables the fan over−ride function for PECI errors. OVT R/W OVT = 1 masks SMBALERT for over temperature THERM conditions. RES R/W Reserved R Reserved NOTE: Description If the mask bits in register 0x82 are set it is also necessary to set the OOL mask bit in register 0x75 to ensure the SMBALERT output is not asserted. Table 99. REGISTER 0x83 − Interrupt Mask Register 4 (Power−On Default = 0x00) Bit Name R/W PCC R/W Logic 1 masks ALERT assertions for PECI completion codes. TTS R/W Logic 1 masks assertions for THERM Timer status bit GCOMM R/W Logic 1 masks the GCOMM PECI status bit PECI1 R/W A logic 1 masks ALERT assertions for out−of−limit conditions on PECI1. PECI2 R/W A logic 1 masks ALERT assertions for out−of−limit conditions on PECI2. PECI3 R/W A logic 1 masks ALERT assertions for out−of−limit conditions on PECI3. SMBCNT R/W Logic 1 masks ALERT assertions for incorrect byte count values returned by the Block Read command VTT R/W A logic 1 masks ALERT assertions for out−of−limit conditions on VTT. NOTE: Description If the mask bits in register 0x83 are set it is also necessary to set the OOL mask bit in register 0x82 to ensure the SMBALERT output is not asserted. Table 100. VTT LOW LIMIT REGISTER Register Address R/W Description Power−On Default 0x84 R/W VTT Low Limit 0x00 Table 101. REGISTER 0x85 − GPIO Config2 (Power−On Default = 0x80) Bit Name R/W Description Reserved GPIO3 R/W If GPIO3 is set to input, this bit reflects the state of the pin. If GPIO3 is configured as an output, writing to this register asserts the output high or low depending on the polarity. GPIO3 POL R/W GPIO3 polarity bit. Set to 0 for active low. Set to1 for active high. GPIO3 DIR R/W GPIO3 direction bit. Set to 1 for GPIO3 to act as an input, set to 0 for GPIO3 to act as an output, OOL must also be masked. Table 102. VTT HIGH LIMIT REGISTER Register Address R/W Description Power−On Default 0x86 R/W VTT High Limit 0xFF www.onsemi.com 65 NCT7491 Table 103. REGISTER 0x87 − Configuration 9 (Power−On Default = 0x00) Bit Name R/W Description PWM1OFF R/W 1= Disables PWM1 PWM2OFF R/W 1= Disables PWM2 PWM3OFF R/W 1 = Disables PWM3 Reserved R D0V R/W 1 = DIMM0 is populated, must be set to enable DIMM0 temperature to be written to CPU D1V R/W 1 = DIMM1 is populated, must be set to enable DIMM1 temperature to be written to CPU D2V R/W 1 = DIMM2 is populated, must be set to enable DIMM2 temperature to be written to CPU D3V R/W 1 = DIMM3 is populated, must be set to enable DIMM3 temperature to be written to CPU Table 104. REGISTER 0x88 − PECI Configuration Register 2 (Power−On Default = 0x00) Bit Name R/W Description RES R DOM3 R/W RESERVED CPU Domain Count information. Set to 0 indicates that CPU 4 associated with the PECI3 reading has a single domain (Default). Set to 1 indicates that the system CPU4 contains two domains. DOM2 R/W CPU Domain Count information. Set to 0 indicates that CPU 3 associated with the PECI2 reading has a single domain (Default). Set to 1 indicates that the system CPU3 contains two domains. DOM1 R/W CPU Domain Count information. Set to 0 indicates that CPU 2 associated with the PECI1 reading has a single domain (Default). Set to 1 indicates that the system CPU2 contains two domains. #CPU R/W CPU Count. These bits indicate the number of CPU’s in the system. That will provide PECI thermal information to the NCT7491. 00 = 1 CPU 01 = 2 CPUs 10 = 3 CPUs 11 = 4 CPUs Table 105. REGISTER 0x89 − Interrupt Status 7 (Power−On Default = 0x00) Bit Name R/W Description OVT0 R 1 = PECI0 Tcontrol exceeded OVT1 R 1 = PECI1 Tcontrol exceeded OVT2 R 1 = PECI2 Tcontrol exceeded OVT3 R 1 = PECI3 Tcontrol exceeded OVT_R1 R 1 = Remote1 THERM exceeded OVT_LOC R 1 = Local THERM exceeded OVT_R2 R 1 = Remote2 THERM exceeded OOL11 R 1 indicates an out of limit condition in register 0xBB Table 106. REGISTER 0x8A − PWM1 Source Control 1 (Power−On Default = 0x08) Bit Name R/W Description LOC R/W Logic 1 enables Local temperature to control PWM1 in automatic fan control loop REM1 R/W Logic 1 enables Remote1 temperature to control PWM1 in automatic fan control loop REM2 R/W Logic 1 enables Remote2 temperature to control PWM1 in automatic fan control loop PEC0 R/W Logic 1 enables PECI0 temperature to control PWM1 in automatic fan control loop PEC1 R/W Logic 1 enables PECI1 temperature to control PWM1 in automatic fan control loop PEC2 R/W Logic 1 enables PECI2 temperature to control PWM1 in automatic fan control loop PEC3 R/W Logic 1 enables PECI3 temperature to control PWM1 in automatic fan control loop Reserved www.onsemi.com 66 NCT7491 Table 107. REGISTER 0x8B − PWM1 Source Control 2 (Power−On Default = 0x00) Bit Name R/W Description SMB0 R/W Logic 1 enables SMBus Slave Device 0 to control PWM1 in automatic fan control loop SMB1 R/W Logic 1 enables SMBus Slave Device 1 to control PWM1 in automatic fan control loop SMB2 R/W Logic 1 enables SMBus Slave Device 2 to control PWM1 in automatic fan control loop SMB3 R/W Logic 1 enables SMBus Slave Device 3 to control PWM1 in automatic fan control loop SMB4 R/W Logic 1 enables SMBus Slave Device 4 to control PWM1 in automatic fan control loop SMB5 R/W Logic 1 enables SMBus Slave Device 5 to control PWM1 in automatic fan control loop SMB6 R/W Logic 1 enables SMBus Slave Device 6 to control PWM1 in automatic fan control loop SMB7 R/W Logic 1 enables SMBus Slave Device 7 to control PWM1 in automatic fan control loop Table 108. REGISTER 0x8C − PWM1 Source Control 3 (Power−On Default = 0x00) Bit Name R/W Description PUSH0 R/W Logic 1 enables Externally written temperature 0 to control PWM1 in automatic fan control loop PUSH1 R/W Logic 1 enables Externally written temperature 1 to control PWM1 in automatic fan control loop PUSH2 R/W Logic 1 enables Externally written temperature 2 to control PWM1 in automatic fan control loop PUSH3 R/W Logic 1 enables Externally written temperature 3 to control PWM1 in automatic fan control loop Reserved Reserved Reserved Reserved Table 109. REGISTER 0x8D − PWM2 Source Control 1 (Power−On Default = 0x00) Bit Name R/W Description LOC R/W Logic 1 enables Local temperature to control PWM2 in automatic fan control loop REM1 R/W Logic 1 enables Remote1 temperature to control PWM2 in automatic fan control loop REM2 R/W Logic 1 enables Remote2 temperature to control PWM2 in automatic fan control loop PEC0 R/W Logic 1 enables PECI0 temperature to control PWM2 in automatic fan control loop PEC1 R/W Logic 1 enables PECI1 temperature to control PWM2 in automatic fan control loop PEC2 R/W Logic 1 enables PECI2 temperature to control PWM2 in automatic fan control loop PEC3 R/W Logic 1 enables PECI3 temperature to control PWM2 in automatic fan control loop Reserved Table 110. REGISTER 0x8E − PWM2 Source Control 2 (Power−On Default = 0x00) Bit Name R/W Description SMB0 R/W Logic 1 enables SMBus Slave Device 0 to control PWM2 in automatic fan control loop SMB1 R/W Logic 1 enables SMBus Slave Device 1 to control PWM2 in automatic fan control loop SMB2 R/W Logic 1 enables SMBus Slave Device 2 to control PWM2 in automatic fan control loop SMB3 R/W Logic 1 enables SMBus Slave Device 3 to control PWM2 in automatic fan control loop SMB4 R/W Logic 1 enables SMBus Slave Device 4 to control PWM2 in automatic fan control loop SMB5 R/W Logic 1 enables SMBus Slave Device 5 to control PWM2 in automatic fan control loop SMB6 R/W Logic 1 enables SMBus Slave Device 6 to control PWM2 in automatic fan control loop SMB7 R/W Logic 1 enables SMBus Slave Device 7 to control PWM2 in automatic fan control loop www.onsemi.com 67 NCT7491 Table 111. REGISTER 0x8F − PWM2 Source Control 3 (Power−On Default = 0x00) Bit Name R/W Description PUSH0 R/W Logic 1 enables Externally written temperature 0 to control PWM2 in automatic fan control loop PUSH1 R/W Logic 1 enables Externally written temperature 1 to control PWM2 in automatic fan control loop PUSH2 R/W Logic 1 enables Externally written temperature 2 to control PWM2 in automatic fan control loop PUSH3 R/W Logic 1 enables Externally written temperature 3 to control PWM2 in automatic fan control loop Reserved Reserved Reserved Reserved Table 112. REGISTER 0x90 − PWM3 Source Control 1 (Power−On Default = 0x00) Bit Name R/W Description LOC R/W Logic 1 enables Local temperature to control PWM3 in automatic fan control loop REM1 R/W Logic 1 enables Remote1 temperature to control PWM3 in automatic fan control loop REM2 R/W Logic 1 enables Remote2 temperature to control PWM3 in automatic fan control loop PEC0 R/W Logic 1 enables PECI0 temperature to control PWM3 in automatic fan control loop PEC1 R/W Logic 1 enables PECI1 temperature to control PWM3 in automatic fan control loop PEC2 R/W Logic 1 enables PECI2 temperature to control PWM3 in automatic fan control loop PEC3 R/W Logic 1 enables PECI3 temperature to control PWM3 in automatic fan control loop Reserved Table 113. REGISTER 0x91 − PWM3 Source Control 2 (Power−On Default = 0x00) Bit Name R/W Description SMB0 R/W Logic 1 enables SMBus Slave Device 0 to control PWM3 in automatic fan control loop SMB1 R/W Logic 1 enables SMBus Slave Device 1 to control PWM3 in automatic fan control loop SMB2 R/W Logic 1 enables SMBus Slave Device 2 to control PWM3 in automatic fan control loop SMB3 R/W Logic 1 enables SMBus Slave Device 3 to control PWM3 in automatic fan control loop SMB4 R/W Logic 1 enables SMBus Slave Device 4 to control PWM3 in automatic fan control loop SMB5 R/W Logic 1 enables SMBus Slave Device 5 to control PWM3 in automatic fan control loop SMB6 R/W Logic 1 enables SMBus Slave Device 6 to control PWM3 in automatic fan control loop SMB7 R/W Logic 1 enables SMBus Slave Device 7 to control PWM3 in automatic fan control loop Table 114. REGISTER 0x92 − PWM3 Source Control 3 (Power−On Default = 0x00) Bit Name R/W Description PUSH0 R/W Logic 1 enables Externally written temperature 0 to control PWM3 in automatic fan control loop PUSH1 R/W Logic 1 enables Externally written temperature 1 to control PWM3 in automatic fan control loop PUSH2 R/W Logic 1 enables Externally written temperature 2 to control PWM3 in automatic fan control loop PUSH3 R/W Logic 1 enables Externally written temperature 3 to control PWM3 in automatic fan control loop Reserved Reserved Reserved Reserved www.onsemi.com 68 NCT7491 Table 115. DEVICE ID REGISTER Register Address R/W Description 0x93 Read Device Revision Power−On Default Table 116. PECI OFFSET REGISTERS Register Address R/W Description Power−On Default 0x94 R/W PECI0 Offset 0x00 0x95 R/W PECI1 Offset 0x00 0x96 R/W PECI2 Offset 0x00 0x97 R/W PECI3 Offset 0x00 Table 117. SMBus MASTER ADDRESS TABLE Register Address R/W Description Default 0x98 R/W Device 0 (PCH) SMBus Address 0x00 0x99 R/W Device 0 (PCH) Block Read command code 0x40 0x9A R/W Device 1 SMBus Address 0x00 0x9B R/W Device 1 Temperature Address Pointer 0x00 0x9C R/W Device 2 SMBus Address 0x00 0x9D R/W Device 2 Temperature Address Pointer 0x00 0x9E R/W Device 3 SMBus Address 0x00 0x9F R/W Device 3 Temperature Address Pointer 0x00 0xA0 R/W Device 4 SMBus Address 0x00 0xA1 R/W Device 4 Temperature Address Pointer 0x00 0xA2 R/W Device 5 SMBus Address 0x00 0xA3 R/W Device 5 Temperature Address Pointer 0x00 0xA4 R/W Device 6 SMBus Address 0x00 0xA5 R/W Device 6 Temperature Address Pointer 0x00 0xA6 R/W Device 7 SMBus Address 0x00 0xA7 R/W Device 7 Temperature Address Pointer 0x00 Table 118. SMBus MASTER TEMPERATURE VALUES Register Address R/W Description 0xA8 R/W SMBus Device 0 (PCH) Temperature 0x80 0xA9 R/W SMBus Device 1 (DIMM0) Temperature 0x80 0xAA R/W SMBus Device 2 (DIMM1) Temperature 0x80 0xAB R/W SMBus Device 3 (DIMM2) Temperature 0x80 0xAC R/W SMBus Device 4 (DIMM3) Temperature 0x80 0xAD R/W SMBus Device 5 Temperature 0x80 0xAE R/W SMBus Device 6 Temperature 0x80 0xAF R/W SMBus Device 7 Temperature 0x80 Table 119. Register 0xB0 − SMBus Master Configuration 1 (Power−On Default = 0xFF) Bit Name R/W Description RS0 R/W Logic 1 enables the Repeated Start protocol for SMBus Slave Device 0 RS1 R/W Logic 1 enables the Repeated Start protocol for SMBus Slave Device 1 www.onsemi.com 69 Default NCT7491 Table 119. Register 0xB0 − SMBus Master Configuration 1 (Power−On Default = 0xFF) Bit Name R/W Description RS2 R/W Logic 1 enables the Repeated Start protocol for SMBus Slave Device 2 RS3 R/W Logic 1 enables the Repeated Start protocol for SMBus Slave Device 3 RS4 R/W Logic 1 enables the Repeated Start protocol for SMBus Slave Device 4 RS5 R/W Logic 1 enables the Repeated Start protocol for SMBus Slave Device 5 RS6 R/W Logic 1 enables the Repeated Start protocol for SMBus Slave Device 6 RS7 R/W Logic 1 enables the Repeated Start protocol for SMBus Slave Device 7 Table 120. REGISTER 0xB1 − SMBus Master Configuration 2 (Power−On Default = 0x00) Bit Name R/W Description PEC0 R/W Logic 1 enables PEC byte support for SMBus Slave Device 0 PEC1 R/W Logic 1 enables PEC byte support for SMBus Slave Device 1 PEC2 R/W Logic 1 enables PEC byte support for SMBus Slave Device 2 PEC3 R/W Logic 1 enables PEC byte support for SMBus Slave Device 3 PEC4 R/W Logic 1 enables PEC byte support for SMBus Slave Device 4 PEC5 R/W Logic 1 enables PEC byte support for SMBus Slave Device 5 PEC6 R/W Logic 1 enables PEC byte support for SMBus Slave Device 6 PEC7 R/W Logic 1 enables PEC byte support for SMBus Slave Device 7 Table 121. REGISTER 0xB2 − SMBus Master Configuration 3 (Power−On Default = 0x03) Bit Name R/W Description TMFT0 R/W SMBus Device 0 temperature format: 00 = 8−bit 2’s Complement 01 = JEDEC SPD format 10 = 8−bit straight binary 11 = Block reads enabled TMFT1 R/W SMBus Device 1 temperature format: 00 = 8−bit 2’s Complement 01 = JEDEC SPD format 10 = 8−bit straight binary 11 = Block reads enabled TMFT2 R/W SMBus Device 2 temperature format: 00 = 8−bit 2’s Complement 01 = JEDEC SPD format 10 = 8−bit straight binary 11 = Block reads enabled TMFT3 R/W SMBus Device 3 temperature format: 00 = 8−bit 2’s Complement 01 = JEDEC SPD format 10 = 8−bit straight binary 11 = Block reads enabled www.onsemi.com 70 NCT7491 Table 122. REGISTER 0xB3 − SMBus Master Configuration 4 (Power−On Default = 0x00) Bit Name R/W Description TMFT4 R/W SMBus Device 4 temperature format: 00 = 8−bit 2’s Complement 01 = JEDEC SPD format 10 = 8−bit straight binary 11 = Reserved TMFT5 R/W SMBus Device 5 temperature format: 00 = 8−bit 2’s Complement 01 = JEDEC SPD format 10 = 8−bit straight binary 11 = Literal Format TMFT6 R/W SMBus Device 6 temperature format: 00 = 8−bit 2’s Complement 01 = JEDEC SPD format 10 = 8−bit straight binary 11 = Literal Format TMFT7 R/W SMBus Device 7 temperature format: 00 = 8−bit 2’s Complement 01 = JEDEC SPD format 10 = 8−bit straight binary 11 = Literal Format Table 123. REGISTER 0xB5 − SMBus Master Configuration 5 (Power−On Default = 0x08) Bit Name R/W SMBEN R/W 0 = SMBus Master disabled 1 = SMBus Master enabled Description SHYS R/W SMBus Device temperature hysteresis R1DIMM R/W 1 = Over−write DIMM0/DIMM1 value registers with Remote1 value R2DIMM R/W 1 = Over−write DIMM2/DIMM3 value registers with Remote2 value PCHDIMM R/W 1 = Read DIMM temperatures from PCH. This setting overrides bits 5 and 6 of this register. 0 = Read DIMM temperatures from SMBus digital sensors Table 124. REGISTER 0xB6 − SMBus Master Status 1 (Power−On Default = 0x00) Bit Name R/W Description NACK0 Read Logic 1 indicates a No Acknowledge from SMBus Device 0 NACK1 Read Logic 1 indicates a No Acknowledge from SMBus Device 1 NACK2 Read Logic 1 indicates a No Acknowledge from SMBus Device 2 NACK3 Read Logic 1 indicates a No Acknowledge from SMBus Device 3 NACK4 Read Logic 1 indicates a No Acknowledge from SMBus Device 4 NACK5 Read Logic 1 indicates a No Acknowledge from SMBus Device 5 NACK6 Read Logic 1 indicates a No Acknowledge from SMBus Device 6 NACK7 Read Logic 1 indicates a No Acknowledge from SMBus Device 7 Table 125. REGISTER 0xB7 − SMBus Master Status 2 (Power−On Default = 0x00) Bit Name R/W Description PEC0 Read Logic 1 indicates an SMBus Device 0 PEC error PEC1 Read Logic 1 indicates an SMBus Device 1 PEC error PEC2 Read Logic 1 indicates an SMBus Device 2 PEC error PEC3 Read Logic 1 indicates an SMBus Device 3 PEC error www.onsemi.com 71 NCT7491 Table 125. REGISTER 0xB7 − SMBus Master Status 2 (Power−On Default = 0x00) Bit Name R/W Description PEC4 Read Logic 1 indicates an SMBus Device 4 PEC error PEC5 Read Logic 1 indicates an SMBus Device 5 PEC error PEC6 Read Logic 1 indicates an SMBus Device 6 PEC error PEC7 Read Logic 1 indicates an SMBus Device 7 PEC error Table 126. REGISTER 0xB8 − SMBus Master Status 3 (Power−On Default = 0x00) Bit Name R/W Description TO0 Read Logic 1 indicates an SMBus Device 0 timeout error TO1 Read Logic 1 indicates an SMBus Device 1 timeout error TO2 Read Logic 1 indicates an SMBus Device 2 timeout error TO3 Read Logic 1 indicates an SMBus Device 3 timeout error TO4 Read Logic 1 indicates an SMBus Device 4 timeout error TO5 Read Logic 1 indicates an SMBus Device 5 timeout error TO6 Read Logic 1 indicates an SMBus Device 6 timeout error TO7 Read Logic 1 indicates an SMBus Device 7 timeout error Table 127. REGISTER 0xB9 − SMBus Master Status 4 (Power−On Default = 0x00) Bit Name R/W Description HILO0 Read Logic 1 indicates that the SMBus Device 0 reading is out of limits HILO1 Read Logic 1 indicates that the SMBus Device 1 reading is out of limits HILO2 Read Logic 1 indicates that the SMBus Device 2 reading is out of limits HILO3 Read Logic 1 indicates that the SMBus Device 3 reading is out of limits HILO4 Read Logic 1 indicates that the SMBus Device 4 reading is out of limits HILO5 Read Logic 1 indicates that the SMBus Device 5 reading is out of limits HILO6 Read Logic 1 indicates that the SMBus Device 6 reading is out of limits HILO7 Read Logic 1 indicates that the SMBus Device 7 reading is out of limits Table 128. REGISTER 0Xba − SMBus Master Status 5 (Power−On Default = 0x00) Bit Name R/W TIV0 Read Logic 1 indicates that the PCH returned a reserved temperature code Description TIV1 Read Logic 1 indicates that the PCH returned a reserved temperature code TIV2 Read Logic 1 indicates that the PCH returned a reserved temperature code TIV3 Read Logic 1 indicates that the PCH returned a reserved temperature code TIV4 Read Logic 1 indicates that the PCH returned a reserved temperature code Reserved Read Reserved Reserved Read Reserved Reserved Read Reserved Table 129. REGISTER 0Xbb − SMBus Master Status 6 (Power−On Default = 0x00) Bit Name R/W Description TH0 Read Logic 1 indicates that the SMBus Device 0 reading is above the programmed THERM Limit TH1 Read Logic 1 indicates that the SMBus Device 1 reading is above the programmed THERM Limit TH2 Read Logic 1 indicates that the SMBus Device 2 reading is above the programmed THERM Limit www.onsemi.com 72 NCT7491 Table 129. REGISTER 0Xbb − SMBus Master Status 6 (Power−On Default = 0x00) Bit Name R/W Description TH3 Read Logic 1 indicates that the SMBus Device 3 reading is above the programmed THERM Limit TH4 Read Logic 1 indicates that the SMBus Device 4 reading is above the programmed THERM Limit TH5 Read Logic 1 indicates that the SMBus Device 5 reading is above the programmed THERM Limit TH6 Read Logic 1 indicates that the SMBus Device 6 reading is above the programmed THERM Limit TH7 Read Logic 1 indicates that the SMBus Device 7 reading is above the programmed THERM Limit Table 130. REGISTER 0xBC − SMBus Master Mask 1 (Power−On Default = 0x00) Bit Name R/W Description NACK0 R/W Logic 1 masks a No Acknowledge assertion for SMBus Device 0 NACK1 R/W Logic 1 masks a No Acknowledge assertion for SMBus Device 1 NACK2 R/W Logic 1 masks a No Acknowledge assertion for SMBus Device 2 NACK3 R/W Logic 1 masks a No Acknowledge assertion for SMBus Device 3 NACK4 R/W Logic 1 masks a No Acknowledge assertion for SMBus Device 4 NACK5 R/W Logic 1 masks a No Acknowledge assertion for SMBus Device 5 NACK6 R/W Logic 1 masks a No Acknowledge assertion for SMBus Device 6 NACK7 R/W Logic 1 masks a No Acknowledge assertion for SMBus Device 7 Table 131. REGISTER 0xBD − SMBus Master Mask 2 (Power−On Default = 0x00) Bit Name R/W Description PEC0 R/W Logic 1 masks a PEC error assertion for SMBus Device 0 PEC1 R/W Logic 1 masks a PEC error assertion for SMBus Device 1 PEC2 R/W Logic 1 masks a PEC error assertion for SMBus Device 2 PEC3 R/W Logic 1 masks a PEC error assertion for SMBus Device 3 PEC4 R/W Logic 1 masks a PEC error assertion for SMBus Device 4 PEC5 R/W Logic 1 masks a PEC error assertion for SMBus Device 5 PEC6 R/W Logic 1 masks a PEC error assertion for SMBus Device 6 PEC7 R/W Logic 1 masks a PEC error assertion for SMBus Device 7 Table 132. REGISTER 0Xbe − SMBus Master Mask 3 (Power−On Default = 0x00) Bit Name R/W Description TO0 R/W Logic 1 masks a timeout error assertion for SMBus Device 0 TO1 R/W Logic 1 masks a timeout error assertion for SMBus Device 1 TO2 R/W Logic 1 masks a timeout error assertion for SMBus Device 2 TO3 R/W Logic 1 masks a timeout error assertion for SMBus Device 3 TO4 R/W Logic 1 masks a timeout error assertion for SMBus Device 4 TO5 R/W Logic 1 masks a timeout error assertion for SMBus Device 5 TO6 R/W Logic 1 masks a timeout error assertion for SMBus Device 6 TO7 R/W Logic 1 masks a timeout error assertion for SMBus Device 7 Table 133. REGISTER 0Xbf − SMBus Master Mask 4 (Power−On Default = 0x00) Bit Name R/W Description HILO0 R/W Logic 1 masks limit assertions for SMBus Device 0 HILO1 R/W Logic 1 masks limit assertions for SMBus Device 1 www.onsemi.com 73 NCT7491 Table 133. REGISTER 0Xbf − SMBus Master Mask 4 (Power−On Default = 0x00) Bit Name R/W Description HILO2 R/W Logic 1 masks limit assertions for SMBus Device 2 HILO3 R/W Logic 1 masks limit assertions for SMBus Device 3 HILO4 R/W Logic 1 masks limit assertions for SMBus Device 4 HILO5 R/W Logic 1 masks limit assertions for SMBus Device 5 HILO6 R/W Logic 1 masks limit assertions for SMBus Device 6 HILO7 R/W Logic 1 masks limit assertions for SMBus Device 7 Table 134. REGISTER 0xC0 − SMBus Master Mask 5 (Power−On Default = 0x00) Bit Name R/W Description TIV0 R/W Logic 1 masks data invalid assertion for SMBus Device 0 TIV1 R/W Logic 1 masks data invalid assertion for SMBus Device 1 TIV2 R/W Logic 1 masks data invalid assertion for SMBus Device 2 TIV3 R/W Logic 1 masks data invalid assertion for SMBus Device 3 TIV4 R/W Logic 1 masks data invalid assertion for SMBus Device 4 TIV5 R/W Logic 1 masks data invalid assertion for SMBus Device 5 TIV6 R/W Logic 1 masks data invalid assertion for SMBus Device 6 TIV7 R/W Logic 1 masks data invalid assertion for SMBus Device 7 Table 135. SMBus MASTER LIMIT REGISTERS Register Address R/W Description Power−On Default 0xC1 R/W SMBus Device High Limit. Programmed as an unsigned 8−bit value 0x7F 0xC2 R/W SMBus Device Low Limit. Programmed as an 8−bit 2’s complement value. 0x81 Table 136. SMBus MASTER THERM LIMIT REGISTERS Register Address R/W 0xC3 R/W Description SMBus Device THERM Limit. Programmed as an unsigned 8−bit value Power−On Default 0x64 Table 137. SMBus DEVICE TMIN REGISTER Register Address R/W 0xC6 R/W Description SMBus Device Tmin value. This sets the the temperature at which fans controlled by any SMBus slave device will turn on. Programmed as an unsigned 8−bit value in the range 0°C to 175°C. www.onsemi.com 74 Power−On Default 0x5A NCT7491 Table 138. REGISTER 0xC7 − SMBus Master Trange/Interval (Power−On Default = 0x0C) Bit Name R/W Description RNG R/W These bits determine the PWM duty cycle vs. the temperature range for automatic fan control. 0000 = 2°C 0001 = 2.5°C 0010 = 3.33°C 0011 = 4°C 0100 = 5°C 0101 = 6.67°C 0110 = 8°C 0111 = 10°C 1000 = 13.33°C 1001 = 16°C 1010 = 20°C 1011 = 26.67°C 1100 = 32°C (default) 1101 = 40°C 1110 = 53.33°C 1111 = 80°C Reserved SMBINT R/W Sets the SMBus Master loop time 00 = 250 ms 01 = 500 ms 10 = 750 ms 11 = 1 sec Table 139. PUSH TEMPERATURE REGISTERS Register Address R/W Description Power−On Default 0xC8 R/W Push0. This register is programmable by an external master to allow temperatures gathered externally to be used by the NCT7491 fan control loop 0x00 0xC9 R/W Push1. This register is programmable by an external master to allow temperatures gathered externally to be used by the NCT7491 fan control loop 0x00 0xCA R/W Push2. This register is programmable by an external master to allow temperatures gathered externally to be used by the NCT7491 fan control loop 0x00 Push3. This register is programmable by an external master to allow temperatures gathered externally to be used by the NCT7491 fan control loop 0x00 0xCB Table 140. PUSH TMIN REGISTER Register Address R/W Description Power−On Default 0xCC R/W Push Device Tmin value. This sets the the temperature at which fans controlled by any SMBus slave device will turn on. This value applies to all 4 Push temperature registers. This value should be programmed in the range 0°C to 127°C 0x5A www.onsemi.com 75 NCT7491 Table 141. REGISTER 0xCD − Push Trange (Power−On Default = 0x0C) Bit Name R/W RNG R/W Reserved Description These bits determine the PWM duty cycle vs. the temperature range for automatic fan control. 0000 = 2°C 0001 = 2.5°C 0010 = 3.33°C 0011 = 4°C 0100 = 5°C 0101 = 6.67°C 0110 = 8°C 0111 = 10°C 1000 = 13.33°C 1001 = 16°C 1010 = 20°C 1011 = 26.67°C 1100 = 32°C (default) 1101 = 40°C 1110 = 53.33°C 1111 = 80°C Table 142. PUSH TEMPERATURE LIMIT REGISTERS Register Address R/W Description Power−On Default 0xCE R/W Push High Limit 0x7F 0xCF R/W Push Low Limit 0x81 0xD0 R/W Push THERM Limit 0x64 Table 143. GENERIC PECI INTERFACE BLOCK Register Address R/W 0xD1 R/W Generic PECI CPU Address. This sets the target processor address for the PECI command 0x00 0xD2 R/W Write Length. This sets the number of byte transferred to the target device when the command is executed 0x00 0xD3 R/W Read Length. This specifies the number of bytes to be returned by the target. 0x00 0xD4 Description 1st byte to be transferred (Command Code) Default R/W WRDAT0; The 0xD5 R/W WRDAT1; 2nd 0x00 byte to be transferred 0x00 0xD6 R/W WRDAT2; 3rd byte to be transferred 0x00 0xD7 R/W WRDAT3; 4th byte to be transferred 0x00 0xD8 R/W WRDAT4; 5th byte to be transferred 0x00 0xD9 R/W WRDAT5; 6th byte to be transferred 0x00 0xDA R/W WRDAT6; 7th byte to be transferred 0x00 0xDB R/W WRDAT7; 8th byte to be transferred 0x00 0xDC R/W WRDAT8; 9th byte to be transferred 0x00 0xDD R/W WRDAT9; 10th byte to be transferred 0x00 0xDE R/W WRDAT10; 11th byte to be transferred 0x00 0xDF R/W WRDAT11; 12th byte to be transferred 0x00 0xE0 R/W WRDAT12; 13th byte to be transferred 0x00 1st 0xE1 R/W RDDAT0; The byte returned 0x00 0xE2 R/W RDDAT1; The 2nd byte returned 0x00 0xE3 R/W RDDAT2; The 3rd byte returned 0x00 0xE4 R/W RDDAT3; The 4th byte returned 0x00 R/W 5th 0x00 0xE5 RDDAT4; The byte returned www.onsemi.com 76 NCT7491 Table 143. GENERIC PECI INTERFACE BLOCK Register Address R/W 0xE6 R/W RDDAT5; The 6th byte returned 0x00 R/W RDDAT6; The 7th byte returned 0x00 RDDAT6; The 8th byte returned 0x00 RDDAT6; The 9th byte returned 0x00 0xE7 0xE8 Description R/W 0xE9 R/W Default Table 144. REGISTER 0xEA − PECI Configuration 5 (Power−On Default = 0x00) Bit Name R/W Description Reserved AW R/W Logic 1 indicates that the command is an Assured Write command. The AW byte is automatically calculated and appended by the NCT7491. Even though the user does not program the AW value the Write Length register for an Assured Write command should include the AW byte (for example, if 5 bytes are to be written the Write length register should be set to 6 as the AW byte will be added to the end of the write sequence) PEX R/W Logic 1 will cause the programmed PECI command sequence to be executed. This bit will automatically clear when the command has completed. Reserved Table 145. REGISTER 0xEB − Push Hysteresis (Power−On Default = 0x04) Bit Name R/W Push Hyst R/W Reserved Description Sets the hysteresis value associated with the Push temperature registers Table 146. REGISTER 0xFF − Page Select Bit Name R/W RGMP R/W Reserved R Description 1 = Selects register map page 1 Table 147. FAN1 LOOK UP TABLE Register Address R/W Description 0x100 R/W Sets the temperature for the 1st LUT point for Fan1 0x00 0x101 R/W Sets the PWM output for the 1st LUT point for Fan1 0xFF 0x102 R/W Sets the temperature for the 2nd LUT point for Fan1 0x00 0x103 R/W Sets the PWM output for the 2nd LUT point for Fan1 0xFF 0x104 R/W Sets the temperature for the 3rd LUT point for Fan1 0x00 0x105 R/W Sets the PWM output for the 3rd LUT point for Fan1 0xFF 0x106 R/W Sets the temperature for the 4th LUT point for Fan1 0x00 0x107 R/W Sets the PWM output for the 4th LUT point for Fan1 0xFF 0x108 R/W Sets the temperature for the 5th LUT point for Fan1 0x00 0x109 R/W Sets the PWM output for the 5th LUT point for Fan1 0xFF 0x10A R/W Sets the temperature for the 6th LUT point for Fan1 0x00 0x10B R/W Sets the PWM output for the 6th LUT point for Fan1 0xFF 0x10C R/W Sets the temperature for the 7th LUT point for Fan1 0x00 0x10D R/W Sets the PWM output for the 7th LUT point for Fan1 0xFF 0x10E R/W Sets the temperature for the 8th LUT point for Fan1 0x00 0x10F R/W Sets the PWM output for the 8th LUT point for Fan1 0xFF www.onsemi.com 77 Default NCT7491 Table 148. FAN2 LOOK UP TABLE Register Address R/W Description Default 0x110 R/W Sets the temperature for the 1st LUT point for Fan2 0xFF 0x111 R/W Sets the PWM output for the 1st LUT point for Fan2 0xFF 0x112 R/W Sets the temperature for the 2nd LUT point for Fan2 0xFF 0x113 R/W Sets the PWM output for the 2nd LUT point for Fan2 0xFF 0x114 R/W Sets the temperature for the 3rd LUT point for Fan2 0xFF 0x115 R/W Sets the PWM output for the 3rd LUT point for Fan2 0xFF 0x116 R/W Sets the temperature for the 4th LUT point for Fan2 0xFF 0x117 R/W Sets the PWM output for the 4th LUT point for Fan2 0xFF 0x118 R/W Sets the temperature for the 5th LUT point for Fan2 0xFF 0x119 R/W Sets the PWM output for the 5th LUT point for Fan2 0xFF 0x11A R/W Sets the temperature for the 6th LUT point for Fan2 0xFF 0x11B R/W Sets the PWM output for the 6th LUT point for Fan2 0xFF 0x11C R/W Sets the temperature for the 7th LUT point for Fan2 0xFF 0x11D R/W Sets the PWM output for the 7th LUT point for Fan2 0xFF 0x11E R/W Sets the temperature for the 8th LUT point for Fan2 0xFF 0x11F R/W Sets the PWM output for the 8th LUT point for Fan2 0xFF Table 149. FAN3 LOOK UP TABLE Register Address R/W Description 0x120 R/W Sets the temperature for the 1st LUT point for Fan3 0xFF 0x121 R/W Sets the PWM output for the 1st LUT point for Fan3 0xFF 0x122 R/W Sets the temperature for the 2nd LUT point for Fan3 0xFF 0x123 R/W Sets the PWM output for the 2nd LUT point for Fan3 0xFF 0x124 R/W Sets the temperature for the 3rd LUT point for Fan3 0xFF 0x125 R/W Sets the PWM output for the 3rd LUT point for Fan3 0xFF 0x126 R/W Sets the temperature for the 4th LUT point for Fan3 0xFF 0x127 R/W Sets the PWM output for the 4th LUT point for Fan3 0xFF 0x128 R/W Sets the temperature for the 5th LUT point for Fan3 0xFF 0x129 R/W Sets the PWM output for the 5th LUT point for Fan3 0xFF 0x12A R/W Sets the temperature for the 6th LUT point for Fan3 0xFF 0x12B R/W Sets the PWM output for the 6th LUT point for Fan3 0xFF 0x12C R/W Sets the temperature for the 7th LUT point for Fan3 0xFF 0x12D R/W Sets the PWM output for the 7th LUT point for Fan3 0xFF 0x12E R/W Sets the temperature for the 8th LUT point for Fan3 0xFF 0x12F R/W Sets the PWM output for the 8th LUT point for Fan3 0xFF Table 150. REGISTER 0x1FF − Page Select Clear Bit Name R/W RGMP R/W Reserved R Description 0 = Selects register map page 0 www.onsemi.com 78 Default MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS QFN24, 4x4, 0.5P CASE 485L ISSUE B 1 24 SCALE 2:1 D PIN 1 REFEENCE 2X 0.15 C 2X ÉÉÉ ÉÉÉ ÉÉÉ 0.15 C DETAIL A E ALTERNATE CONSTRUCTIONS ÉÉÉ ÉÉÉ ÇÇÇ EXPOSED Cu DETAIL B 0.10 C SEATING PLANE L 24X 7 DIM A A1 A3 b D D2 E E2 e L L1 MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.20 0.30 4.00 BSC 2.70 2.90 4.00 BSC 2.70 2.90 0.50 BSC 0.30 0.50 0.05 0.15 XXXXX XXXXX ALYWG G 13 E2 1 24 A1 A3 GENERIC MARKING DIAGRAM* D2 DETAIL A ÉÉ ÉÉ ÇÇ ALTERNATE TERMINAL CONSTRUCTIONS C A1 SIDE VIEW MOLD CMPD DETAIL B A A3 NOTE 4 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L1 TOP VIEW 0.08 C L L A B DATE 05 JUN 2012 19 e e/2 24X b 0.10 C A B 0.05 C BOTTOM VIEW NOTE 3 RECOMMENDED SOLDERING FOOTPRINT 4.30 24X 0.55 2.90 XXXXX = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. 1 4.30 2.90 0.50 PITCH 24X 0.32 DIMENSIONS: MILLIMETERS DOCUMENT NUMBER: DESCRIPTION: 98AON11783D QFN24, 4X4, 0.5P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS QSOP24 NB CASE 492B−01 ISSUE A DATE 06 MAY 2008 2X SCALE 2:1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. 4. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EX­ CEED 0.15 PER SIDE. DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. IN­ TERLEAD FLASH OR PROTRUSION SHALL NOT EX­ CEED 0.15 PER SIDE. D AND E1 ARE DETERMINED AT DATUM H. 5. DATUMS A AND B ARE DETERMINED AT DATUM H. 0.20 C D D A 24 D C 13 GAUGE PLANE L2 E E1 C L DETAIL A 2X 2X 12 TIPS 0.20 C D 1 12 24X e B b 0.25 0.25 C D M C A-B D A 0.10 C 0.10 C A1 24X C SEATING PLANE 24X 0.42 1.12 24 h x 45 _ H SOLDERING FOOTPRINT 24X DIM A A1 b C D E E1 e h L L2 M DETAIL A M MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.20 0.30 0.19 0.25 8.65 BSC 6.00 BSC 3.90 BSC 0.635 BSC 0.22 0.50 0.40 1.27 0.25 BSC 0_ 8_ GENERIC MARKING DIAGRAM* 13 xxxxxxxxx AWLYWW 6.40 1 12 0.635 PITCH DOCUMENT NUMBER: DESCRIPTION: DIMENSIONS: MILLIMETERS 98AON04474D QSOP24 NB xxx A WL Y WW = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G”, may or not be present. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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