NCV4266-2CST50T3G

NCV4266-2C Regulator with Enable, 150 mA, Low-Dropout Voltage, Low Iq The NCV4266−2C is a 150 mA output current integrated low dropout, low quiescent current regulator family designed for use in harsh automotive environments. It includes wide operating temperature and input voltage ranges. The device is offered with fixed voltage versions of 3.3 V and 5.0 V available in 2% output voltage accuracy. It has a high peak input voltage tolerance and reverse input voltage protection. It also provides overcurrent protection, overtemperature protection and enable function for control of the state of the output voltage. The NCV4266−2C is available in SOT−223 surface mount package. The output is stable over a wide output capacitance and ESR range. The NCV4266−2C has improved startup behavior during input voltage transients. www.onsemi.com SOT−223 ST SUFFIX CASE 318E MARKING DIAGRAM Features • • • • • • • • • Output Voltage Options: 3.3 V, 5.0 V Output Voltage Accuracy: ±2.0% Output Current: up to 150 mA Low Quiescent Current (typ. 40 mA @ 100 mA) Low Dropout Voltage (typ. 250 mV @ 100 mA) Enable Input Fault Protection ♦ +45 V Peak Transient Voltage ♦ −42 V Reverse Voltage ♦ Short Circuit ♦ Thermal Overload NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable These are Pb−Free Devices I AYW 662CxG G 1 A Y W x G = Assembly Location = Year = Work Week = Voltage Option 3.3 V (x = 3) 5.0 V (x = 5) = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the ordering information section on page 10 of this data sheet. Q Bandgap Reference Error Amplifier Current Limit and Saturation Sense − + Thermal Shutdown EN GND Figure 1. Block Diagram © Semiconductor Components Industries, LLC, 2015 November, 2018 − Rev. 3 1 Publication Order Number: NCV4266−2C/D NCV4266−2C PIN FUNCTION DESCRIPTION Pin No. DFN8 Pin No. 1 1 I 3 2 EN Enable Input; Low level disables the IC. 4 3 Q Output; Bypass with a capacitor to GND. 8 4 GND Symbol Description Input; Battery Supply Input Voltage. Ground. MAXIMUM RATINGS Symbol Min Max Unit Input Voltage Rating VI −42 45 V Input Peak Transient Voltage VI − 45 V Enable Input Voltage VEN −42 45 V Output Voltage VQ −0.3 32 V Ground Current Iq − 100 mA Input Voltage Operating Range VI VQ + 0.5 V or 4.5 (Note 1) 45 V − 3.0 − kV Junction Temperature TJ −40 150 °C Storage Temperature Tstg −50 150 °C ESD Susceptibility (Human Body Model) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Minimum VI = 4.5 V or (VQ + 0.5 V), whichever is higher. LEAD TEMPERATURE SOLDERING REFLOW AND MSL (Note 2) Rating Symbol Lead Temperature Soldering Reflow (SMD styles only), Leaded, 60−150 s above 183, 30 s max at peak Reflow (SMD styles only), Free, 60−150 s above 217, 40 s max at peak Wave Solder (through hole styles only), 12 sec max TSLD Moisture Sensitivity Level MSL Min Max − − − 240 265 310 3 Unit °C − 2. Per IPC / JEDEC J−STD−020C. THERMAL RESISTANCE Parameter Symbol Condition Min Max Unit Junction−to−Ambient SOT−223 RqJA − 109 (Note 3) °C/W Junction−to−Tab SOT−223 RyJT − 10.9 °C/W 3. 1 oz copper, 100 mm2 copper area, FR4. www.onsemi.com 2 NCV4266−2C ELECTRICAL CHARACTERISTICS (−40°C < TJ < 150°C, VI = 13.5 V, VEN = 5 V; unless otherwise noted.) Symbol Characteristic Test Conditions Min Typ Max Unit OUTPUT Output Voltage (5.0 V Version) VQ 100 mA < IQ < 150 mA, 6.0 V < VI < 28 V 4.9 5.0 5.1 V Output Voltage (3.3 V Version) VQ 100 mA < IQ < 150 mA, 4.5 V < VI < 28 V 3.234 3.3 3.366 V Output Current Limitation IQ VQ = 90% VQTYP 150 390 500 mA Quiescent Current (Sleep Mode) Iq = II − IQ Iq VEN = 0 V, TJ = −40°C to 100°C − 0 1.0 mA Quiescent Current, Iq = II − IQ Iq IQ = 100 mA, TJ < 85°C − 40 60 mA Quiescent Current, Iq = II − IQ Iq IQ = 100 mA − 40 70 mA Iq IQ = 50 mA − 0.55 4.0 mA IQ = 100 mA, VDR = VI − VQ (Note 4) − 230 500 mV Quiescent Current, Iq = II − IQ Dropout Voltage (5.0 V Version) VDR Load Regulation (5.0 V Version) DVQ,LO IQ = 1.0 mA to 100 mA − 3.5 90 mV Load Regulation (3.3 V Version) DVQ,LO IQ = 1.0 mA to 100 mA − 0.5 60 mV Line Regulation (5.0 V Version) DVQ DVI = 6.0 V to 28 V, IQ = 1.0 mA − 1.0 30 mV Line Regulation (3.3 V Version) DVQ DVI = 4.5 V to 28 V, IQ = 1.0 mA − 0.5 20 mV Power Supply Ripple Rejection PSRR fr = 100 Hz, Vr = 0.5 VPP − 68 − dB ENABLE INPUT Enable Voltage, Output High VEN VQ w VQMIN − 2.0 2.7 V Enable Voltage, Output Low (Off) VEN VQ v 0.1 V 0.8 1.8 − V Enable Input Current IEN VEN = 5.0 V − 4.0 8.0 mA 150 − 200 °C THERMAL SHUTDOWN Thermal Shutdown Temperature* TSD Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. *Guaranteed by design, not tested in production. 4. Measured when the output voltage VQ has dropped 100 mV from the nominal value obtained at V = 13.5 V. Input II CI1 1.0 mF I 1 CI2 100 nF NCV4266−2C EN IEN 2 IQ 3 Q CQ 3.3 mF RL 4 GND Figure 2. Applications Circuit www.onsemi.com 3 Output NCV4266−2C TYPICAL CHARACTERISTICS CURVES − 5 V Version 100 5.10 VQ, OUTPUT VOLTAGE (V) Unstable Region ESR (W) 10 1 Stable Region 0.1 VI = 13.5 V RL = 1 kW 5.05 5.00 4.95 CQ = 3.3 mF 0.01 0 25 50 75 100 125 4.90 −40 150 0 IQ, OUTPUT CURRENT (mA) Figure 3. Output Stability with Output Capacitor ESR II, INPUT CURRENT (mA) VQ, OUTPUT VOLTAGE (V) 160 4 3 2 RL = 33 W TJ = 25°C 1 0 1 2 3 4 5 6 7 8 9 0.6 0.2 −0.2 RL = 6.8 kW TJ = 25°C −0.6 −1.0 −50 −40 −30 −20 −10 10 VI, INPUT VOLTAGE (V) 0 10 20 30 40 50 VI, INPUT VOLTAGE (V) Figure 5. Output Voltage vs. Input Voltage Figure 6. Input Current vs. Input Voltage 450 VDR, DROPOUT VOLTAGE (mV) 350 IQ, OUTPUT CURRENT (mA) 120 1.0 5 300 250 200 150 VQ = 0 V TJ = 25°C 100 50 0 80 Figure 4. Output Voltage vs. Junction Temperature 6 0 40 TJ, JUNCTION TEMPERATURE (°C) 0 5 10 15 20 25 30 VI, INPUT VOLTAGE (V) 35 40 400 350 250 200 Figure 7. Maximum Output Current vs. Input Voltage TJ = 25°C 150 100 50 0 45 TJ = 125°C 300 0 25 50 75 100 IQ, OUTPUT CURRENT (mA) 125 Figure 8. Dropout Voltage vs. Output Current www.onsemi.com 4 150 NCV4266−2C TYPICAL CHARACTERISTICS CURVES − 5 V Version 0.25 Iq, QUIESCENT CURRENT (mA) VI = 13.5 V TJ = 25°C 3.0 2.5 2.0 1.5 1.0 0.5 0 VI = 13.5 V TJ = 25°C 0.20 0.15 0.10 0.05 0 0 25 50 75 100 IQ, OUTPUT CURRENT (mA) 125 150 0 Figure 9. Quiescent Current vs. Output Current (High Load) 2 4 10 12 14 16 6 8 IQ, OUTPUT CURRENT (mA) 5 4 3 2 TJ = 25°C RL = 33 W 1 0 0 5 10 15 18 Figure 10. Quiescent Current vs. Output Current (Low Load) 6 Iq, QUIESCENT CURRENT (mA) Iq, QUIESCENT CURRENT (mA) 3.5 20 25 30 35 VI, INPUT VOLTAGE (V) Figure 11. Quiescent Current vs. Input Voltage www.onsemi.com 5 40 20 NCV4266−2C TYPICAL CHARACTERISTICS CURVES − 3.3 V Version 3.36 100 VQ, OUTPUT VOLTAGE (V) Unstable Region ESR (W) 10 1 Stable Region 0.1 CQ = 3.3 mF 0.01 0 25 50 75 100 125 3.32 3.30 3.28 VI = 13.5 V RL = 660 W 3.26 3.24 −40 150 0 40 120 160 TJ, JUNCTION TEMPERATURE (°C) Figure 12. Output Stability with Output Capacitor ESR Figure 13. Output Voltage vs. Junction Temperature 1.0 II, INPUT CURRENT (mA) 3 2 RL = 22 W TJ = 25°C 1 0 0 1 2 3 4 5 6 7 8 9 0.6 0.2 −0.2 RL = 6.8 kW TJ = 25°C −0.6 −1.0 −50 −40 −30 −20 −10 10 VI, INPUT VOLTAGE (V) 10 20 30 40 50 Figure 15. Input Current vs. Input Voltage 5.5 Iq, QUIESCENT CURRENT (mA) 350 300 250 200 150 100 VQ = 0 V TJ = 25°C 50 0 0 VI, INPUT VOLTAGE (V) Figure 14. Output Voltage vs. Input Voltage IQ, OUTPUT CURRENT (mA) 80 IQ, OUTPUT CURRENT (mA) 4 VQ, OUTPUT VOLTAGE (V) 3.34 0 5 10 15 20 25 30 35 40 45 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 TJ = 25°C RL = 22 W 1.0 0.5 0 0 VI, INPUT VOLTAGE (V) 5 10 15 20 25 30 35 40 VI, INPUT VOLTAGE (V) Figure 17. Quiescent Current vs. Input Voltage Figure 16. Maximum Output Current vs. Input Voltage www.onsemi.com 6 NCV4266−2C TYPICAL CHARACTERISTICS CURVES − 3.3 V Version 0.25 TJ = 25°C VI = 13.5 V 3.0 Iq, QUIESCENT CURRENT (mA) Iq, QUIESCENT CURRENT (mA) 3.5 2.5 2.0 1.5 1.0 0.5 0 0 25 50 75 100 125 150 TJ = 25°C VI = 13.5 V 0.20 0.15 0.10 0.05 0 0 2 4 6 8 10 12 14 16 18 IQ, OUTPUT CURRENT (mA) IQ, OUTPUT CURRENT (mA) Figure 18. Quiescent Current vs. Output Current (High Load) Figure 19. Quiescent Current vs. Output Current (Low Load) www.onsemi.com 7 20 NCV4266−2C Circuit Description The NCV4266−2C is an integrated low dropout regulator that provides a regulated voltage at 150 mA to the output. It is enabled with an input to the enable pin. The regulator voltage is provided by a PNP pass transistor controlled by an error amplifier with a bandgap reference, which gives it the lowest possible dropout voltage. The output current capability is 150 mA, and the base drive quiescent current is controlled to prevent oversaturation when the input voltage is low or when the output is overloaded. The regulator is protected by both current limit and thermal shutdown. Thermal shutdown occurs above 150°C to protect the IC during overloads and extreme ambient temperatures. transient response and loop stability. The capacitor value and type should be based on cost, availability, size and temperature constraints. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (−25°C to −40°C), both the value and ESR of the capacitor will vary considerably. The capacitor manufacturer’s data sheet usually provides this information. The value for the output capacitor CQ, shown in Figure 2, should work for most applications; see also Figures 3 and 12 for output stability at various load and Output Capacitor ESR conditions. Stable region of ESR in Figures 3 and 12 shows ESR values at which the LDO output voltage does not have any permanent oscillations at any dynamic changes of output load current. Marginal ESR is the value at which the output voltage waving is fully damped during five periods after the load change and no oscillation is further observable. ESR characteristics were measured with ceramic capacitors and additional series resistors to emulate ESR. Low duty cycle pulse load current technique has been used to maintain junction temperature close to ambient temperature. Regulator The error amplifier compares the reference voltage to a sample of the output voltage (VQ) and drives the base of a PNP series pass transistor via a buffer. The reference is a bandgap design to give it a temperature−stable output. Saturation control of the PNP is a function of the load current and input voltage. Oversaturation of the output power device is prevented, and quiescent current in the ground pin is minimized. See Figure 2, Test Circuit, for circuit element nomenclature illustration. Enable Input The enable pin is used to turn the regulator on or off. By holding the pin down to a voltage less than 0.8 V, the output of the regulator will be turned off. When the voltage on the enable pin is greater than 2.7 V, the output of the regulator will be enabled to power its output to the regulated output voltage. The enable pin may be connected directly to the input pin to give constant enable to the output regulator. Regulator Stability Considerations The input capacitors (CI1 and CI2) are necessary to stabilize the input impedance to avoid voltage line influences. Using a resistor of approximately 1.0 W in series with CI2 can stop potential oscillations caused by stray inductance and capacitance. The output capacitor helps determine three main characteristics of a linear regulator: startup delay, load www.onsemi.com 8 NCV4266−2C Calculating Power Dissipation in a Single Output Linear Regulator The maximum power dissipation for a single output regulator (Figure 20) is: PD(max) + [VI(max) * VQ(min)] IQ(max) Heatsinks A heatsink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of RqJA: (eq. 1) ) VI(max)Iq where RqJA + RqJC ) RqCS ) RqSA VI(max) VQ(min) IQ(max) is the maximum input voltage, is the minimum output voltage, is the maximum output current for the application, Iq is the quiescent current the regulator consumes at IQ(max). Once the value of PD(max) is known, the maximum permissible value of RqJA can be calculated: o T RqJA + 150 C * A PD where RqJC is the junction−to−case thermal resistance, RqCS is the case−to−heatsink thermal resistance, RqSA is the heatsink−to−ambient thermal resistance. RqJC appears in the package section of the data sheet. Like RqJA, it too is a function of package type. RqCS and RqSA are functions of the package type, heatsink and the interface between them. These values appear in data sheets of heatsink manufacturers. Thermal, mounting, and heatsinking considerations are discussed in the ON Semiconductor application note AN1040/D. (eq. 2) The value of RqJA can then be compared with those in the package section of the data sheet. Those packages with RqJA less than the calculated value in Equation 2 will keep the die temperature below 150°C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required. IQ II VI SMART REGULATOR® (eq. 3) VQ } Control Features Iq Figure 20. Single Output Regulator with Key Performance Parameters Labeled www.onsemi.com 9 RqJA, THERMAL RESISTANCE (C°/W) NCV4266−2C 180 160 140 120 100 1 oz 80 2 oz 60 40 0 100 200 300 400 500 COPPER HEAT SPREADER AREA 600 700 (mm2) Figure 21. RqJA vs. Copper Spreader Area, SOT−223 1000 Cu Area 100 mm2, 1 oz. R(t) (C°/W) 100 10 1 0.1 0.000001 0.00001 0.0001 0.001 0.01 0.1 PULSE TIME (sec) 1 10 100 1000 Figure 22. Single−Pulse Heating Curve, SOT−223 ORDERING INFORMATION Output Voltage Package Shipping† NCV4266−2CST33T3G 3.3 V SOT−223 (Pb−Free) 4000 / Tape & Reel NCV4266−2CST50T3G 5.0 V SOT−223 (Pb−Free) 4000 / Tape & Reel Device* †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. www.onsemi.com 10 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOT−223 (TO−261) CASE 318E−04 ISSUE R DATE 02 OCT 2018 SCALE 1:1 q q DOCUMENT NUMBER: DESCRIPTION: 98ASB42680B SOT−223 (TO−261) Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2018 www.onsemi.com SOT−223 (TO−261) CASE 318E−04 ISSUE R STYLE 1: PIN 1. 2. 3. 4. BASE COLLECTOR EMITTER COLLECTOR STYLE 2: PIN 1. 2. 3. 4. ANODE CATHODE NC CATHODE STYLE 6: PIN 1. 2. 3. 4. RETURN INPUT OUTPUT INPUT STYLE 7: PIN 1. 2. 3. 4. ANODE 1 CATHODE ANODE 2 CATHODE STYLE 11: PIN 1. MT 1 2. MT 2 3. GATE 4. MT 2 STYLE 3: PIN 1. 2. 3. 4. GATE DRAIN SOURCE DRAIN STYLE 8: STYLE 12: PIN 1. INPUT 2. OUTPUT 3. NC 4. OUTPUT CANCELLED DATE 02 OCT 2018 STYLE 4: PIN 1. 2. 3. 4. SOURCE DRAIN GATE DRAIN STYLE 5: PIN 1. 2. 3. 4. STYLE 9: PIN 1. 2. 3. 4. INPUT GROUND LOGIC GROUND STYLE 10: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE DRAIN GATE SOURCE GATE STYLE 13: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR GENERIC MARKING DIAGRAM* AYW XXXXXG G 1 A = Assembly Location Y = Year W = Work Week XXXXX = Specific Device Code G = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98ASB42680B SOT−223 (TO−261) Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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