NCV4276B
400 mA Low‐Drop Voltage
Regulator
The NCV4276B is a 400 mA output current integrated low dropout
regulator family designed for use in harsh automotive environments.
It includes wide operating temperature and input voltage ranges. The
device is offered with 3.3 V, 5.0 V, and adjustable voltage versions
available in 2% output voltage accuracy. It has a high peak input
voltage tolerance and reverse input voltage protection. It also
provides overcurrent protection, overtemperature protection and
inhibit for control of the state of the output voltage. The NCV4276B
family is available in DPAK and D2PAK surface mount packages.
The output is stable over a wide output capacitance and ESR range.
The NCV4276B has improved startup behavior during input voltage
transients.
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D2PAK
CASE 936A
DPAK
CASE 175AA
MARKING DIAGRAMS
Features
• 3.3 V, 5.0 V, and Adjustable Voltage Version (from 2.5 V to 20 V)
•
•
•
•
•
•
•
±2% Output Voltage
400 mA Output Current
500 mV (max) Dropout Voltage (5.0 V Output)
Inhibit Input
Very Low Current Consumption
Fault Protection
♦ +45 V Peak Transient Voltage
♦ −42 V Reverse Voltage
♦ Short Circuit
♦ Thermal Overload
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements
These are Pb-Free Devices
76BXXG
ALYWW
1
DPAK
5-PIN
NC
V4276B−XX
AWLYWWG
1
D2PAK
5-PIN
*Tab is connected to Pin 3 on all packages.
A
WL, L
Y
WW
G
XX
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb-Free Device
= 33 (3.3 V)
= 50 (5.0 V)
= AJ (Adj. Voltage)
ORDERING INFORMATION
See detailed ordering and shipping information in the ordering
information section on page 16 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 6
1
Publication Order Number:
NCV4276B/D
NCV4276B
I
Q
Error
Amplifier
Bandgap
Reference
Current Limit and
Saturation Sense
−
+
Thermal
Shutdown
INH
GND
NC
Figure 1. NCV4276B Block Diagram
I
Q
Error
Amplifier
Bandgap
Reference
Current Limit and
Saturation Sense
−
+
Thermal
Shutdown
INH
GND
VA
Figure 2. NCV4276B Adjustable Block Diagram
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NCV4276B
Table 1. PIN FUNCTION DESCRIPTION
Pin No.
Symbol
Description
1
I
2
INH
Input; Battery Supply Input Voltage.
Inhibit; Set low-to inhibit.
3
GND
Ground; Pin 3 internally connected to heatsink.
4
NC/VA
Not connected for fixed voltage version/Voltage Adjust Input for adjustable voltage version; use an external
voltage divider to set the output voltage
5
Q
Output: Bypass with a capacitor to GND. See Figures 3 to 7 and Regulator Stability Considerations section.
Table 2. MAXIMUM RATINGS*
Rating
Symbol
Min
Max
Unit
VI
−42
45
V
Input Voltage
Input Peak Transient Voltage
VI
−
45
V
Inhibit INH Voltage
VINH
−42
45
V
Voltage Adjust Input VA
VVA
−0.3
10
V
Output Voltage
VQ
−1.0
40
V
Ground Current
Iq
−
100
mA
Input Voltage Operating Range
VI
VQ + 0.5 V or 4.5 V
(Note 1)
40
V
−
−
−
4.0
250
1.25
−
−
−
kV
V
kV
Junction Temperature
TJ
−40
150
°C
Storage Temperature
Tstg
−50
150
°C
ESD Susceptibility
(Human Body Model)
(Machine Model)
(Charged Device Model)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
*During the voltage range which exceeds the maximum tested voltage of I, operation is assured, but not specified. Wider limits may apply. Thermal
dissipation must be observed closely.
1. Minimum VI = 4.5 V or (VQ + 0.5 V), whichever is higher.
Table 3. LEAD TEMPERATURE SOLDERING REFLOW (Note 2)
Lead Temperature Soldering
Reflow (SMD styles only), Leaded, 60−150 s above 183, 30 s max at peak
Reflow (SMD styles only), Lead Free, 60−150 s above 217, 40 s max at peak
Wave Solder (through hole styles only), 12 sec max
°C
TSLD
−
−
−
240
265
310
2. Per IPC/JEDEC J−STD−020C.
Table 4. THERMAL CHARACTERISTICS (Notes 3 and 4)
Characteristic
Test Conditions (Typical Value)
Unit
DPAK 5-PIN PACKAGE
Min Pad Board (Note 5)
1, Pad Board (Note 6)
Junction-to-Tab (psi-JLx, yJLx)
4.2
4.7
C/W
Junction-to-Ambient (RqJA, qJA)
100.9
46.8
C/W
0.4 sq. in. Spreader Board (Note 7)
1.2 sq. in. Spreader Board (Note 8)
Junction-to-Tab (psi-JLx, yJLx)
3.8
4.0
C/W
Junction-to-Ambient (RqJA, qJA)
74.8
41.6
C/W
D2PAK
3.
4.
5.
6.
7.
8.
5-PIN PACKAGE
Minimum VI = 4.5 V or (VQ + 0.5 V), whichever is higher.
Per IPC/JEDEC J−STD−020C.
1 oz. copper, 0.26 inch2 (168 mm2) copper area, 0.062″ thick FR4.
1 oz. copper, 1.14 inch2 (736 mm2) copper area, 0.062″ thick FR4.
1 oz. copper, 0.373 inch2 (241 mm2) copper area, 0.062″ thick FR4.
1 oz. copper, 1.222 inch2 (788 mm2) copper area, 0.062″ thick FR4.
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NCV4276B
Table 5. ELECTRICAL CHARACTERISTICS (VI = 13.5 V; −40°C < TJ < 150°C; unless otherwise noted.)
NCV4276B
Characteristic
Symbol
Test Conditions
Min
Typ
Max
Unit
OUTPUT
Output Voltage, 5.0 V Version
VQ
5.0 mA < IQ < 400 mA,
6.0 V < VI < 28 V
4.9
5.0
5.1
V
Output Voltage, 5.0 V Version
VQ
5.0 mA < IQ < 200 mA,
6.0 V < VI < 40 V
4.9
5.0
5.1
V
Output Voltage, 3.3 V Version
VQ
5.0 mA < IQ < 400 mA,
4.5 V < VI < 28 V
3.234
3.3
3.366
V
Output Voltage, 3.3 V Version
VQ
5.0 mA < IQ < 200 mA,
4.5 V < VI < 40 V
3.234
3.3
3.366
V
AVQ
5.0 mA < IQ < 400 mA
VQ+1 < VI < 40 V
VI > 4.5 V
−2%
−
+2%
V
Output Voltage, Adjustable
Version
Output Current Limitation
IQ
VQ = 90% VQTYP (VQTYP = 2.5 V for ADJ Version)
400
700
1100
mA
Quiescent Current (Sleep Mode)
Iq = II − IQ
Iq
VINH = 0 V
−
−
10
mA
Quiescent Current, Iq = II − IQ
Iq
IQ = 1.0 mA
−
130
200
mA
Quiescent Current, Iq = II − IQ
Iq
IQ = 250 mA
−
10
15
mA
Quiescent Current, Iq = II − IQ
Iq
IQ = 400 mA
−
25
35
mA
IQ = 250 mA, VDR = VI − VQ
VI > 4.5 V
−
250
500
mV
IQ = 250 mA (Note 9)
−
250
500
mV
IQ = 5.0 mA to 400 mA
−
3.0
20
mV
DVI = 12 V to 32 V,
IQ = 5.0 mA
−
4.0
15
mV
−
70
−
dB
−
0.5
−
mV/K
2.8
V
Dropout Voltage,
Adjustable Version
Dropout Voltage (5.0 V Version)
VDR
VDR
Load Regulation
DVQ,LO
Line Regulation
DVQ
Power Supply Ripple Rejection
PSRR
Temperature Output Voltage Drift
dVQ/dT
fr = 100 Hz, Vr = 0.5 VPP
−
INHIBIT
Inhibit Voltage, Output High
VINH
VQ w VQMIN
−
2.3
Inhibit Voltage, Output Low (Off)
VINH
VQ v 0.1 V
1.8
2.2
−
V
Input Current
IINH
VINH = 5.0 V
5.0
10
20
mA
TSD
IQ = 5.0 mA
150
−
210
°C
THERMAL SHUTDOWN
Thermal Shutdown Temperature*
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
*Guaranteed by design, not tested in production.
9. Measured when the output voltage VQ has dropped 100 mV from the nominal valued obtained at V = 13.5 V.
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NCV4276B
II
5.5 − 45 V
Input
CI1
1.0 mF
I 1
CI2
100 nF
CQ
22 mF
NCV4276B
INH
2
IINH
4
3
Output
IQ
5 Q
NC
RL
GND
Figure 3. Applications Circuit; Fixed Voltage Version
VQ = [(R1 + R2) * Vref] / R2
II
Input
CI1
1.0 mF
I 1
CI2
100 nF
2
4
3
Output
IQ
CQ
22 mF
NCV4276B
INH
IINH
5 Q
Cb*
R1
VA
GND
RL
R2
Cb* − Required if usage of low ESR output capacitor CQ is demand, see Regulator Stability Considerations section
Figure 4. Applications Circuit; Adjustable Voltage Version
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NCV4276B
TYPICAL PERFORMANCE CHARACTERISTICS
10
CQ = 22 mF for all
Fixed Output Voltages
Unstable Region
ESR (W)
1
Maximum ESR
for CQ = 22 mF
Stable Region
0.1
0.01
0
50
100
300
150 200
250
IQ, OUTPUT CURRENT (mA)
350
400
Figure 5. Output Stability with Output Capacitor
ESR, 5.0 V and 3.3 V Regulator
10
CQ = 10 mF for 3.3 V and
5 V Fixed Output Voltages
Unstable Region
ESR (W)
1
Maximum ESR
for CQ = 10 mF
Stable Region
0.1
0.01
0
50
100
150 200
250
300
IQ, OUTPUT CURRENT (mA)
350
400
Figure 6. Output Stability with Output Capacitor
ESR, 5.0 V and 3.3 V Regulator
100
CQ = 22 mF for these
Output Voltages
Unstable Region
ESR (W)
10
1
2.5 V
Stable Region
6V
12 V
0.1
Unstable Region
Cb capacitor not connected
0.01
0
50
100
150 200
250
300
IQ, OUTPUT CURRENT (mA)
350
400
Figure 7. Output Stability with Output Capacitor
ESR, Adjustable Regulator
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NCV4276B
TYPICAL PERFORMANCE CHARACTERISTICS − 4276B Version
3.45
VI = 13.5 V
RL = 1 kW
VQ, OUTPUT VOLTAGE (V)
VQ, OUTPUT VOLTAGE (V)
5.2
5.1
5.0
4.9
4.8
−40
0
40
80
120
3.35
3.30
3.25
3.20
3.15
−40
160
0
80
120
TJ, JUNCTION TEMPERATURE (°C)
Figure 8. Output Voltage vs.
Junction Temperature, 5.0 V Version
Figure 9. Output Voltage vs.
Junction Temperature, 3.3 V Version
10
Iq, CURRENT CONSUMPTION (mA)
TJ = 25°C
RL = 20 W
30
20
10
160
RL = 20 W
TJ = 25°C
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0
0
0
10
20
30
40
0
50
10
Figure 10. Current Consumption vs.
Input Voltage, 5.0 V Version
30
40
50
Figure 11. Current Consumption vs. Input
Voltage, 3.3 V Version
6.0
5.0
5.0
VQ, OUTPUT VOLTAGE (V)
6.0
RL = 20 W
TJ = 25°C
4.0
20
VI, INPUT VOLTAGE (V)
VI, INPUT VOLTAGE (V)
VQ, OUTPUT VOLTAGE (V)
40
TJ, JUNCTION TEMPERATURE (°C)
40
Iq, CURRENT CONSUMPTION (mA)
VI = 13.5 V
RL = 1 kW
3.40
3.0
2.0
1.0
TJ = 25°C
RL = 20 W
4.0
3.0
2.0
1.0
0
0
0
2.0
4.0
6.0
8.0
0
10
1.0
2.0
3.0
4.0
5.0
VI, INPUT VOLTAGE (V)
VI, INPUT VOLTAGE (V)
Figure 12. Low Voltage Behavior, 5.0 V Version
Figure 13. Low Voltage Behavior, 3.3 V Version
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6.0
NCV4276B
TYPICAL PERFORMANCE CHARACTERISTICS − 4276B Version
2.0
6.0
II, INPUT CURRENT (mA)
II, INPUT CURRENT (mA)
4.0
2.0
0
−2.0
−4.0
−6.0
−10
−50
−25
0
25
−6.0
RL = 6.8 kW
TJ = 25°C
−25
0
25
50
VI, INPUT VOLTAGE (V)
VI, INPUT VOLTAGE (V)
Figure 14. Input Current vs. Input Voltage,
5.0 V Version
Figure 15. Input Current vs. Input Voltage,
3.3 V Version
800
IQ, OUTPUT CURRENT (mA)
VDR, DROP VOLTAGE (mV)
−4.0
−10
−50
50
600
500
TJ = 125°C
400
300
TJ = 25°C
200
100
0
TJ = 25°C
VQ = 0 V
600
400
200
0
0
100
200
300
400
0
10
20
30
40
IQ, OUTPUT CURRENT (mA)
VI, INPUT VOLTAGE (V)
Figure 16. Dropout Voltage vs.
Output Current
Figure 17. Maximum Output Current vs.
Input Voltage
50
1.6
Iq, CURRENT CONSUMPTION (mA)
60
Iq, CURRENT CONSUMPTION (mA)
−2.0
−8.0
RL = 6.8 kW
TJ = 25°C
−8.0
0
50
VI = 13.5 V
TJ = 25°C
40
30
20
10
0
1.4
VI = 13.5 V
TJ = 25°C
1.2
1.0
0.8
0.6
0.4
0.2
0
0
100
200
300
400
500
600
0
10
20
30
40
50
IQ, OUTPUT CURRENT (mA)
IQ, OUTPUT CURRENT (mA)
Figure 18. Current Consumption vs.
Output Current (High Load)
Figure 19. Current Consumption vs.
Output Current (Low Load)
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NCV4276B
TYPICAL PERFORMANCE CHARACTERISTICS − Adjustable Version
5.0
2.54
Iq, CURRENT CONSUMPTION (mA)
VQ, OUTPUT VOLTAGE (V)
2.55
VI = 13.5 V
TJ = 25°C
2.53
2.52
2.51
2.50
2.49
2.48
2.47
2.46
2.45
−40
0
40
80
120
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
160
TJ, JUNCTION TEMPERATURE (°C)
0
20
30
VI, INPUT VOLTAGE (V)
Figure 20. Output Voltage vs. Junction
Temperature, Adjustable Version
Figure 21. Current Consumption vs. Input
Voltage, Adjustable Version
4
10
40
50
2
TJ = 25°C
RL = 20 W
3.5
0
II, INPUT CURRENT (mA)
VQ, OUTPUT VOLTAGE (V)
TJ = 25°C
RL = 20 W
4.5
3
2.5
2
1.5
1
−2
−4
−6
−8
−10
−12
TJ = 25°C
RL = 6.8 kW
−14
0.5
−16
−18
−50
0
0
2
4
6
VI, INPUT VOLTAGE (V)
8
10
−25
0
25
VI, INPUT VOLTAGE (V)
Figure 22. Low Voltage Behavior,
Adjustable Version
Figure 23. High Voltage Behavior,
Adjustable Version
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50
NCV4276B
TYPICAL PERFORMANCE CHARACTERISTICS − Adjustable Version
800
500
TJ = 125°C
400
300
TJ = 25°C
200
100
IQ, OUTPUT CURRENT (mA)
VDR, DROPOUT VOLTAGE (mV)
600
700
600
500
TJ = 25°C
VQ = 0 V
400
300
200
100
0
0
0
50
100
150 200
250 300
IQ, OUTPUT CURRENT (mA)
350 400
0
Figure 24. Dropout Voltage vs. Output Current,
Regulator Set at 5.0 V, Adjustable Version
20
30
VI, INPUT VOLTAGE (V)
40
50
Figure 25. Maximum Output Current vs.
Input Voltage, Adjustable Version
60
1.6
Iq, CURRENT CONSUMPTION (mA)
Iq, CURRENT CONSUMPTION (mA)
10
TJ = 25°C
VI = 13.5 V
50
40
30
20
10
0
0
100
200
300
400
500
TJ = 25°C
VI = 13.5 V
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
600
0
10
20
30
40
50
IQ, OUTPUT CURRENT (mA)
IQ, OUTPUT CURRENT (mA)
Figure 26. Current Consumption vs.
Output Current (High Load), Adjustable Version
Figure 27. Current Consumption vs. Output
Current (Low Load), Adjustable Version
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NCV4276B
Minimum ESR for CQ = 22 mF is native ESR of ceramic
capacitor with which the fixed output voltage devices are
performing stable. Murata ceramic capacitors were used,
Circuit Description
The NCV4276B is an integrated low dropout regulator
that provides a regulated voltage at 400 mA to the output.
It is enabled with an input to the inhibit pin. The regulator
voltage is provided by a PNP pass transistor controlled by
an error amplifier with a bandgap reference, which gives it
the lowest possible dropout voltage. The output current
capability is 400 mA, and the base drive quiescent current
is controlled to prevent oversaturation when the input
voltage is low or when the output is overloaded. The
regulator is protected by both current limit and thermal
shutdown. Thermal shutdown occurs above 150°C to
protect the IC during overloads and extreme ambient
temperatures.
GRM32ER71C226KE18 (22 mF, 16 V, X7R, 1210),
GRM31CR71C106KAC7 (10 mF, 16 V, X7R, 1206).
Calculating Bypass Capacitor
If usage of low ESR ceramic capacitors is demand in case
of Adjustable Regulator, connect the bypass capacitor Cb
between Voltage Adjust pin and Q pin according to
Applications circuit at Figure 4.
Parallel combination of bypass capacitor Cb with the
feedback resistor R1 contributes in the device transfer
function as an additional zero and affects the device loop
stability, therefore its value must be optimized. Attention
to the Output Capacitor value and its ESR must be paid. See
also Stability in High Speed Linear LDO Regulators
Application Note, AND8037/D for more information.
Optimal value of bypass capacitor is given by following
expression
Regulator
The error amplifier compares the reference voltage to a
sample of the output voltage (VQ) and drives the base of a
PNP series pass transistor via a buffer. The reference is a
bandgap design to give it a temperature-stable output.
Saturation control of the PNP is a function of the load
current and input voltage. Oversaturation of the output
power device is prevented, and quiescent current in the
ground pin is minimized. See Figure 4, Test Circuit, for
circuit element nomenclature illustration.
Cb +
2
p
1
fz
R1
@ (F)
(eq. 1)
where
R1 = the upper feedback resistor
fz = the frequency of the zero added into the device
transfer function by R1 and Cb external components.
Regulator Stability Considerations
The input capacitors (CI1 and CI2) are necessary to
stabilize the input impedance to avoid voltage line
influences. Using a resistor of approximately 1.0 W in
series with CI2 can stop potential oscillations caused by
stray inductance and capacitance.
The output capacitor helps determine three main
characteristics of a linear regulator: startup delay, load
transient response and loop stability. The capacitor value
and type should be based on cost, availability, size and
temperature constraints. The aluminum electrolytic
capacitor is the least expensive solution, but, if the circuit
operates at low temperatures (−25°C to −40°C), both the
value and ESR of the capacitor will vary considerably. The
capacitor manufacturer’s data sheet usually provides this
information.
The value for the output capacitor CQ, shown in Figure 3,
should work for most applications; see also Figures 5 to 7
for output stability at various load and Output Capacitor
ESR conditions. Stable region of ESR in Figures 5 to 7
shows ESR values at which the LDO output voltage does
not have any permanent oscillations at any dynamic
changes of output load current. Marginal ESR is the value
at which the output voltage waving is fully damped during
four periods after the load change and no oscillation is
further observable.
ESR characteristics were measured with ceramic
capacitors and additional series resistors to emulate ESR.
Low duty cycle pulse load current technique has been used
to maintain junction temperature close to ambient
temperature.
Set the R1 resistor according to output voltage
requirement. Chose the fz with regard on the output
capacitance CQ, refer to the table below.
CQ (mF)
10
22
47
100
fz Range (kHz)
20 - 50
14 - 35
10 - 20
7 – 14
Ceramic capacitors and its part numbers listed bellow
have been used as low ESR output capacitors CQ from the
table above to define the frequency ranges of additional
zero required for stability.
GRM31CR71C106KAC7 (10 mF, 16 V, X7R, 1206)
GRM32ER71C226KE18 (22 mF, 16 V, X7R, 1210)
GRM32ER61C476ME15 (47 mF, 16 V, X5R, 1210)
GRM32ER60J107ME20 (100 mF, 6.3 V, X5R, 1210)
Inhibit Input
The inhibit pin is used to turn the regulator on or off. By
holding the pin down to a voltage less than 1.8 V, the output
of the regulator will be turned off. When the voltage on the
Inhibit pin is greater than 2.8 V, the output of the regulator
will be enabled to power its output to the regulated output
voltage. The inhibit pin may be connected directly to the
input pin to give constant enable to the output regulator.
Setting the Output Voltage (Adjustable Version)
The output voltage range of the adjustable version can be
set between 2.5 V and 20 V. This is accomplished with an
external resistor divider feeding back the voltage to the IC
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NCV4276B
back to the error amplifier by the voltage adjust pin VA.
The internal reference voltage is set to a temperature stable
reference of 2.5 V.
The output voltage is calculated from the following
formula. Ignoring the bias current into the VA pin:
VQ + [(R1 ) R2) * Vref] ń R2
(eq. 2)
Iq
Figure 28. Single Output Regulator with Key
Performance Parameters Labeled
Heatsinks
A heatsink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
Each material in the heat flow path between the IC and
the outside environment will have a thermal resistance.
Like series electrical resistances, these resistances are
summed to determine the value of RqJA:
RqJA + RqJC ) RqCS ) RqSA
The maximum power dissipation for a single output
regulator (Figure 28) is:
(eq. 5)
where:
RqJC is the junction-to-case thermal resistance,
RqCS is the case-to-heatsink thermal resistance,
RqSA is the heatsink-to-ambient thermal resistance.
(eq. 3)
where:
VI(max)
VQ(min)
IQ(max)
RqJC appears in the package section of the data sheet.
Like RqJA, it too is a function of package type. RqCS and
RqSA are functions of the package type, heatsink and the
interface between them. These values appear in data sheets
of heatsink manufacturers.
Thermal, mounting, and heatsinking considerations are
discussed in the ON Semiconductor application note
AN1040/D.
is the maximum input voltage,
is the minimum output voltage,
is the maximum output current for the
application,
Iq
is the quiescent current the regulator
consumes at IQ(max).
Once the value of PD(max) is known, the maximum
permissible value of RqJA can be calculated:
o
T
RqJA + 150 C * A
PD
VQ
Control
Features
Calculating Power Dissipation
in a Single Output Linear Regulator
) VI(max)Iq
SMART
REGULATOR
VI
Use R2 < 50 k to avoid significant voltage output errors
due to VA bias current.
Connecting VA directly to Q without R1 and R2 creates
an output voltage of 2.5 V.
Designers should consider the tolerance of R1 and R2
during the design phase.
The input voltage range for operation (pin 1) of the
adjustable version is between (VQ + 0.5 V) and 40 V.
Internal bias requirements dictate a minimum input voltage
of 4.5 V. The dropout voltage for output voltages less than
4.0 V is (4.5 V − VQ).
PD(max) + [VI(max) * VQ(min)] IQ(max) )
IQ
II
Thermal Model
(eq. 4)
See pages 13 to 16 for detailed information about thermal
model parameters.
The value of RqJA can then be compared with those in the
package section of the data sheet. Those packages with
RqJA less than the calculated value in Equation 4 will keep
the die temperature below 150°C.
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external
heatsink will be required.
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12
NCV4276B
Table 6. DPAK 5-LEAD THERMAL RC NETWORK MODELS
Drain Copper Area (1 oz thick)
168 mm2
(SPICE Deck Format)
736 mm2
168 mm2
Cauer Network
736 mm2
Foster Network
168 mm2
736 mm2
Units
Tau
Tau
Units
C_C1
Junction
GND
1.00E−06
1.00E−06
W−s/C
1.36E−08
1.361E−08
sec
C_C2
node1
GND
1.00E−05
1.00E−05
W−s/C
7.41E−07
7.411E−07
sec
C_C3
node2
GND
6.00E−05
6.00E−05
W−s/C
1.04E−05
1.029E−05
sec
C_C4
node3
GND
1.00E−04
1.00E−04
W−s/C
3.91E−05
3.737E−05
sec
C_C5
node4
GND
4.36E−04
3.64E−04
W−s/C
1.80E−03
1.376E−03
sec
C_C6
node5
GND
6.77E−02
1.92E−02
W−s/C
3.77E−01
2.851E−02
sec
C_C7
node6
GND
1.51E−01
1.27E−01
W−s/C
3.79E+00
9.475E−01
sec
C_C8
node7
GND
4.80E−01
1.018
W−s/C
2.65E+01
1.173E+01
sec
C_C9
node8
GND
3.740
2.955
W−s/C
8.71E+01
8.59E+01
sec
C_C10
node9
GND
10.322
0.438
W−s/C
168 mm2
736 mm2
sec
R’s
R’s
R_R1
Junction
node1
0.015
0.015
C/W
0.0123
0.0123
C/W
R_R2
node1
node2
0.08
0.08
C/W
0.0585
0.0585
C/W
R_R3
node2
node3
0.4
0.4
C/W
0.0304
0.0287
C/W
R_R4
node3
node4
0.2
0.2
C/W
0.3997
0.3772
C/W
R_R5
node4
node5
2.97519
2.6171
C/W
3.115
2.68
C/W
R_R6
node5
node6
8.2971
1.6778
C/W
3.571
1.38
C/W
R_R7
node6
node7
25.9805
7.4246
C/W
12.851
5.92
C/W
R_R8
node7
node8
46.5192
14.9320
C/W
35.471
7.39
C/W
R_R9
node8
node9
17.7808
19.2560
C/W
46.741
28.94
C/W
R_R10
node9
GND
0.1
0.1758
C/W
NOTE:
C/W
Bold face items represent the package without the external thermal system.
R1
Junction
C1
R2
C2
R3
C3
Rn
Cn
Time constants are not simple RC products. Amplitudes
of mathematical solution are not the resistance values.
Ambient
(thermal ground)
Figure 29. Grounded Capacitor Thermal Network (“Cauer” Ladder)
Junction
R1
C1
R2
C2
R3
C3
Each rung is exactly characterized by its RC-product
time constant; amplitudes are the resistances.
Rn
Cn
Ambient
(thermal ground)
Figure 30. Non-Grounded Capacitor Thermal Ladder (“Foster” Ladder)
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13
NCV4276B
Table 7. D2PAK 5-LEAD THERMAL RC NETWORK MODELS
Drain Copper Area (1 oz thick)
241 mm2
(SPICE Deck Format)
788 mm2
241 mm2
Cauer Network
788 mm2
Foster Network
241 mm2
653 mm2
Units
Tau
Tau
Units
C_C1
Junction
GND
1.00E−06
1.00E−06
W−s/C
1.361E−08
1.361E−08
sec
C_C2
node1
GND
1.00E−05
1.00E−05
W−s/C
7.411E−07
7.411E−07
sec
C_C3
node2
GND
6.00E−05
6.00E−05
W−s/C
1.005E−05
1.007E−05
sec
C_C4
node3
GND
1.00E−04
1.00E−04
W−s/C
3.460E−05
3.480E−05
sec
C_C5
node4
GND
2.82E−04
2.87E−04
W−s/C
7.868E−04
8.107E−04
sec
C_C6
node5
GND
5.58E−03
5.95E−03
W−s/C
7.431E−03
7.830E−03
sec
C_C7
node6
GND
4.25E−01
4.61E−01
W−s/C
2.786E+00
2.012E+00
sec
C_C8
node7
GND
9.22E−01
2.05
W−s/C
2.014E+01
2.601E+01
sec
C_C9
node8
GND
1.73
4.88
W−s/C
1.134E+02
1.218E+02
sec
C_C10
node9
GND
7.12
1.31
W−s/C
241 mm2
653 mm2
sec
R’s
R’s
R_R1
Junction
node1
0.015
0.0150
C/W
0.0123
0.0123
C/W
R_R2
node1
node2
0.08
0.0800
C/W
0.0585
0.0585
C/W
R_R3
node2
node3
0.4
0.4000
C/W
0.0257
0.0260
C/W
R_R4
node3
node4
0.2
0.2000
C/W
0.3413
0.3438
C/W
R_R5
node4
node5
1.85638
1.8839
C/W
1.77
1.81
C/W
R_R6
node5
node6
1.23672
1.2272
C/W
1.54
1.52
C/W
R_R7
node6
node7
9.81541
5.3383
C/W
4.13
3.46
C/W
R_R8
node7
node8
33.1868
18.9591
C/W
6.27
5.03
C/W
R_R9
node8
node9
27.0263
13.3369
C/W
60.80
29.30
C/W
R_R10
node9
GND
1.13944
0.1191
C/W
NOTE:
C/W
Bold face items represent the package without the external thermal system.
The Cauer networks generally have physical
significance and may be divided between nodes to separate
thermal behavior due to one portion of the network from
another. The Foster networks, though when sorted by time
constant (as above) bear a rough correlation with the Cauer
networks, are really only convenient mathematical models.
Cauer networks can be easily implemented using circuit
simulating tools, whereas Foster networks may be more
easily implemented using mathematical tools (for instance,
in a spreadsheet program), according to the following
formula:
n
R(t) +
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14
S Ri ǒ1−e−tńtaui Ǔ
i+1
(eq. 6)
110
110
100
100
90
90
80
80
70
qJA (C°/W)
qJA (C°/W)
NCV4276B
1 oz
60
2 oz
70
60
1 oz
2 oz
50
50
40
40
30
150 200 250 300 350 400 450 500 550 600 650 700 750
30
150 200 250 300 350 400 450 500 550 600 650 700 750
COPPER AREA (mm2)
COPPER AREA (mm2)
Figure 31. qJA vs. Copper Spreader Area,
DPAK 5-Lead
Figure 32. qJA vs. Copper Spreader Area,
D2PAK 5-Lead
100
Cu Area 167 mm2
Cu Area 736 mm2
R(t) C°/W
10
1.0
sqrt(t)
0.1
0.01
0.0000001
0.000001
0.00001
0.0001
0.001
0.01
0.1
1.0
10
100
1000
TIME (sec)
Figure 33. Single-Pulse Heating Curves, DPAK 5-Lead
100
Cu Area 167 mm2
Cu Area 736 mm2
R(t) C°/W
10
1.0
0.1
0.01
0.0000001
0.000001
0.00001
0.0001
0.001
0.01
0.1
1.0
TIME (sec)
Figure 34. Single-Pulse Heating Curves, D2PAK 5-Lead
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15
10
100
1000
NCV4276B
100
50% Duty Cycle
RqJA 736 mm2 C°/W
20%
10
1.0
10%
5%
2%
1%
0.1
Non−normalized Response
0.01
0.0000001
0.000001
0.00001
0.0001
0.001
0.01
0.1
1.0
10
100
1000
10
100
1000
PULSE WIDTH (sec)
Figure 35. Duty Cycle for 1, Spreader Boards, DPAK 5-Lead
100
RqJA 788 mm2 C°/W
50% Duty Cycle
10
20%
10%
5%
1.0
2%
1%
0.1
Non−normalized Response
0.01
0.0000001
0.000001
0.00001
0.0001
0.001
0.01
0.1
1.0
PULSE WIDTH (sec)
Figure 36. Duty Cycle for 1, Spreader Boards, D2PAK 5-Lead
Table 8. ORDERING INFORMATION
Device
Output Voltage Accuracy
Output Voltage
NCV4276BDT33RKG
3.3 V
NCV4276BDS33R4G
NCV4276BDT50RKG
NCV4276BDS50R4G
2%
5.0 V
NCV4276BDTADJRKG
NCV4276BDSADJR4G
Adjustable
Package
Shipping†
DPAK, 5-Pin
(Pb-Free)
2,500 / Tape & Reel
D2PAK, 5-Pin
(Pb-Free)
800 / Tape & Reel
DPAK, 5-Pin
(Pb-Free)
2,500 / Tape & Reel
D2PAK, 5-Pin
(Pb-Free)
800 / Tape & Reel
DPAK, 5-Pin
(Pb-Free)
2,500 / Tape & Reel
D2PAK, 5-Pin
(Pb-Free)
800 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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16
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DPAK−5, CENTER LEAD CROP
CASE 175AA
ISSUE B
DATE 15 MAY 2014
SCALE 1:1
−T−
C
B
V
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
SEATING
PLANE
E
R
R1
Z
A
S
12 3 4 5
U
K
F
J
L
H
D
G
5 PL
0.13 (0.005)
M
T
2.2
0.086
0.34 5.36
0.013 0.217
5.8
0.228
10.6
0.417
0.8
0.031
SCALE 4:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON12855D
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.020 0.028
0.018 0.023
0.024 0.032
0.180 BSC
0.034 0.040
0.018 0.023
0.102 0.114
0.045 BSC
0.170 0.190
0.185 0.210
0.025 0.040
0.020
−−−
0.035 0.050
0.155 0.170
MILLIMETERS
MIN
MAX
5.97
6.22
6.35
6.73
2.19
2.38
0.51
0.71
0.46
0.58
0.61
0.81
4.56 BSC
0.87
1.01
0.46
0.58
2.60
2.89
1.14 BSC
4.32
4.83
4.70
5.33
0.63
1.01
0.51
−−−
0.89
1.27
3.93
4.32
GENERIC
MARKING DIAGRAMS*
RECOMMENDED
SOLDERING FOOTPRINT*
6.4
0.252
DIM
A
B
C
D
E
F
G
H
J
K
L
R
R1
S
U
V
Z
XXXXXXG
ALYWW
AYWW
XXX
XXXXXG
IC
Discrete
XXXXXX
A
L
Y
WW
G
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DPAK−5 CENTER LEAD CROP
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
D2PAK 5−LEAD
CASE 936A−02
ISSUE E
DATE 28 JUL 2021
SCALE 1:1
GENERIC
MARKING DIAGRAM*
xx
xxxxxxxxx
AWLYWWG
xxxxxx
A
WL
Y
WW
G
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98ASH01006A
D2PAK 5−LEAD
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
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