NCV4276C
Voltage Regulator Low-Drop
400 mA
The NCV4276C is a 400 mA output current integrated low dropout
regulator family designed for use in harsh automotive environments.
It includes wide operating temperature and input voltage ranges. The
device is offered with 3.3 V, 5.0 V, and adjustable voltage versions
available in 2% output voltage accuracy. It has a high peak input
voltage tolerance and reverse input voltage protection. It also
provides overcurrent protection, overtemperature protection and
inhibit for control of the state of the output voltage. The NCV4276C
family is available in DPAK and D2PAK surface mount packages.
The output is stable over a wide output capacitance and ESR range.
The NCV4276C has improved startup behavior during input voltage
transients.
The NCV4276C is pin for pin compatible with NCV4276B.
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MARKING
DIAGRAMS
1
DPAK
5−PIN
DT SUFFIX
CASE 175AA
5
1
D2PAK
5−PIN
DS SUFFIX
CASE 936A
Features
• 3.3 V, 5.0 V, and Adjustable Voltage Version (from 2.5 V to 20 V)
•
•
•
•
•
•
•
±2% Output Voltage
400 mA Output Current
500 mV (max) Dropout Voltage (5.0 V Output)
Inhibit Input
Very Low Current Consumption
Fault Protection
♦ +45 V Peak Transient Voltage
♦ −42 V Reverse Voltage
♦ Short Circuit
♦ Thermal Overload
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These are Pb−Free Devices
76CXXG
ALYWW
1
5
NC
V4276C−XX
AWLYWWG
1
*Tab is connected to Pin 3 on all packages.
A
WL, L
Y
WW
G
XX
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Device
= 33 (3.3 V)
= 50 (5.0 V)
= AJ (Adj. Voltage)
ORDERING INFORMATION
See detailed ordering and shipping information in the ordering
information section on page 14 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
October, 2019 − Rev. 1
1
Publication Order Number:
NCV4276C/D
NCV4276C
I
Q
Bandgap
Reference
Error
Amplifier
Current Limit and
Saturation Sense
−
+
Thermal
Shutdown
INH
GND
NC
Figure 1. NCV4276C Block Diagram
I
Q
Bandgap
Reference
Error
Amplifier
Current Limit and
Saturation Sense
−
+
Thermal
Shutdown
INH
GND
VA
Figure 2. NCV4276C Adjustable Block Diagram
PIN FUNCTION DESCRIPTION
Pin No.
Symbol
1
I
Description
2
INH
Inhibit; Set low−to inhibit.
3
GND
Ground; Pin 3 internally connected to heatsink.
4
NC / VA
Not connected for fixed voltage version / Voltage Adjust Input for adjustable voltage version; use an external
voltage divider to set the output voltage
5
Q
Output: Bypass with a capacitor to GND. See Figures 3 to 8 and Regulator Stability Considerations section.
Input; Battery Supply Input Voltage.
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2
NCV4276C
MAXIMUM RATINGS
Rating
Symbol
Min
Max
Unit
Input Voltage
VI
−42
45
V
Input Peak Transient Voltage
VI
−
45
V
Inhibit INH Voltage
VINH
−42
45
V
Voltage Adjust Input VA
VVA
−0.3
10
V
Output Voltage
VQ
−1.0
40
V
Ground Current
Iq
−
100
mA
Input Voltage Operating Range (Note 1)
VI
VQ + 0.5 V or 4.5 V
(Note 2)
40
V
−
−
−
4.0
250
1.25
−
−
−
kV
V
kV
Junction Temperature
TJ
−40
150
°C
Storage Temperature
Tstg
−50
150
°C
ESD Susceptibility
(Human Body Model)
(Machine Model)
(Charged Device Model)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
2. Minimum VI = 4.5 V or (VQ + 0.5 V), whichever is higher.
LEAD TEMPERATURE SOLDERING REFLOW (Note 3)
Lead Temperature Soldering
Reflow (SMD styles only), Leaded, 60−150 s above 183, 30 s max at peak
Reflow (SMD styles only), Lead Free, 60−150 s above 217, 40 s max at peak
Wave Solder (through hole styles only), 12 sec max
TSLD
−
−
−
240
265
310
°C
3. Per IPC / JEDEC J−STD−020C.
THERMAL CHARACTERISTICS
Characteristic
Test Conditions (Typical Value)
Unit
DPAK 5−PIN PACKAGE
Min Pad Board (Note 4)
1, Pad Board (Note 5)
Junction−to−Tab (psi−JLx, yJLx)
3.8
4.3
C/W
Junction−to−Ambient (RqJA, qJA)
75.1
58.5
C/W
0.4 sq. in. Spreader Board (Note 6)
1.2 sq. in. Spreader Board (Note 7)
Junction−to−Tab (psi−JLx, yJLx)
5.4
5.4
C/W
Junction−to−Ambient (RqJA, qJA)
54.2
43.3
C/W
D2PAK 5−PIN PACKAGE
4.
5.
6.
7.
1 oz. copper, 0.26 inch2 (168 mm2) copper area, 0.062″ thick FR4.
1 oz. copper, 1.14 inch2 (736 mm2) copper area, 0.062″ thick FR4.
1 oz. copper, 0.373 inch2 (241 mm2) copper area, 0.062″ thick FR4.
1 oz. copper, 1.222 inch2 (788 mm2) copper area, 0.062″ thick FR4.
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NCV4276C
ELECTRICAL CHARACTERISTICS (VI = 13.5 V; −40°C < TJ < 150°C; unless otherwise noted.)
Characteristic
Symbol
Test Conditions
Min
Typ
Max
Unit
OUTPUT
Output Voltage, 5.0 V Version
VQ
5.0 mA < IQ < 400 mA,
6.0 V < VI < 28 V
4.9
5.0
5.1
V
Output Voltage, 5.0 V Version
VQ
5.0 mA < IQ < 200 mA,
6.0 V < VI < 40 V
4.9
5.0
5.1
V
Output Voltage, 3.3 V Version
VQ
5.0 mA < IQ < 400 mA,
4.5 V < VI < 28 V
3.234
3.3
3.366
V
Output Voltage, 3.3 V Version
VQ
5.0 mA < IQ < 200 mA,
4.5 V < VI < 40 V
3.234
3.3
3.366
V
AVQ
5.0 mA < IQ < 400 mA
VQ+1 < VI < 40 V
VI > 4.5 V
−2%
−
+2%
V
400
600
1100
mA
Output Voltage, Adjustable Version
Output Current Limitation
IQ
VQ = 90% VQTYP
(VQTYP = 2.5 V for ADJ version)
Quiescent Current (Sleep Mode)
Iq = II − IQ
Iq
VINH = 0 V
−
−
10
mA
Quiescent Current, Iq = II − IQ
Iq
IQ = 1.0 mA
−
95
200
mA
Quiescent Current, Iq = II − IQ
Iq
IQ = 250 mA
−
5
15
mA
Quiescent Current, Iq = II − IQ
Iq
IQ = 400 mA
−
10
35
mA
IQ = 250 mA,
VDR = VI − VQ
VI > 4.5 V
−
250
500
mV
IQ = 250 mA (Note 8)
−
250
500
mV
IQ = 5.0 mA to 400 mA
−
3.0
20
mV
DVI = 12 V to 32 V,
IQ = 5.0 mA
−
4.0
15
mV
fr = 100 Hz, Vr = 0.5 VPP
−
70
−
dB
Dropout Voltage,
VDR
Adjustable Version
Dropout Voltage (5.0 V Version)
VDR
Load Regulation
DVQ,LO
Line Regulation
DVQ
Power Supply Ripple Rejection
PSRR
INHIBIT
Inhibit Voltage, Output High
VINH
VQ w VQMIN
−
2.3
2.8
V
Inhibit Voltage, Output Low (Off)
VINH
VQ v 0.1 V
1.8
2.2
−
V
Input Current
IINH
VINH = 5.0 V
5.0
10
20
mA
TSD
IQ = 5.0 mA
150
−
210
°C
THERMAL SHUTDOWN
Thermal Shutdown Temperature (Note 9)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
8. Measured when the output voltage VQ has dropped 100 mV from the nominal valued obtained at V = 13.5 V.
9. Guaranteed by design, not tested in production.
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4
NCV4276C
5.5 − 45 V
Input
II
CI1
1.0 mF
I 1
CI2
100 nF
CQ
22 mF
NCV4276C
INH
2
IINH
4
3
Output
IQ
5 Q
NC
RL
GND
Figure 3. Applications Circuit; Fixed Voltage Version
VQ = [(R1 + R2) * Vref] / R2
Input
II
CI1
1.0 mF
I 1
CI2
100 nF
2
4
3
Output
IQ
CQ
22 mF
NCV4276C
INH
IINH
5 Q
Cb*
R1
VA
GND
RL
R2
Cb* − Required if usage of low ESR output capacitor CQ is demand, see Regulator Stability Considerations section
Figure 4. Applications Circuit; Adjustable Voltage Version
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NCV4276C
TYPICAL PERFORMANCE CHARACTERISTICS
100
100
Unstable Region
Unstable Region
10
ESR (W)
ESR (W)
10
1
Stable Region
1
Stable Region
0.1
0.1
CQ = 10 mF
0.01
0
50
150 200
250
100
300
IQ, OUTPUT CURRENT (mA)
350
CQ = 22 mF
0.01
400
0
Figure 5. Output Stability with Output Capacitor
ESR, Fixed Versions (5.0 V and 3.3 V)
10
Unstable Region
50
100
150 200
250
300
IQ, OUTPUT CURRENT (mA)
350
400
Figure 6. Output Stability with Output Capacitor
ESR, Fixed Versions (5.0 V and 3.3 V)
1000
Cb capacitor not connected
Cb capacitor not connected
Unstable Region
100
CQ = 22 mF
Stable Region
0.1
ESR (W)
ESR (W)
1
CQ = 22 mF
VQ = 2.5 V
0
50
100
150 200
250
300
IQ, OUTPUT CURRENT (mA)
Stable Region
1
VQ = 6 V
VQ = 12 V
0.1
Unstable Region
0.01
10
350
0.01
400
Figure 7. Output Stability with Output Capacitor
ESR, Adjustable Version
Unstable Region
0
50
100
150 200
250
300
IQ, OUTPUT CURRENT (mA)
350
400
Figure 8. Output Stability with Output Capacitor
ESR, Adjustable Version
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NCV4276C
TYPICAL PERFORMANCE CHARACTERISTICS − Fixed Versions
3.36
VI = 13.5 V
RL = 1 kW
VQ, OUTPUT VOLTAGE (V)
VQ, OUTPUT VOLTAGE (V)
5.10
5.05
5.00
4.95
4.90
−40
0
40
80
120
3.32
3.30
3.28
3.26
3.24
−40
160
120
6
TJ = 25°C
RL = 20 W
8
6
4
2
0
160
Figure 10. Output Voltage vs.
Junction Temperature, 3.3 V Version
10
5
15
20
30
25
35
5
4
3
2
1
0
40
TJ = 25°C
RL = 20 W
0
5
10
15
20
25
30
35
40
VI, INPUT VOLTAGE (V)
VI, INPUT VOLTAGE (V)
Figure 11. Quiescent Current vs.
Input Voltage, 5.0 V Version
Figure 12. Quiescent Current vs. Input Voltage,
3.3 V Version
4
6
5
VQ, OUTPUT VOLTAGE (V)
VQ, OUTPUT VOLTAGE (V)
80
TJ, JUNCTION TEMPERATURE (°C)
10
4
3
TJ = 25°C
RL = 20 W
2
1
0
40
Figure 9. Output Voltage vs.
Junction Temperature, 5.0 V Version
Iq, QUIESCENT CURRENT (mA)
Iq, QUIESCENT CURRENT (mA)
0
TJ, JUNCTION TEMPERATURE (°C)
12
0
VI = 13.5 V
RL = 660 W
3.34
0
1
2
3
4
5
6
7
8
9
3
2
1
0
10
TJ = 25°C
RL = 20 W
0
1
2
3
4
5
6
7
8
9
VI, INPUT VOLTAGE (V)
VI, INPUT VOLTAGE (V)
Figure 13. Output Voltage vs. Input Voltage,
5.0 V Version
Figure 14. Output Voltage vs. Input Voltage,
3.3 V Version
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10
NCV4276C
TYPICAL PERFORMANCE CHARACTERISTICS − Fixed Versions
0.8
0.6
1.2
II, INPUT CURRENT (mA)
II, INPUT CURRENT (mA)
1.6
0.8
0.4
0
−0.4
RL = 6.8 kW
TJ = 25°C
−0.8
−1.2
−50 −40 −30 −20 −10
0
10
20
30
40
−0.4
RL = 6.8 kW
TJ = 25°C
−0.6
0
10
20
30
40
VI, INPUT VOLTAGE (V)
Figure 15. Input Current vs. Input Voltage,
5.0 V Version
Figure 16. Input Current vs. Input Voltage,
3.3 V Version
50
700
TJ = 125°C
IQ, OUTPUT CURRENT (mA)
VDR, DROPOUT VOLTAGE (mV)
−0.2
−1.0
−50 −40 −30 −20 −10
50
300
250
TJ = 25°C
200
150
100
50
0
50
100
150
200
250
300
350
600
500
400
300
200
TJ = 25°C
VQ = 0 V
100
0
400
0
5
10
15
20
25
30
35
40
IQ, OUTPUT CURRENT (mA)
VI, INPUT VOLTAGE (V)
Figure 17. Dropout Voltage vs. Output Current,
Only 5 V Version
Figure 18. Maximum Output Current vs.
Input Voltage
45
0.5
18
16
Iq, QUIESCENT CURRENT (mA)
Iq, QUIESCENT CURRENT (mA)
0
VI, INPUT VOLTAGE (V)
350
VI = 13.5 V
TJ = 25°C
14
12
10
8
6
4
2
0
0.2
−0.8
400
0
0.4
0
100
200
300
400
500
0.3
0.2
0.1
0
600
VI = 13.5 V
TJ = 25°C
0.4
0
10
20
30
40
IQ, OUTPUT CURRENT (mA)
IQ, OUTPUT CURRENT (mA)
Figure 19. Quiescent Current vs.
Output Current (High Load)
Figure 20. Quiescent Current vs.
Output Current (Low Load)
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50
NCV4276C
TYPICAL PERFORMANCE CHARACTERISTICS − Adjustable Version
5.0
2.54
VI = 13.5 V
RL = 500 W
2.53
Iq, QUIESCENT CURRENT (mA)
VQ, OUTPUT VOLTAGE (V)
2.55
2.52
2.51
2.50
2.49
2.48
2.47
2.46
2.45
−40
0
40
80
120
160
4.5
TJ = 25°C
RL = 20 W
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
TJ, JUNCTION TEMPERATURE (°C)
Figure 21. Output Voltage vs.
Junction Temperature
10
15
20
25
30
VI, INPUT VOLTAGE (V)
35
40
Figure 22. Quiescent Current vs.
Input Voltage
3
0.6
II, INPUT CURRENT (mA)
VQ, OUTPUT VOLTAGE (V)
5
2
1
TJ = 25°C
RL = 20 W
1
2
4
6
3
5
7
VI, INPUT VOLTAGE (V)
8
0.2
0
−0.2
−0.4
−0.6
TJ = 25°C
RL = 6.8 kW
−0.8
−1.0
−50 −40 −30 −20 −10
0
0
0.4
9
10
0
10
20
30
40
VI, INPUT VOLTAGE (V)
Figure 23. Output Voltage vs. Input Voltage
Figure 24. Input Current vs. Input Voltage
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50
NCV4276C
TYPICAL PERFORMANCE CHARACTERISTICS − Adjustable Version
700
350
IQ, OUTPUT CURRENT (mA)
VDR, DROPOUT VOLTAGE (mV)
400
TJ = 125°C
300
250
TJ = 25°C
200
150
100
600
500
400
300
200
TJ = 25°C
VQ = 0 V
100
50
0
0
50
100
150 200
250 300
IQ, OUTPUT CURRENT (mA)
350
0
400
5
0
18
35
40
45
0.5
16
Iq, QUIESCENT CURRENT (mA)
Iq, QUIESCENT CURRENT (mA)
15
25
20
30
VI, INPUT VOLTAGE (V)
Figure 26. Maximum Output Current vs.
Input Voltage
Figure 25. Dropout Voltage vs. Output Current,
Output Voltage set to 5.0 V
TJ = 25°C
VI = 13.5 V
14
12
10
8
6
4
2
0
10
0
100
200
300
400
500
0.3
0.2
0.1
0
600
TJ = 25°C
VI = 13.5 V
0.4
0
10
20
30
40
IQ, OUTPUT CURRENT (mA)
IQ, OUTPUT CURRENT (mA)
Figure 27. Quiescent Current vs.
Output Current (High Load)
Figure 28. Quiescent Current vs.
Output Current (Low Load)
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50
NCV4276C
Circuit Description
The NCV4276C is an integrated low dropout regulator
that provides a regulated voltage at 400 mA to the output.
It is enabled with an input to the inhibit pin. The regulator
voltage is provided by a PNP pass transistor controlled by
an error amplifier with a bandgap reference, which gives it
the lowest possible dropout voltage. The output current
capability is 400 mA, and the base drive quiescent current
is controlled to prevent oversaturation when the input
voltage is low or when the output is overloaded. The
regulator is protected by both current limit and thermal
shutdown. Thermal shutdown occurs above 150°C to
protect the IC during overloads and extreme ambient
temperatures.
Minimum ESR for CQ = 10 mF and 22 mF is native ESR
of ceramic capacitor with which the fixed output voltage
devices are performing stable. Murata ceramic capacitors
were used,
GCM32ER71E106KA57 (10 mF, 25V, X7R, 1210),
GRM32ER71E226ME15 (22 mF, 25V, X7R, 1210).
Calculating Bypass Capacitor
If usage of low ESR ceramic capacitors is demand in case
of Adjustable Regulator, connect the bypass capacitor Cb
between Voltage Adjust pin and Q pin according to
Applications circuit at Figure 4.
Parallel combination of bypass capacitor Cb with the
feedback resistor R1 contributes in the device transfer
function as an additional zero and affects the device loop
stability, therefore its value must be optimized. Attention
to the Output Capacitor value and its ESR must be paid. See
also Stability in High Speed Linear LDO Regulators
Application Note, AND8037/D for more information.
Optimal value of bypass capacitor is given by following
expression
Regulator
The error amplifier compares the reference voltage to a
sample of the output voltage (VQ) and drives the base of a
PNP series pass transistor via a buffer. The reference is a
bandgap design to give it a temperature−stable output.
Saturation control of the PNP is a function of the load
current and input voltage. Oversaturation of the output
power device is prevented, and quiescent current in the
ground pin is minimized. See Figure 4, Test Circuit, for
circuit element nomenclature illustration.
Cb +
2
p
1
fz
R1
@ (F)
where
R1 = the upper feedback resistor
fz = the frequency of the zero added into the device
transfer function by R1 and Cb external components.
Set the R1 resistor according to output voltage
requirement. Chose the fz with regard on the output
capacitance CQ, refer to the table below.
Regulator Stability Considerations
The input capacitors (CI1 and CI2) are necessary to
stabilize the input impedance to avoid voltage line
influences. Using a resistor of approximately 1.0 W in
series with CI2 can stop potential oscillations caused by
stray inductance and capacitance.
The output capacitor helps determine three main
characteristics of a linear regulator: startup delay, load
transient response and loop stability. The capacitor value
and type should be based on cost, availability, size and
temperature constraints. The aluminum electrolytic
capacitor is the least expensive solution, but, if the circuit
operates at low temperatures (−25°C to −40°C), both the
value and ESR of the capacitor will vary considerably. The
capacitor manufacturer’s data sheet usually provides this
information.
The value for the output capacitor CQ, shown in Figure 3,
should work for most applications; see also Figures 5 to 8
for output stability at various load and Output Capacitor
ESR conditions. Stable region of ESR in Figures 5 to 8
shows ESR values at which the LDO output voltage does
not have any permanent oscillations at any dynamic
changes of output load current. Marginal ESR is the value
at which the output voltage waving is fully damped during
four periods after the load change and no oscillation is
further observable.
ESR characteristics were measured with ceramic
capacitors and additional series resistors to emulate ESR.
Low duty cycle pulse load current technique has been used
to maintain junction temperature close to ambient
temperature.
CQ (mF)
10
22
47
fz Range (kHz)
16 − 18
11 − 18
8 − 18
Ceramic capacitors and its part numbers listed bellow
have been used as low ESR output capacitors CQ from the
table above to define the frequency ranges of additional
zero required for stability.
GCM32ER71E106KA57 (10 mF, 25V, X7R, 1210)
GRM32ER71E226ME15 (22 mF, 25V, X7R, 1210)
GRM32ER61C476ME15 (47 mF, 16 V, X5R, 1210)
Inhibit Input
The inhibit pin is used to turn the regulator on or off. By
holding the pin down to a voltage less than 1.8 V, the output
of the regulator will be turned off. When the voltage on the
Inhibit pin is greater than 2.8 V, the output of the regulator
will be enabled to power its output to the regulated output
voltage. The inhibit pin may be connected directly to the
input pin to give constant enable to the output regulator.
Setting the Output Voltage (Adjustable Version)
The output voltage range of the adjustable version can be
set between 2.5 V and 20 V. This is accomplished with an
external resistor divider feeding back the voltage to the IC
back to the error amplifier by the voltage adjust pin VA.
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11
NCV4276C
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external
heatsink will be required.
The internal reference voltage is set to a temperature stable
reference of 2.5 V.
The output voltage is calculated from the following
formula. Ignoring the bias current into the VA pin:
VI
Use R2 < 50 k to avoid significant voltage output errors
due to VA bias current.
Connecting VA directly to Q without R1 and R2 creates
an output voltage of 2.5 V.
Designers should consider the tolerance of R1 and R2
during the design phase.
The input voltage range for operation (pin 1) of the
adjustable version is between (VQ + 0.5 V) and 40 V.
Internal bias requirements dictate a minimum input voltage
of 4.5 V. The dropout voltage for output voltages less than
4.0 V is (4.5 V − VQ).
PD(max) + [VI(max) * VQ(min)] IQ(max)
VQ
Iq
Figure 29. Single Output Regulator with Key
Performance Parameters Labeled
Heatsinks
A heatsink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
Each material in the heat flow path between the IC and
the outside environment will have a thermal resistance.
Like series electrical resistances, these resistances are
summed to determine the value of RqJA:
(1)
) VI(max)Iq
Iq
SMART
REGULATOR®
} Control
Features
Calculating Power Dissipation
in a Single Output Linear Regulator
The maximum power dissipation for a single output
regulator (Figure 29) is:
where
VI(max)
VQ(min)
IQ(max)
IQ
II
VQ + [(R1 ) R2) * Vref]ńR2
RqJA + RqJC ) RqCS ) RqSA
where
RqJC is the junction−to−case thermal resistance,
RqCS is the case−to−heatsink thermal resistance,
RqSA is the heatsink−to−ambient thermal
resistance.
is the maximum input voltage,
is the minimum output voltage,
is the maximum output current for the
application,
is the quiescent current the regulator
consumes at IQ(max).
RqJC appears in the package section of the data sheet.
Like RqJA, it too is a function of package type. RqCS and
RqSA are functions of the package type, heatsink and the
interface between them. These values appear in data sheets
of heatsink manufacturers.
Thermal, mounting, and heatsinking considerations are
discussed in the ON Semiconductor application note
AN1040/D.
Once the value of PD(max) is known, the maximum
permissible value of RqJA can be calculated:
o
T
RqJA + 150 C * A
PD
(3)
(2)
The value of RqJA can then be compared with those in the
package section of the data sheet. Those packages with
RqJA less than the calculated value in Equation 2 will keep
the die temperature below 150°C.
www.onsemi.com
12
110
RqJA, THERMAL RESISTANCE (°C/W)
RqJA, THERMAL RESISTANCE (°C/W)
NCV4276C
100
90
80
1 oz
70
2 oz
60
50
40
0
100
200
300
400
500
600
700
80
75
70
65
60
1 oz
55
50
2 oz
45
40
35
30
0
800
COPPER SPREADER AREA (mm2)
100
200
300
400
500
600
700
800
COPPER SPREADER AREA (mm2)
Figure 30. RqJA vs. Copper Spreader Area,
DPAK 5−Lead
Figure 31. RqJA vs. Copper Spreader Area,
D2PAK 5−Lead
100
Cu Area 168 mm2
R(t) (°C/W)
Cu Area 736 mm2
10
1
0.1
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 32. Single−Pulse Heating Curves, DPAK 5−Lead
100
R(t) (°C/W)
Cu Area 241 mm2
Cu Area 788 mm2
10
1
0.1
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
PULSE TIME (sec)
Figure 33. Single−Pulse Heating Curves, D2PAK 5−Lead
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13
10
100
1000
NCV4276C
100
RqJA, 736 mm2 (°C/W)
50% Duty Cycle
20%
10
10%
5%
1
2%
1%
Non−normalized Response
Single Pulse
0.1
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
100
1000
PULSE TIME (sec)
Figure 34. Duty Cycle for 1, Spreader Boards, DPAK 5−Lead
100
RqJA, 788 mm2 (°C/W)
50% Duty Cycle
10
20%
10%
5%
1
2%
1%
Non−normalized Response
Single Pulse
0.1
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
PULSE TIME (sec)
Figure 35. Duty Cycle for 1, Spreader Boards, D2PAK 5−Lead
ORDERING INFORMATION
Device
Output Voltage Accuracy
Output Voltage
NCV4276CDT33RKG
3.3 V
NCV4276CDS33R4G
NCV4276CDT50RKG
NCV4276CDS50R4G
5.0 V
2%
NCV4276CDTADJRKG
NCV4276CDTADJT5G
Adjustable
NCV4276CDSADJR4G
Package
Shipping†
DPAK, 5−Pin
(Pb−Free)
2500 / Tape & Reel
D2PAK, 5−Pin
(Pb−Free)
800 / Tape & Reel
DPAK, 5−Pin
(Pb−Free)
2500 / Tape & Reel
D2PAK, 5−Pin
(Pb−Free)
800 / Tape & Reel
DPAK, 5−Pin
(Pb−Free)
2500 / Tape & Reel
DPAK, 5−Pin
(Pb−Free)
2500 / Tape & Reel
D2PAK, 5−Pin
(Pb−Free)
800 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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14
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DPAK−5, CENTER LEAD CROP
CASE 175AA
ISSUE B
DATE 15 MAY 2014
SCALE 1:1
−T−
C
B
V
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
SEATING
PLANE
E
R
R1
Z
A
S
12 3 4 5
U
K
F
J
L
H
D
G
5 PL
0.13 (0.005)
M
T
2.2
0.086
0.34 5.36
0.013 0.217
5.8
0.228
10.6
0.417
0.8
0.031
SCALE 4:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON12855D
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.020 0.028
0.018 0.023
0.024 0.032
0.180 BSC
0.034 0.040
0.018 0.023
0.102 0.114
0.045 BSC
0.170 0.190
0.185 0.210
0.025 0.040
0.020
−−−
0.035 0.050
0.155 0.170
MILLIMETERS
MIN
MAX
5.97
6.22
6.35
6.73
2.19
2.38
0.51
0.71
0.46
0.58
0.61
0.81
4.56 BSC
0.87
1.01
0.46
0.58
2.60
2.89
1.14 BSC
4.32
4.83
4.70
5.33
0.63
1.01
0.51
−−−
0.89
1.27
3.93
4.32
GENERIC
MARKING DIAGRAMS*
RECOMMENDED
SOLDERING FOOTPRINT*
6.4
0.252
DIM
A
B
C
D
E
F
G
H
J
K
L
R
R1
S
U
V
Z
XXXXXXG
ALYWW
AYWW
XXX
XXXXXG
IC
Discrete
XXXXXX
A
L
Y
WW
G
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DPAK−5 CENTER LEAD CROP
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
D2PAK 5−LEAD
CASE 936A−02
ISSUE E
DATE 28 JUL 2021
SCALE 1:1
GENERIC
MARKING DIAGRAM*
xx
xxxxxxxxx
AWLYWWG
xxxxxx
A
WL
Y
WW
G
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98ASH01006A
D2PAK 5−LEAD
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
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