NCV7341D21G

NCV7341 High Speed Low Power CAN Transceiver The NCV7341 CAN transceiver is the interface between a controller area network (CAN) protocol controller and the physical bus and may be used in both 12 V and 24 V systems. The transceiver provides differential transmit capability to the bus and differential receive capability to the CAN controller. Due to the wide common−mode voltage range of the receiver inputs, the NCV7341 is able to reach outstanding levels of electromagnetic susceptibility (EMS). Similarly, extremely low electromagnetic emission (EME) is achieved by the excellent matching of the output signals. The NCV7341 is a new addition to the ON Semiconductor CAN high−speed transceiver family and offers the following additional features: Features http://onsemi.com PIN ASSIGNMENT TxD GND VCC 1 14 STB CANH 2 13 3 12 NCV7341 CANL VSPLIT • Ideal Passive Behavior when Supply Voltage is Removed • Separate VIO Supply for Digital Interface Allowing Communication • • • • • • • • • • • • RxD VIO 4 11 to CAN Controllers and Microcontrollers with Different Supply Levels Fully Compatible with the ISO 11898 Standard High Speed (up to 1 Mb) Very Low Electromagnetic Emission (EME) VSPLIT Voltage Source for Stabilizing the Recessive Bus Level if Split Termination is Used (Further Improvement of EME) Differential Receiver with High Common−Mode Range for Electromagnetic Immunity (EMI) Up to 110 Nodes can be Connected in Function of the Bus Topology Transmit Data (TxD) Dominant Time−out Function Bus Pins Protected Against Transients in Automotive Environments Bus Pins and Pin VSPLIT Short−Circuit Proof to Battery and Ground Thermally Protected NCV Prefix for Automotive and Other Applications Requiring Site and Control Changes These are Pb−Free Devices* 5 10 VBAT EN INH 6 9 WAKE ERR 7 8 (Top View) PC20060727.1 ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 17 of this data sheet. Typical Applications • Automotive • Industrial Networks *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2008 November, 2008 − Rev. 3 1 Publication Order Number: NCV7341/D NCV7341 Table 1. TECHNICAL CHARACTERISTICS Symbol VCC VIO VEN VSTB VTxD VRxD VERR VCANH VCANL VSPLIT VO(dif)(bus_dom) CMrange Cload tpd(rec−dom) tpd(dom−rec) TJ ESDHBM Parameter Supply Voltage for the Core Circuitry Supply Voltage for the Digital Interface DC Voltage at Pin EN DC Voltage at Pin STB DC Voltage at Pin TxD DC Voltage at Pin RxD DC Voltage at Pin ERR DC Voltage at Pin CANH DC Voltage at Pin CANL DC Voltage at Pin VSPLIT Differential Bus Output Voltage in Dominant State Input Common−Mode Range for Comparator Load Capacitance on IC Outputs Propagation Delay TxD to RxD Propagation Delay TxD to RxD Junction Temperature ESD Level, Human Body Model Pins CANH, CANL, VSPLIT, WAKE, VBAT other Pins See Figure 6 See Figure 6 90 90 −40 −4 −3 0 < VCC < 5.25 V; No Time Limit 0 < VCC < 5.25 V; No Time Limit 0 < VCC < 5.25 V; No time Limit 42.5 W < RLT < 60 W Guaranteed Differential Receiver Threshold and Leakage Current Condition Max 4.75 2.8 −0.3 −0.3 −0.3 −0.3 −0.3 −35 −35 −35 1.5 −35 Max 5.25 5.25 VIO + 0.3 VIO + 0.3 VIO + 0.3 VIO + 0.3 VIO + 0.3 +35 +35 +35 3 +35 15 230 245 150 4 3 Unit V V V V V V V V V V V V pF ns ns °C kV http://onsemi.com 2 NCV7341 BLOCK DIAGRAM VIO VIO 5 INH 7 VBAT 10 POR 13 TxD EN 1 6 Timer Thermal shutdown VCC V SPLIT ”Active” 14 Driver control Level shifter VIO ERR 8 Digital Control Block 12 CANL 11 VSPLIT CANH VCC 3 STB Wake − up Filter Rec Low Power Rec 26 kW VCC/2 26 kW 2 GND RxD 4 WAKE 9 NCV7341 PC20060921.1 ÏÏ ÏÏ ÏÏ ÏÏ ÏÏ VIO Clock VIO + − ”Active” Figure 1. Block Diagram http://onsemi.com 3 NCV7341 TYPICAL APPLICATION SCHEMATICS OUT 100 nF 100nF VCC TxD EN CAN controller x mF* 5V−Reg IN 1 kW 10 nF Vio 1 6 5 VCC INH VBAT 3 7 10 WAKE 9 2.7 kW CANH 13 NCV7341 11 VSPLIT CANL RLT = 60 W 180 kW VBAT 10 nF STB 14 RxD 4 RLT = 60 W CAN BUS ERR 8 2 GND Note (*): Value depending on regulator CLT= 4.7 nF 12 GND PC20060921.4 Figure 2. Application Diagram with a 5V CAN Controller x m F* OUT 3V− reg IN OUT 100 nF x m F* 100 nF Vcc TxD EN Vio 5 1 3 5V− reg IN 1 kW 10 nF 180 kW VBAT Vcc 7 INH VBAT 10 9 WAKE 2.7 kW CANH 10 nF CAN controller NCV7341 6 STB RxD 13 14 4 11 VSPLIT CANL RLT = 60 W CAN BUS ERR 8 2 CLT = 4.7 nF 12 RLT = 60 W GND Note (*): Value depending on regulator GND PC20060921.4 Figure 3. Application Diagram with a 3V CAN Controller http://onsemi.com 4 NCV7341 PIN DESCRIPTION TxD GND VCC 1 14 STB CANH 2 13 3 12 NCV7341 CANL VSPLIT RxD VIO 4 11 5 10 VBAT EN INH 6 9 WAKE ERR 7 8 PC20060727.1 Figure 4. NCV7340 Pin Assignment Table 2. PIN DESCRIPTION Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Name TxD GND VCC RxD VIO EN INH ERR WAKE VBAT VSPLIT CANL CANH STB Description Transmit data input; low level = dominant on the bus; internal pull−up current Ground Supply voltage for the core circuitry and the transceiver Receive data output; dominant bus => low output Supply voltage for the CAN controller interface Enable input; internal pull−down current High voltage output for controlling external voltage regulators Digital output indicating errors and power−up; active low Local wake−up input Battery supply connection Common−mode stabilization output Low−level CAN bus line (low in dominant) High−level CAN bus line (high in dominant) Stand−by mode control input; internal pull−down current http://onsemi.com 5 NCV7341 FUNCTIONAL DESCRIPTION OPERATING MODES Operation modes of NCV7341 are shown in Figures 5 and in Table 3. SLEEP MODE STB = H and EN = L and VCC/VIO undervoltage flag reset STB = H and EN = H and VCC/VIO undervoltage flag reset STB = H and EN = H STB = H and EN = L STB = L and flags set RECEIVE ONLY MODE NORMAL MODE STB = H and EN = H flags reset and t > t h(min) STB = H and EN = L STB = H and EN = L STB = H and EN = H STB = L and EN = H and flags reset STB = L and EN = L STB = L and EN = H STB = L and (EN = L or flags set) POWER UP STANDBY MODE STB = L and EN = H and flags reset STB = L and (EN = L or flags set) GOTO SLEEP MODE LEGEND ”Flags set” : ”Flags reset” : wake−up or power−up not (wake−up or power−up) PC20060921.2 Figure 5. Operation Modes http://onsemi.com 6 NCV7341 Table 3. OPERATION MODES Conditions VCC/VIO Undervoltage Flag Set Reset VBAT Undervoltage Flag X Set Power−up or Wakeup Flag X Set Reset Transceiver Behavior Pin STB X Pin EN X Operating Mode Sleep Standby If in sleep, then no change otherwise stand−by Pin INH Floating High Floating High High Floating High High Floating High High High Low Low Reset Reset Set Reset Stand−by If in sleep, then no change otherwise stand−by Low High Reset Reset Set Reset Stand−by If in sleep, then no change otherwise go−to−sleep High High Low High Reset Reset Reset Reset X X Receive−only Normal Normal Mode In Normal mode, the transceiver is able to communicate via the bus lines. The CAN controller can transmit data to the bus via TxD pin and receive data from the bus via Pin RxD. The bus lines (CANH and CANL) are internally biased to VCC/2 via the common−mode input resistance. Pin VSPLIT is also providing voltage VCC/2 which can be further used to externally stabilize the common mode voltage of the bus – see Figure 2 and Figure 3. Pin INH is active (pulled high) so that the external regulators controlled by INH Pin are switched on. Receive−Only Mode puts pin EN to High and STB Pin to Low. If the logical state of Pins EN and STB is kept unchanged for minimum period of th(min) and neither a wake−up nor a power−up event occur during this time, the transceiver enters sleep mode. While in go−to−sleep mode, the transceiver behaves identically to stand−by mode. Sleep Mode In Receive−only mode, the CAN transmitter is disabled. The CAN controller can still receive data from the bus via RxD Pin as the receiver part remains active. Equally to normal mode, the bus lines (CANH and CANL) are internally biased to VCC/2 and Pin VSPLIT is providing voltage VCC/2. Pin INH is also active (pulled high). Standby Mode Standby mode is a low−power mode. Both the transmitter and the receiver are disabled and a very low−power differential receiver monitors the CAN bus activity. Bus lines are biased internally to ground via the common mode input resistance and Pin VSPLIT is high−impedant (floating). A wake−up event can be detected either on the CAN bus or on the WAKE Pin. A valid wake−up is signaled on pins ERR and RxD. Pin INH remains active (pulled high) so that the external regulators controlled by INH Pin are switched on. Go−To−Sleep Mode Sleep mode is a low−power mode in which the consumption is further reduced compared to stand−by mode. Sleep mode can be entered via go−to−sleep mode or in case an undervoltage on either VCC or VIO occurs for longer than the under−voltage detection time. The transceiver behaves identically to standby mode, but the INH Pin is deactivated (left floating) and the external regulators controlled by INH Pin are switched off. In this way, the VBAT consumption is reduced to a minimum. The device will leave sleep mode either by a wake−up event (in case of a CAN bus wake−up or via Pin WAKE) or by putting Pin STB high (as long as an under−voltage on VCC or VIO is not detected). Internal Flags Go−To−Sleep mode is an intermediate state used to put the transceiver into sleep mode in a controlled way. Go−To−Sleep mode is entered when the CAN controller The transceiver keeps several internal flags reflecting conditions and events encountered during its operation. Some flags influence the operation mode of the transceiver (see Figure 5 and Table 3). Beside the undervoltage and the TxD dominant timeout flags, all others can be read by the CAN controller on Pin ERR. Pin ERR signals internal flags depending on the operation mode of the transceiver. An overview of the flags and their visibility on Pin ERR is given in Table 4. Because the ERR Pin uses negative logic, it will be pulled low if the signaled flag is set and will be pulled high if the signaled flag is reset. http://onsemi.com 7 NCV7341 Table 4. INTERNAL FLAGS AND THEIR VISIBILITY Internal Flag VCC/VIO Undervoltage VBAT Undervoltage Powerup Wake−up Set Condition VCC < VCC(SLEEP) longer than tUV(VCC) or VIO < VIO(SLEEP) longer than tUV(VIO) VBAT < VBAT(STB) VBAT rises above VBAT(PWUP) (VBAT connection to the transceiver) When remote or local wake−up is detected Reset Condition At wake−up or power−up When VBAT recovers When normal mode is entered At power−up or when normal mode is entered or when VCC/VIO undervoltage flag is set At power−up or when leaving normal mode No No In receive−only mode. Not going from normal mode Both on ERR and RxD (both pulled to low). In go−to−sleep, standby and sleep mode. In normal mode before 4 consecutive dominant symbols are sent. Then ERR pin becomes High again Overtemperature condition observable in receive−only mode entered from normal mode Visibility on Pin ERR Local Wake−up When local wake−up is detected (i.e.via pin WAKE) Failure Pin TxD clamped low or overtemperature When entering normal mode or when RxD is Low while TxD is high (provided all failures disappeared) The VCC/VIO undervoltage flag is set if VCC supply drops below VCC(sleep) level for longer than tUV(VCC) or VIO supply drops below VIO(sleep) level for longer than tUV(VIO). If the flag is set, the transceiver enters sleep mode. After a waiting time identical to the undervoltage detection times tUV(VCC) and tUV(VIO), respectively, the flag can be reset either by a valid wake−up request or when the powerup flag is set. During this waiting time, the wakeup detection is blocked. VBAT Under−voltage Flag VCC/VIO Undervoltage Flag Local wake−up Flag This flag is set when a valid wake−up request through WAKE Pin occurs. It can be observed on the ERR Pin in normal mode. It can only be set when the powerup flag is reset. The local wake−up flag is reset at powerup or at leaving Normal mode. Failure Flag The flag is set when VBAT supply drops below VBAT(STB) level. The transceiver will enter the standby mode. The flag is reset when VBAT supply recovers. The transceiver then enters the mode defined by inputs STB and EN. Power−up Flag This flag is set when VBAT supply recovers after being below VBAT(PWUP) level, which corresponds to a connection of the transceiver to the battery. The VCC/VIO undervoltage flag is cleared so that the transceiver cannot enter the Go−to−sleep Mode, ensuring that INH Pin is high and the external voltage regulators are activated at the battery connection. In Receive−only mode, the powerup flag can be observed on the ERR Pin. The flag is reset when Normal mode is entered. Wake−up Flag The failure flag is set in one of the following situations: • TxD Pin is Low (i.e. dominant is requested by the CAN controller) for longer than tdom(TxD) − Under this condition, the transmitter is disabled so that a bus lockup is avoided in case of an application failure which would drive permanent dominant on the bus. The transmitter remains disabled until the failure flag is reset. • Overtemperature − If the junction temperature reaches TJ(SD), the transmitter is disabled in order to protect it from overheating and the failure flag is set. The transmitter remains disabled until the failure flag is reset. The failure flag is reset when Normal mode is entered or when TxD pin is High while RxD pin is Low. In case of overtemperature, the failure flag is observable on pin ERR. Split Circuit This flag is set when the transceiver detects a valid wake−up request via the bus or via the WAKE Pin. Setting the wake−up flag is blocked during the waiting time of the VCC/VIO undervoltage flag. The wake−up flag is immediately propagated to Pins ERR and RxD – provided that supplies VCC and VIO are available. The wake−up flag is reset at power−up or when VCC/VIO undervoltage occurs or when Normal mode is entered. The VSPLIT Pin is operational only in normal and receive−only modes. It is floating in standby and sleep modes. The VSPLIT can be connected as shown in Figure 2 and Figure 3 and its purpose is to provide a stabilized DC voltage of VCC/2 to the bus avoiding possible steps in the common−mode signal, therefore reducing EME. These unwanted steps could be caused by an unpowered node on the network with excessive leakage current from the bus that shifts the recessive voltage from its nominal VCC/2 level. http://onsemi.com 8 NCV7341 Wake−up Fail Safe Features The transceiver can detect wake−up events in stand−by, go−to−sleep and sleep modes. Two types of wake−up events are handled – remote wake−up via the CAN bus or a local wake−up via the WAKE pin. A valid remote wake−up is recognized after two dominant states of the CAN bus of at least tdom, each of them followed by a recessive state of at least trec. A local wake−up is detected after a change of state (High to Low, or Low to High) on WAKE Pin which is stable for at least tWAKE. To increase the EMS level of the WAKE Pin, an internal current source is connected to it. If the state of the WAKE Pin is stable at least for tWAKE, the direction of the current source follows (pulldown current for Low state, pullup current for High state). It is recommended to connect Pin WAKE either to GND or VBAT if it’s not used in the application. Fail safe behavior is ensured by the detection functions associated with the internal flags. Furthermore, a current−limiting circuit protects the transmitter output stage from damage caused by accidental short circuit to either positive or negative supply voltage, although power dissipation increases during this fault condition. The Pins CANH and CANL are protected from automotive electrical transients (according to ISO 7637; see Figure 9). Pins TxD is pulled high and Pins STB and EN are pulled low internally should the input become disconnected. Pins TxD, STB, EN and RxD will be floating, preventing reverse supply should the VIO supply be removed. http://onsemi.com 9 NCV7341 ELECTRICAL CHARACTERISTICS Definitions Absolute Maximum Ratings All voltages are referenced to GND (Pin 2). Positive currents flow into the IC. Sinking current means the current is flowing into the pin; sourcing current means the current is flowing out of the pin. Table 5. ABSOLUTE MAXIMUM RATINGS Symbol VBAT VCC VIO VCANH VCANL VCANL−VCANH VSPLIT VINH VWAKE VTxD VRxD VSTB VEN VERR Vtran(CANH) Vtran(CANL) Vtran(VSPLIT) Vesd(CANL/CANH/ VSPLIT, VBAT, WAKE) Stresses above those listed in the following table may cause permanent device failure. Exposure to absolute maximum ratings for extended periods may affect device reliability. Parameter Supply voltage Supply voltage Supply voltage DC voltage at pin CANH DC voltage at pin CANL DC voltage between bus pins CANH and CANL DC voltage at pin VSPLIT DC voltage at pin INH DC voltage at pin WAKE DC voltage at pin TxD DC voltage at pin RxD DC voltage at pin STB DC voltage at pin EN DC voltage at pin ERR Transient voltage at pin CANH Transient voltage at pin CANL Transient voltage at pin VSPLIT Electrostatic discharge voltage at pins intended to be wired outside of the module (CANH, CANL, VSPLIT, VBAT, WAKE) Electrostatic discharge voltage at all other pins Static latch−up at all pins Storage temperature Ambient temperature Maximum junction temperature Conditions Min. −0.3 −0.3 −0.3 Max. 58 +7 +7 +58 +58 +58 +58 VBAT+0.3 58 7 VIO + 0.3 7 7 VIO + 0.3 +300 +300 +300 4 500 3 500 120 Unit V V V V V V V V V V V V V V V V V kV V kV V mA °C °C °C 0 < VCC < 5.25 V; no time limit 0 < VCC < 5.25 V; no time limit 0 < VCC < 5.25 V; no time limit 0 < VCC < 5.25 V; no time limit −58 −58 −58 −58 −0.3 −0.3 −0.3 −0.3 −0.3 −0.3 −0.3 (Note 1) (Note 1) (Note 1) (Note 2) (Note 4) (Note 2) (Note 4) (Note 3) −300 −300 −300 −4 −500 −3 −500 Vesd Latch−up Tstg Tamb Tjunc −50 −50 −50 +150 +125 +180 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Applied transient waveforms in accordance with ISO 7637 part 3, test pulses 1, 2, 3a, and 3b (see Figure 9). 2. Standardized human body model electrostatic discharge (ESD) pulses in accordance to MIL883 method 3015.7. 3. Static latch-up immunity: Static latch-up protection level when tested according to EIA/JESD78. 4. Standardized charged device model ESD pulses when tested according to EOS/ESD DS5.3-1993. http://onsemi.com 10 NCV7341 Operating Conditions Operating conditions define the limits for functional operation, parametric characteristics and reliability specification of the device. Functionality of the device is not guaranteed outside the operating conditions. Table 6. OPERATING RANGES Symbol VBAT VBAT_SLEEP VCC VIO VCANH VCANL VCANL−VCANH VSPLIT VINH VWAKE VTxD VRxD VSTB VEN VERR CLOAD TA TJ Parameter Supply Voltage Supply Voltage in the Sleep Mode Supply Voltage Supply Voltage DC Voltage at Pin CANH DC Voltage at Pin CANL DC Voltage Between Bus Pins CANH and CANL DC Voltage at Pin VSPLIT DC Voltage at Pin INH DC Voltage at Pin WAKE DC Voltage at Pin TxD DC Voltage at Pin RxD DC Voltage at Pin STB DC Voltage at Pin EN DC Voltage at Pin ERR Capacitive Load on Digital Outputs (Pins RxD and ERR) Ambient Temperature Maximum Junction Temperature −40 −40 Receiver Function Guaranteed Receiver Function Guaranteed Receiver Function Guaranteed Leakage and Current Limitation are Guaranteed (Note 1) Conditions Min 5.0 6.0 4.75 2.8 −35 −35 −35 −35 −0.3 −0.3 −0.3 −0.3 −0.3 −0.3 −0.3 Max 50 50 5.25 5.25 +35 +35 +35 +35 VBAT + 0.3 VBAT + 0.3 VIO + 0.3 VIO + 0.3 VIO + 0.3 VIO + 0.3 VIO + 0.3 15 +125 +150 Unit V V V V V V V V V V V V V V V pF °C °C 1. In the sleep mode, all relevant parameters are guaranteed only for VBAT > 6 V. For VBAT between 5 V and 6 V, no power−on−reset will occur and the functionality is also guaranteed, but some parameters might get slightly out of the specification − e.g. the wakeup detection thresholds. Table 7. THERMAL CHARACTERISTICS Symbol Rth(vj−a) Rth(vj−a) Parameter Thermal Resistance from Junction−to−Ambient in SOIC−14 Package Thermal Resistance from Junction−to−Ambient in SOIC−14 Package Conditions 1S0P PCB 2S2P PCB Value 128 70 Unit K/W K/W http://onsemi.com 11 NCV7341 Characteristics The characteristics of the device are valid for operating conditions defined in Table 7 and the bus lines are considered to be loaded with RLT = 60 W, unless specified otherwise. Table 8. DC CHARACTERISTICS Symbol SUPPLY (PIN VBAT) VBAT(STB) VBAT(PWUP) IVBAT Level for Setting VBAT Undervoltage Flag Level for Setting Powerup Flag VBAT Current Consumption in Normal and Receive−Only Modes VBAT Current Consumption in Standby and Go−to−Sleep Modes. The total supply current is drawn partially from VBAT and partially from VCC. VBAT Current Consumption in Sleep Mode. The supply current is drawn from VBAT only. VCC = 5 V VCC = 0 V INH and WAKE Not Loaded 2.75 2.75 1.0 3.3 3.3 10 4.5 4.5 40 V V mA Parameter Conditions Min Typ Max Unit VVCC > 4.75 V, VVIO > 2.8 V VINH = VWAKE = VVBAT = 12 V Tamb < 100°C VVCC > 4.75 V, VVIO > 2.8 V VINH = VWAKE = VVBAT = 12 V VVCC = VINH = VVIO = 0 V VWAKE = VVBAT = 12 V Tamb < 100°C VVCC = VINH = VVIO = 0 V VWAKE = VVBAT = 12 V 10 20 8.0 12 18 mA 22.5 35 mA mA 50 mA SUPPLY (PIN VCC) VCC(SLEEP) IVCC VCC Level for Setting VCC/VIO Undervoltage Flag VCC Current Consumption in Normal or Receive−Only Mode VBAT = 12 V Normal Mode: VTxD = 0 V, i.e. Dominant Normal Mode: VTxD = VIO, i.e. Recessive (or Receive−Only Mode) Tamb < 100°C 6.5 Tamb < 100°C 0.2 0.5 12 2.75 25 2.0 3.3 55 6.0 4.5 80 10 V mA mA VCC Current Consumption in Standby and Go−to−Sleep Mode. The total supply current is drawn partially from VBAT and partially from VCC. VCC Current Consumption in Sleep Mode SUPPLY (PIN VIO) VIO(SLEEP) IVIO VIO Level for Setting VCC/VIO Undervoltage Flag VIO Current Consumption in Normal or Receive−Only Mode 17.5 19.5 1.0 2.0 mA mA mA mA 0.9 Normal Mode: VTxD = 0V, i.e. Dominant Normal Mode: VTxD = VIO, i.e. Recessive (or Receive−Only mode) Tamb < 100°C 0 100 0 1.6 350 0.2 2.0 1000 1.0 V mA mA VIO Current Consumption in Standby or Sleep Mode TRANSMITTER DATA INPUT (PIN TxD) VIH VIL IIH High−Level Input Voltage Low−Level Input Voltage High−Level Input Current 1.0 0 5.0 mA mA Output Recessive Output Dominant VTxD = VVIO 0.7VVIO −0.3 −5.0 − − 0 VIO + 0.3 0.3VVIO +5.0 V V mA http://onsemi.com 12 NCV7341 Table 8. DC CHARACTERISTICS Symbol Parameter Conditions Min Typ Max Unit TRANSMITTER DATA INPUT (PIN TxD) IIL Ci VIH VIL IIH IIL Ci IOH IOL Low−Level Input Current Input Capacitance VTxD = 0.3 VVIO Not Tested −70 1.0 −250 5.0 −500 10 mA pF STANDBY AND ENABLE INPUTS (PINS STB AND EN) High−Level Input Voltage Low−Level Input Voltage High−Level Input Current Low−Level Input Current Input Capacitance VSTB = VEN = 0.7VVIO VSTB = VEN = 0 V 0.7VVIO −0.3 1.0 −0.5 1.0 − − 5.0 0 5.0 VIO + 0.3 0.3VVIO 10 5.0 10 V V mA mA pF RECEIVER DATA OUTPUT (PIN RxD) High−Level Output Current Low−Level Output Current VRxD = VVIO − 0.4 V VVIO = VVCC VRxD = 0.4 V VTxD = 0 V Bus is Dominant −1.0 2.0 −3.0 5.0 −6.0 12 mA mA FLAG INDICATION OUTPUT (PIN ERR) IOH IOL IIH IIL Vthreshold High−Level Output Current Low−Level Output Current VERR = VVIO − 0.4 V VVIO = VVCC VERR = 0.4 V VWAKE = VVBAT − 1.9 V VWAKE = VVBAT − 3.1 V Sleep or Standby Mode −4.0 100 −20 200 −50 350 mA mA LOCAL WAKE−UP INPUT (PIN WAKE) High−Level Input Current Low−Level Input Current Threshold of the Local Wake−up Comparator −1.0 1.0 VVBAT − 3V −5.0 5.0 VVBAT − 2.5 V −10 10 VVBAT − 2V mA mA V INHIBIT OUTPUT (PIN INH) VHDROP ILEAK High Level Voltage Drop Leakage Current in Sleep Mode IINH = −180 mA Tamb < 100°C VTxD = VVCC; No Load, Normal Mode VTxD = VVCC; No Load, Standby Mode −35 V < VCANH < +35 V; 0 V < VCC < 5.25 V −35 V < VCANL < +35 V; 0 V < VVCC < 5.25 V VTxD = 0 V VTxD = 0 V VTxD = 0 V; Dominant; 42.5 W < RLT < 60 W VTxD = VCC; Recessive; No Load VCANH = 0 V; VTxD = 0 V 50 0 0 200 − − 800 5.0 1.0 mV mA mA BUS LINES (PINS CANH AND CANL) Vo(reces) (norm) Vo(reces) (stby) Io(reces) (CANH) Io(reces) (CANL) Vo(dom) (CANH) Vo(dom) (CANL) Vo(dif) (bus_dom) Vo(dif) (bus_rec) Io(sc) (CANH) Recessive Bus Voltage Recessive Bus Voltage Recessive Output Current at Pin CANH Recessive Output Current at Pin CANL Dominant output Voltage at Pin CANH Dominant Output Voltage at Pin CANL Differential Bus Output Voltage (VCANH − VCANL) Differential Bus Output Voltage (VCANH − VCANL) Short−Circuit Output Current at Pin CANH 2.0 −100 −2.5 −2.5 3.0 0. 5 1.5 −120 −45 2.5 0 − − 3.6 1.4 2.25 0 −70 3.0 100 +2.5 +2.5 4.25 1.75 3.0 +50 −120 V mV mA mA V V V mV mA http://onsemi.com 13 NCV7341 Table 8. DC CHARACTERISTICS Symbol Parameter Conditions Min Typ Max Unit BUS LINES (PINS CANH AND CANL) Io(sc) (CANL) Vi(dif) (th) Vihcm(dif) (th) Short−Circuit Output Current at Pin CANL Differential Receiver Threshold Voltage (see Figure 7) Differential Receiver Threshold Voltage for High Common−Mode (see Figure 7) Differential Receiver Input Voltage Hysteresis (see Figure 7) Differential Receiver Input Voltage for Bus Wake−up Detection (in Sleep or Standby Mode) Common−Mode Input Resistance at Pin CANH Common−Mode Input Resistance at Pin CANL Matching between Pin CANH and Pin CANL Common Mode Input Resistance Differential Input Resistance Input Capacitance at Pin CANH Input Capacitance at Pin CANL Differential Input Capacitance VTxD = VCC VTxD = VCC VTxD = VCC Normal mode; −500 mA < ISPLIT < 500 mA Standby Mode −27 V < VSPLIT < 40 V Standby Mode −27 V < VSPLIT < 40 V Tamb < 100°C ISPLIT(lim) VSPLIT Limitation Current (Absolute Value) Normal Mode 0.3 x VCC −50 −5.0 VCANH = VCANL VCANL = 42 V; VTxD = 0 V −12 V < VCANL < +12 V −12 V < VCANH < +12 V −35 V < VCANL < +35 V −35 V < VCANH < +35 V −35 V < VCANL < +35 V −35V 1.4 V Vdif(CAN) > 1.2 V VBAT = 12 V VBAT = 12 V Setup According to Figure 8 Setup According to Figure 8 Setup According to Figure 8 Setup According to Figure 8 Setup According to Figure 8 40 30 25 40 90 85 60 55 65 130 105 105 105 105 230 ns ns ns ns ns td(dom−rec) Setup According to Figure 8 90 140 245 ns tUV(VCC) tUV(VIO) tdom(TxD) th(min) tdom trec tWAKE 5.0 5.0 300 15 0.75 0.75 0.75 5.0 10 10 600 35 2.5 3.0 2.5 25 12.5 12.5 1000 50 5.0 5.8 5.0 50 ms ms ms ms ms ms ms ms MEASUREMENT DEFINITIONS AND SETUPS recessive dominant 50% recessive 50% TxD CANH CANL Vi(dif) = VCANH − V CANL 0.9V 0.5V RxD 0.3 X V CC 0.7 x VCC td(TxD−BUSon) tpd(rec−dom) td(TxD−BUSoff) td(BUSon−RxD) t pd(dom−rec) td(BUSoff−RxD) PC20060915.2 Figure 6. Timing Diagram for AC Characteristics http://onsemi.com 15 NCV7341 VRxD High Low Hysteresis PC20040829.7 0.5 0.9 Vi(dif)(hys) Figure 7. Hysteresis of the Receiver +5V 47 m F 100 nF 10 nF 1 kW +12V Vio EN STB ERR Generator TxD RxD 5 6 3 Vcc INH VBAT 7 10 9 WAKE CANH NCV7341 14 8 1 4 13 RLT 11 VSPLIT 60 W CLT 100 pF 2 12 CANL 15 pF GND PC20060921.6 Figure 8. Test Circuit for Timing Characteristics +5V 47 mF 100 nF 10 nF 1 kW Vio EN STB ERR TxD RxD 15 pF 5 6 3 Vcc INH VBAT 7 10 9 WAKE CANH 10 nF Transient Generator NCV7341 14 8 1 4 13 1 nF 11 VSPLIT 2 12 CANL 1 nF PC20060921.5 GND Figure 9. Test Circuit for Automotive Transients http://onsemi.com 16 NCV7341 +5V 47 m F 100 nF 10 nF Vio EN STB ERR Generator TxD RxD 15pF 5 6 3 1 kW +12V Vcc INH VBAT 7 10 13 CANH 6.2 kW 10 nF Active Probe Spectrum Anayzer NCV7341 14 8 1 4 CANL 12 6.2 kW 30 W 11 VSPLIT WAKE 2 9 47nF PC20060921.7 GND Figure 10. Basic Test Setup for Conducted Emission Measurement DEVICE ORDERING INFORMATION Part Number NCV7341D21G NCV7341D21R2G Temperature Range −40°C − 125°C −40°C − 125°C Package Type SOIC−14 (Pb−Free) SOIC−14 (Pb−Free) Shipping† 55 Tube / Tray 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 17 30 W NCV7341 SOIC 14 CASE 751AP−01 ISSUE A ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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